JPH0673378B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0673378B2 JPH0673378B2 JP58018438A JP1843883A JPH0673378B2 JP H0673378 B2 JPH0673378 B2 JP H0673378B2 JP 58018438 A JP58018438 A JP 58018438A JP 1843883 A JP1843883 A JP 1843883A JP H0673378 B2 JPH0673378 B2 JP H0673378B2
- Authority
- JP
- Japan
- Prior art keywords
- diffusion region
- contacts
- source
- drain
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims 4
- 238000009792 diffusion process Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000013256 coordination polymer Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】 本発明は、MOS電界効果トランジスタ（MOSFET）のパタ
ーン形状に関する。The present invention relates to a pattern shape of a MOS field effect transistor (MOSFET).
従来のＭSFETは、第一図に示すごとく、ソース，ドレ
インともに一括してソース・ドレインのアルミ配線部と
ソース・ドレインの拡散領域とを接続するコンタクト
（以下、CFコンタクトという）を設け櫛形に配置された
部分にはCFコンタクトもソース・ドレインのアルミ配線
部とソース・ドレインの拡散領域の形成された基板とを
接続するコンタクト（以下、CVコンタクトという）もと
られていないため櫛形部分でのドレイン抵抗及びソース
抵抗による影響で、トランジスタの駆動能力が低下し、
また基板の電位がドレインからCVコンタクトとチャネル
間に分布する寄生抵抗を通り基板へ流れ込む電流の影響
で上昇しオン耐圧が低下するという欠点を有する。な
お、上記内容については、既に、ＴRU TYABE,KEN Y
AMAGUCHI,SHJIR ASAI,“A Numerical Model of Vva
lance Breakdown in MSFETs"IEEE Trans Election De
vices,VOL.ED−25,PP.825−832等に報告されている。As shown in FIG. 1, the conventional MSFET is provided with contacts (hereinafter referred to as CF contacts) that connect the source / drain aluminum wiring portion and the source / drain diffusion regions together in a comb shape. Since the CF contact is not formed in the contacted part, which connects the source / drain aluminum wiring part and the substrate in which the source / drain diffusion region is formed (hereinafter referred to as CV contact), the drain in the comb-shaped part Due to the effect of resistance and source resistance, the driving ability of the transistor decreases.
In addition, the potential of the substrate rises due to the influence of the current flowing from the drain to the substrate through the parasitic resistance distributed between the CV contact and the channel, and the on-breakdown voltage decreases. Regarding the above contents, TRU TYABE, KEN Y
AMAGUCHI, SHJIR ASAI, “A Numerical Model of Vva
lance Breakdown in MSFETs "IEEE Trans Election De
vices, VOL.ED-25, PP.825-832, etc.
本発明は、かかる欠点を鑑みてソースとドレインが交互
に櫛形に配置されたＭSFETのパターンにおいて、櫛形
部分のソース及びドレインにCFコンタクトを設け、かつ
ソース領域にはCVコンタクトをCFコンタクトの間に設け
ることによりＭSFETの駆動能力及び耐圧の低下を防止
することを目的としたＭSFETのパターン形状である。In view of the above drawbacks, the present invention provides a CF contact for the source and drain of the comb-shaped portion in the pattern of the MSFET in which the source and the drain are alternately arranged in a comb shape, and a CV contact between the CF contact in the source region. This is the pattern shape of the MSFET for the purpose of preventing the driving capability and the breakdown voltage of the MSFET from being lowered by providing them.
以下実施例に基づいて本発明を詳しく説明する。第２図
に本発明の具体的な一構成例を示す。第２図において、
１はゲートのポリシリコン配線、２はフィールド領域、
３はCFコンタクト、４はCVコンタクト、５はドレインア
ルミ配線、６はソースアルミ配線、７はゲートアルミ配
線、８はゲートのアルミ配線とポリシリコン配線とのコ
ンタクト（以下、CPコンタクトという）である。第２図
のＭSFETでは、CFコンタクト３の存在により、ソース
電流ドレイン電流は拡散領域を流れる距離が短くなりソ
ース抵抗ドレイン抵抗は低くなる。またCVコンタクト４
の存在によりバックゲートバイアスを低減することが可
能となる。ゆえにＭSFETの駆動能力及び耐圧の低下を
防ぐことができる。Hereinafter, the present invention will be described in detail based on examples. FIG. 2 shows a specific configuration example of the present invention. In FIG.
1 is a gate polysilicon wiring, 2 is a field region,
3 is a CF contact, 4 is a CV contact, 5 is a drain aluminum wiring, 6 is a source aluminum wiring, 7 is a gate aluminum wiring, and 8 is a contact between a gate aluminum wiring and a polysilicon wiring (hereinafter referred to as a CP contact). . In the MSFET of FIG. 2, due to the presence of the CF contact 3, the source current and the drain current have a shorter distance flowing through the diffusion region, and the source resistance and the drain resistance are lower. Also CV contact 4
It becomes possible to reduce the back gate bias due to the presence of. Therefore, it is possible to prevent the driving capability and breakdown voltage of the MSFET from decreasing.
本発明は、ソース及びドレインが交互に櫛形に配置され
たＭSFETにおいて、ソース電極のコンタクトと基板の
コンタクトを交互に配置することにより、ソース抵抗を
低下させ基板の電位を安定化させるとともに、寄生トラ
ンジスタによるラッチアップを抑制することができると
いうすぐれた効果を有するものである。According to the present invention, in the MSFET in which the source and the drain are alternately arranged in a comb shape, the source electrode contact and the substrate contact are alternately arranged to lower the source resistance and stabilize the substrate potential, and the parasitic transistor. It has an excellent effect that the latch-up due to
第１図は従来のＭSFETのパターン形状、第２図は本発
明によるＭSFETのパターン形状。 １……ゲートのポリシリコン配線 ２……フイールド領域 ３……CFコンタクト ４……CVコンタクト ５……ドレインアルミ配線 ６……ソースアルミ配線 ７……ゲートアルミ配線 ８……CPコンタクトFIG. 1 shows the pattern shape of the conventional MSFET, and FIG. 2 shows the pattern shape of the MSFET according to the present invention. 1 …… Gate polysilicon wiring 2 …… Field region 3 …… CF contact 4 …… CV contact 5 …… Drain aluminum wiring 6 …… Source aluminum wiring 7 …… Gate aluminum wiring 8 …… CP contact
Claims (2)
つ略平行に配置された複数のゲート電極と、前記第１の
方向に沿って細長い形状を有し、かつ前記複数のゲート
電極間に配置されたソース拡散領域及びドレイン拡散領
域と、前記ソース拡散領域に電位を印加する配線と前記
ソース拡散領域とを電気的に接続するために、前記第１
の方向に沿って前記ソース拡散領域内に複数個設けられ
た第１のコンタクトとを備えた半導体装置において、 前記ソース拡散領域の形成された基板に電位を印加する
配線と前記基板とを電気的に接続するために、前記第１
の方向に沿って前記ソース拡散領域内に複数個設けられ
た第２のコンタクトを有し、隣合う前記第１のコンタク
トの間に前記第１のコンタクトと離間して前記第２のコ
ンタクトを配置し、 前記ドレイン拡散領域に電位を印加する配線と前記ドレ
イン拡散領域とを電気的に接続するために、前記第１の
方向に沿って前記ドレイン拡散領域内に複数個設けられ
た第３のコンタクトとを有してなることを特徴とする半
導体装置。1. A plurality of gate electrodes having an elongated shape along a first direction and arranged substantially in parallel, and an elongated shape along the first direction, and the plurality of gates. In order to electrically connect the source diffusion region and the drain diffusion region arranged between the electrodes, the wiring for applying a potential to the source diffusion region and the source diffusion region,
In a semiconductor device having a plurality of first contacts provided in the source diffusion region along the direction of, and electrically connecting a wiring for applying a potential to the substrate in which the source diffusion region is formed and the substrate. The first to connect to
A plurality of second contacts are provided in the source diffusion region along the direction of, and the second contacts are arranged between the first contacts adjacent to each other and apart from the first contacts. And a plurality of third contacts provided in the drain diffusion region along the first direction to electrically connect the wiring for applying a potential to the drain diffusion region and the drain diffusion region. A semiconductor device comprising:
記第３のコンタクトに対応する位置に屈曲部を有するこ
とを特徴とする特許請求の範囲第１項記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the gate electrode has a bent portion at a position corresponding to the first, second, and third contacts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58018438A JPH0673378B2 (en) | 1983-02-07 | 1983-02-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58018438A JPH0673378B2 (en) | 1983-02-07 | 1983-02-07 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7159151A Division JP2611687B2 (en) | 1995-06-26 | 1995-06-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59144173A JPS59144173A (en) | 1984-08-18 |
| JPH0673378B2 true JPH0673378B2 (en) | 1994-09-14 |
Family
ID=11971642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58018438A Expired - Lifetime JPH0673378B2 (en) | 1983-02-07 | 1983-02-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0673378B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54158179A (en) * | 1978-06-02 | 1979-12-13 | Nec Corp | Semiconductor device |
| JPS5615075A (en) * | 1979-07-19 | 1981-02-13 | Pioneer Electronic Corp | Semiconductor device |
-
1983
- 1983-02-07 JP JP58018438A patent/JPH0673378B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59144173A (en) | 1984-08-18 |
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