JP2602360B2 - Field effect type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A plurality of field effect semiconductor devices which can be formed on a chip without increasing the element area, without passing drain / source wiring over the gate of the field effect semiconductor element, Another object of the present invention is to provide a field-effect semiconductor device capable of flowing a large current without lowering the integration density. The field-effect semiconductor device includes a plurality of drain wirings and a plurality of source wirings arranged alternately in a column. In the type semiconductor device, each drain wiring and source wiring have the same trapezoidal shape, and are disposed such that the oblique sides of adjacent drain wirings and source wirings are parallel to each other, and the bottom side of the trapezoidal drain wiring or A gate electrode extending in a comb-like shape from a common portion present on one of the bottom sides of the source wiring to a portion between the hypotenuse of the drain wiring and the hypotenuse of the source wiring, Each of the oblique sides of the drain wiring and the source wiring and the side of the gate electrode are arranged so as to extend in an oblique direction by changing stepwise.

[Industrial applications]

The present invention provides a plurality of field-effect semiconductor devices that can be formed on a chip without increasing the element area, for example, MIS (Metal Ins.
ulator Semiconductor).

In recent years, field-effect transistors have been used as semiconductor output elements with reduced drive current. If the on-resistance is reduced to allow a large current to flow, and the wiring becomes thicker, the element area on the chip becomes larger, and the operation speed is inevitably reduced. It has been desired to develop a semiconductor device that has solved these problems.

[Conventional technology]

Hereinafter, a MOS transistor having a typical structure among MIS transistors will be described. A semiconductor device in which a plurality of MOS transistors are connected in parallel and used in an output stage such as an amplifier has the configuration shown in FIGS. FIG. 3 is a top view showing the transistor with part of the insulating film removed, wherein 1 is a gate electrode, 2 is an aluminum wiring directly connected to a drain electrode, and 3 is an aluminum wiring directly connected to a source electrode. . FIG. 4 shows the third
FIG. 4 is a partial cross-sectional view taken along the line IV-IV in the figure and viewed in the direction of the arrow. Reference numerals 1 to 3 are the same as those in FIG. 4 denotes an insulating film, 20 denotes a drain region, and 30 denotes a source region. As shown in FIGS. 3 and 4, the drain and source wirings are connected to the respective electrodes, and each is a thick aluminum wiring. Each of the wirings enters alternately with the gate interposed therebetween, and has a smaller thickness from the connection position of the same type of adjacent electrode to the tip. This is the source
This is for realizing a uniform current density over the entire length of the drain electrode. In FIG. 3, the current flows from the top to the bottom of the figure, and the gates are arranged in the same width in the form of teeth of a comb. Therefore, the transistor elements formed by the gate, the drain and the source are connected in parallel, so that a large current can be handled as a whole.

In FIG. 3, the parasitic capacitance increases because the drain wiring 2 passes over the gate electrode 1. Therefore, an improved type shown in FIG. 5 was studied. In FIG. 5, the interval between the comb teeth forming the gate is increased so that the drain and source wirings 2 and 3 do not intersect on the gate electrode 1.

[Problems to be solved by the invention]

In the configuration shown in FIG. 3, since the parasitic capacitance is formed in the region where the gate and the drain or the gate and the source overlap, the capacitance between the gate and the drain and between the gate and the source are increased, and the operation speed can be increased. There were no drawbacks. In FIG. 5, the operation speed was cleared, but the comb teeth of the gate required a wide interval, which caused a disadvantage that the element area on the chip became large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which can solve the above-mentioned drawbacks and can flow a large current without passing a drain-source wiring over a gate of a field-effect type semiconductor element and without reducing the integration density. Is to do.

[Means for solving the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention. In FIG. 1, 1-1 and 1-2 indicate gate electrodes, 2 indicates a drain electrode wiring, 3 indicates a source electrode wiring, and 5 indicates the direction of current.

In a field-effect semiconductor device in which a plurality of drain wirings 2 and a plurality of source wirings 3 are alternately arranged in a column, each drain wiring 2 and source wiring 3 have the same trapezoidal shape, and the adjacent drain wirings have the same trapezoidal shape. The oblique sides of the wiring 2 and the source wiring 3 are arranged so as to be parallel to each other, and the oblique side of the drain wiring and the source It has gate electrodes 1-1 and 1-2 extending in a comb-like shape between the oblique sides of the wiring, and the oblique sides of the drain wiring 2 and the source wiring 3 and the gate electrodes 1-1 and 1-2. The sides are arranged so as to extend in an oblique direction by changing stepwise.

[Action]

In the present invention, as shown in FIG. 1, since the source / drain and gate of each semiconductor element connected in parallel are formed in parallel and non-parallel to other transistors, the semiconductor element is viewed as a single transistor. In this case, the distance between the gate electrode and the drain / source electrode wiring can be kept small. Therefore, a semiconductor device for a large current can be obtained without increasing the element area on the chip.

〔Example〕

FIGS. 2 (a) and 2 (b) are diagrams showing the configuration of a MOS transistor as an embodiment of the present invention. In FIG. 2A, the gate electrodes 1-1 and 1-2 are parallel to the wirings 2 and 3 of the source and drain electrodes, and the gate electrodes and the like of adjacent elements are formed non-parallel to each other. I have. The width of the wiring between the gate electrode and the source / drain electrode has a width change that forms a small inclination of about 0.5% in the horizontal direction with respect to the length in the vertical direction.

FIG. 2 (b) is a view showing a sectional structure of the embodiment shown in FIG. 2 (a). In FIG. 2 (b), a P-type source region 30-1, 30-2... And drain regions 20-1, 20-2. A gate oxide film (SiO ₂ ) 4-1, 4-2 is formed on a region (channel region) between the source region 30 and the drain region 20.
Are formed via the gate electrodes 1-1, 1-2,. Also, on the drain region 20 and the source region 30, a drain electrode 2-1, 2-2,... And source electrodes 3-1, 3-2,.

Then, the region 20-1, the source region 30-1, the drain electrode 2-1 and the source electrode 3-1, which constitute one transistor, are formed.
1. The gate electrode 1-1 is laid out non-parallel to that of the other transistors as shown in FIG. 2 (a).

In order to facilitate the design of the shape of each electrode wiring shown in FIG. 2 (a), no oblique side is provided in each region and each electrode, and the width of each parallel side is changed stepwise. I have.

In the MOS transistor of this embodiment configured as described above, the gate electrodes 1-1, 1-2,..., The source electrode 3 and the drain electrode 2 do not overlap, no parasitic capacitance is formed, and There is no increase in size.

In addition, since the change of each electrode width is stepped,
Manufacturing is facilitated.

The MOS (Metal Oxide Semiconductor) has been described as an embodiment of the present invention.
onductor) type transistor, but other MIS (Metal Insulator Semiconductor) type transistors and MES (M
Even in the case of a field effect transistor (FET) such as an etal semiconductor type transistor, a similar excellent effect can be obtained by adopting a similar configuration.

〔The invention's effect〕

As described above, according to the present invention, it is possible to obtain an MIS type semiconductor device in which the gate electrode does not pass over the drain / source electrode and a large current can flow without significantly increasing the element area. Since the capacitance between the drain wiring and the gate region does not increase, it is effective for higher frequency signals.

[Brief description of the drawings]

 FIG. 1 is a diagram showing a principle configuration of the present invention, FIGS. 2 (a) and 2 (b) are diagrams showing a configuration of an embodiment of the present invention, FIG. 3 is a diagram showing a configuration of a conventional apparatus, FIG. FIG. 3 is a partial sectional view of FIG. 3, and FIG. 5 is a view showing a configuration of another conventional apparatus. 1-1, 1-2 ... gate electrode 2 ... drain electrode 3 ... source electrode 5 ... direction of current

Claims (1)

(57) [Claims] In a field effect type semiconductor device in which a plurality of drain wirings and a plurality of source wirings are alternately arranged in a column, each drain wiring and a source wiring have the same trapezoidal shape and are adjacent to each other. The oblique sides of the drain line and the source line are arranged so that the oblique sides of the drain line and the source line are parallel to each other, and the oblique side of the drain line and the source line A gate electrode extending in a comb-like shape between the hypotenuse and each of the hypotenuses of the drain wiring and the source wiring and a side of the gate electrode extending in an oblique direction by changing in a step shape; The field effect type semiconductor device characterized by being arranged as follows.