JPH0237114B2 - - Google Patents
Info
- Publication number
- JPH0237114B2 JPH0237114B2 JP54165953A JP16595379A JPH0237114B2 JP H0237114 B2 JPH0237114 B2 JP H0237114B2 JP 54165953 A JP54165953 A JP 54165953A JP 16595379 A JP16595379 A JP 16595379A JP H0237114 B2 JPH0237114 B2 JP H0237114B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- source
- electrode
- field effect
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 15
- 230000010354 integration Effects 0.000 description 8
- 239000000758 substrate Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は絶縁ゲート型電界効果トランジスタに
かかり、特に高集積化に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to insulated gate field effect transistors, and particularly relates to high integration.
従来の絶縁ゲート型電界効果トランジスタの断
面構造を第１図ａに示す。１はＰ導電型基板であ
り、ベースと呼ばれる領域である。２および３は
各々N+導電型ソースおよびドレーンである。４，
５および各々ゲート電極、ソース電極およびドレ
ーン電極である。絶縁ゲート型電界効果トランジ
スタは、通常、ベース領域１とソース領域２は短
絡される。Ｐ＋導電型領域７は、ベース領域１と
電極５とのコンタクトを取るために設けられてい
る。８は絶縁膜である。１１および１２は絶縁膜
ゲート型電界効果トランジスタの一部分を示しソ
ース、ドレーンおよびゲートを有する素子単位で
あり、それぞれを素子部１および素子部２と呼
ぶ。絶縁ゲート型電界効果トランジスタは、高入
力インピーダンスである為、高利得を得ることが
できるが、大電力用素子として使われる場合さら
に高利得を得る必要があり、すなわち相互コンダ
クタンス（gm）を大きくする必要がある。絶縁
ゲート型電界効果トランジスタの直線領域におけ
る相互コンダクタンスは次式で示される。 A cross-sectional structure of a conventional insulated gate field effect transistor is shown in FIG. 1a. 1 is a P-conductivity type substrate, and is a region called a base. 2 and 3 are N + conductivity type source and drain, respectively. 4,
5 and a gate electrode, a source electrode, and a drain electrode, respectively. In an insulated gate field effect transistor, base region 1 and source region 2 are usually short-circuited. P+ conductivity type region 7 is provided to make contact between base region 1 and electrode 5. 8 is an insulating film. Reference numerals 11 and 12 indicate parts of an insulating film gate type field effect transistor, which are element units having a source, a drain, and a gate, and are referred to as an element part 1 and an element part 2, respectively. Insulated gate field effect transistors have high input impedance, so they can obtain high gain, but when used as high power devices, it is necessary to obtain even higher gain, which means that the transconductance (gm) must be increased. There is a need. The mutual conductance in the linear region of an insulated gate field effect transistor is expressed by the following equation.
gm＝Ｗ／Ｌ・μ・ε／tox・VD ………(1)
ここで
Ｌ：ゲート長、
Ｗ：ゲート幅、
μ：キヤリアの易動度、
σ：酸化膜の誘電率
tpx：ゲート酸化膜厚、
VD：ドレイン電圧
前記(1)式で大きな相互コンダクタンスを得るた
めには、ゲート酸化膜厚を一定とした場合Ｗ／Ｌ
を大きくすることである。チツプサイズを大きく
することは、コスト上昇、歩留低下につながるた
め、チツプサイズを大きくせず、高集積化をはか
り大きなＷ／Ｌを得ることが必要となる。高集積
化の手段のひとつとして、ソースおよびドレーン
が微細に入り組んだくし形構造があり、従来の、
くし形構造で第１図ａに対応する絶縁ゲート型電
界効果トランジスタの平面図を第１図ｂに示す。
２および３は、N+導電型ソースおよびドレーン
である。４はゲート電極である。７はＰ＋導電型
領域である。９はソース電極およびベース電極を
取り出し、さらにソースおよびベースを電気的に
短絡するためのコンタクト窓であり、また、１０
はドレーン電極を取り出すためのコンタクト窓で
ある。１１および１２は、絶縁ゲート型電界効果
トランジスタの一部分でありそれぞれ第１素子部
および第２素子部を示す。gm=W/L・μ・ε/tox・V D ………(1) where L: gate length, W: gate width, μ: carrier mobility, σ: dielectric constant of oxide film t px : Gate oxide film thickness, V D : Drain voltage In order to obtain a large mutual conductance using the above equation (1), W/L is required when the gate oxide film thickness is constant.
The goal is to increase the Increasing the chip size leads to an increase in cost and a decrease in yield, so it is necessary to achieve high integration and obtain a large W/L without increasing the chip size. One of the means of achieving high integration is a comb-shaped structure in which sources and drains are minutely intricate.
A plan view of an insulated gate field effect transistor corresponding to FIG. 1a with a comb-shaped structure is shown in FIG. 1b.
2 and 3 are N + conductivity type source and drain. 4 is a gate electrode. 7 is a P+ conductivity type region. 9 is a contact window for taking out the source electrode and the base electrode and further electrically short-circuiting the source and the base;
is a contact window for taking out the drain electrode. Reference numerals 11 and 12 are parts of an insulated gate field effect transistor, and indicate a first element part and a second element part, respectively.
第１図ａおよび第１図ｂに示した従来のくし型
構造絶縁ゲート型電界効果トランジスタでは第１
素子部１１と第２素子部１２のソース２がＰ＋導
電型領域７によつて分離されていたため、ソース
電極およびベース電極５のコンタクト窓９は、Ｐ
＋導電型領域７以上の巾を必要とし、具体的に
は、第１素子部１１および第２素子部１２のソー
ス２の巾およびＰ＋導電型領域７の巾をそれぞれ
6μｍとしたとき、第１素子部１１におけるソー
ス２の左端から第２素子部１２におけるソース２
の右端までの距離は18μｍ必要であり、またソー
ス電極およびベース電極５のコンタクト窓９の巾
は12μｍ程度必要であつた。このようにソース電
極およびドレーン電極５のコンタクト窓９が、Ｐ
＋導電型領域７以上の巾を必要としていたこと
が、絶縁ゲート型電界効果トランジスタの高集積
化を阻害していた大きな要因であつた。 In the conventional comb-structure insulated gate field effect transistor shown in FIGS. 1a and 1b, the first
Since the sources 2 of the element section 11 and the second element section 12 were separated by the P+ conductivity type region 7, the contact window 9 of the source electrode and the base electrode 5 was
The width of the + conductivity type region 7 or more is required, and specifically, the width of the source 2 and the width of the P+ conductivity type region 7 of the first element part 11 and the second element part 12 are required respectively.
6 μm, from the left end of the source 2 in the first element section 11 to the source 2 in the second element section 12
The distance to the right end of the contact window 9 was required to be 18 μm, and the width of the contact window 9 of the source electrode and base electrode 5 was approximately 12 μm. In this way, the contact windows 9 of the source and drain electrodes 5 are
The fact that the width of the + conductivity type region was required to be 7 or more was a major factor that hindered the high integration of insulated gate field effect transistors.
本発明の目的は、ソース電極およびベース電極
５のコンタクト窓９の巾を従来より狭くしても第
１素子部１１および第２素子部１２のソース電極
およびベース電極５を取り出すことが出き、かつ
第１素子部１１および第２素子部１２のソース２
間の巾を狭くすることが可能な絶縁ゲート型電界
効果トランジスタを提供することにある。 An object of the present invention is to make it possible to take out the source electrode and base electrode 5 of the first element part 11 and the second element part 12 even if the width of the contact window 9 of the source electrode and base electrode 5 is narrower than before. and the source 2 of the first element section 11 and the second element section 12
An object of the present invention is to provide an insulated gate field effect transistor that can reduce the width between the gates.
本発明の特徴は例えば、絶縁ゲート型電界効果
トランジスタの高集積化を阻害していた第１の素
子部１１および第２の素子部１２のそれぞれのソ
ース２を分離していたＰ＋導電型領域７をソース
２に沿つて連続には設けず、Ｐ＋導電型領域７を
ソース２に沿つて点状に設け、第１素子部１１お
よび第２素子部１２のソース２を分断しないこと
にあり、本発明によりＰ＋導電型領域７よりも、
ソース電極およびドレーン電極５のコンタクト窓
９の巾が、たとえ狭くなつても、第１素子部１１
および第２素子部１２のソース２およびベース１
の電極を取り出すことができ、さらにソース電極
およびベース電極５のコンタクト窓９巾および、
第１素子部１１および第２素子部１２のソース２
間の巾を狭くすることができ、もつて絶縁ゲート
型電界効果トランジスタの高集積化が可能とな
る。 A feature of the present invention is, for example, the P+ conductivity type region 7 that separates the sources 2 of the first element part 11 and the second element part 12, which has hindered the high integration of insulated gate field effect transistors. The P+ conductivity type region 7 is not provided continuously along the source 2, but is provided in a dotted manner along the source 2, and the source 2 of the first element part 11 and the second element part 12 is not separated. According to the invention, from the P+ conductivity type region 7,
Even if the width of the contact window 9 of the source electrode and drain electrode 5 becomes narrower, the first element part 11
and source 2 and base 1 of second element section 12
electrodes can be taken out, and the contact window 9 width of the source electrode and base electrode 5 and
Source 2 of the first element section 11 and the second element section 12
The width between them can be narrowed, thereby making it possible to highly integrate insulated gate field effect transistors.
次に、本発明を実施例を参照して説明する。 Next, the present invention will be explained with reference to examples.
第２図ａおよび第２図ｂは、本発明の第１の実
施例における断面図および平面図である。１１は
Ｐ導電型基板であり、ベースと呼ばれる領域であ
る。１２および１３は各々Ｎ導電型ソースおよび
ドレーンである。１４，１５および１６は各々ゲ
ート電極、ソース電極およびドレーン電極であ
る。１７はソース１２に沿つて点状に（平面的に
数ブロツクに分けて）設けられたＰ＋導電型領域
である。１８は絶縁膜である。１９はソース電極
およびベース電極１５のコンタクト窓であり、２
０はドレーン電極１６のコンタクト窓である。２
１および２２は各々第１素子部および第２素子部
と呼ぶ。 FIGS. 2a and 2b are a sectional view and a plan view of the first embodiment of the present invention. Reference numeral 11 is a P conductivity type substrate, which is a region called a base. 12 and 13 are an N conductivity type source and drain, respectively. 14, 15 and 16 are a gate electrode, a source electrode and a drain electrode, respectively. Reference numeral 17 denotes a P+ conductivity type region provided dotted (divided into several blocks in a plane) along the source 12. 18 is an insulating film. 19 is a contact window for the source electrode and base electrode 15;
0 is the contact window of the drain electrode 16. 2
1 and 22 are referred to as a first element section and a second element section, respectively.
第２図ａおよび第２図ｂによれば、Ｐ＋導電型
領域１７がソース１２に沿つて電気的特性を劣化
させない程度の間隔で点状に設けられ、またＰ＋
導電型領域１７が第１素子部２１および第２素子
部２２のソース１２を分断していないため、ソー
ス電極およびドレーン電極１５のコンタクト窓１
９がたとえＰ＋導電型領域１７の巾より狭くても
ソース電極およびベース電極の取り出しが可能で
あり、その結果素子部１，２１および素子部２，
２２のソース１２間の巾を狭くすることができ高
集積化が可能となる。前記したように、従来の構
造では、第１図ａおよび第１図ｂの第１素子部１
１および第２素子部１２のソース２の巾およびＰ
＋導電型領域７の巾をそれぞれ6μｍとしたとき、
第１素子部１１におけるソース２の左端から、第
２素子部１２におけるソース２の右端までの距離
は18μｍ必要であり、またソース電極およびベー
ス電極５のコンタクト窓９の巾は12μｍ程度必要
であつたが、本発明の第２図ａおよび第２図ｂに
よれば、ソース電極およびベース電極１５のコン
タクト窓１９の巾は6μｍ程度と従来構造に比べ
狭くすることができ、よつて第１素子部２１のソ
ース１２の左端から第２素子部２２のソース１２
の右端までの距離は12μｍとなり、高集積化が達
成され、同一面積チツプでの比較で従来構造に比
べ相互にコンダクタンス（gm）が約20％向上し
た。 According to FIGS. 2a and 2b, P+ conductivity type regions 17 are provided along the source 12 at intervals that do not deteriorate the electrical characteristics, and P+
Since the conductivity type region 17 does not separate the source 12 of the first element part 21 and the second element part 22, the contact window 1 of the source electrode and drain electrode 15
Even if 9 is narrower than the width of the P+ conductivity type region 17, the source electrode and the base electrode can be taken out, and as a result, the element parts 1, 21 and the element parts 2,
The width between the 22 sources 12 can be narrowed, and high integration becomes possible. As described above, in the conventional structure, the first element section 1 of FIGS. 1a and 1b
1 and the width of the source 2 of the second element section 12 and P
+ When the width of the conductivity type region 7 is each 6 μm,
The distance from the left end of the source 2 in the first element section 11 to the right end of the source 2 in the second element section 12 needs to be 18 μm, and the width of the contact window 9 of the source electrode and base electrode 5 needs to be about 12 μm. However, according to FIGS. 2a and 2b of the present invention, the width of the contact window 19 of the source electrode and base electrode 15 can be narrowed to about 6 μm compared to the conventional structure, and therefore the first element From the left end of the source 12 of the section 21 to the source 12 of the second element section 22
The distance to the right edge of the chip is 12 μm, achieving high integration, and the mutual conductance (gm) has improved by about 20% compared to the conventional structure when comparing chips with the same area.
第２図ａおよび第２図ｂでは、Ｐ＋導電型領域
１７の巾が、第１素子部２１および第２素子部２
２のソース１２の巾よりも狭く、Ｐ＋導電型領域
１７が、半導体表面上から見て、ソース１２に囲
まれた場合を示したが、Ｐ＋導電型領域１７が第
１素子部２１および第２素子部２２のソース１２
の巾より広くてもかまわない。 In FIGS. 2a and 2b, the width of the P+ conductivity type region 17 is the same as that of the first element part 21 and the second element part 2.
2, and the P+ conductivity type region 17 is surrounded by the source 12 when viewed from above the semiconductor surface. Source 12 of element section 22
It doesn't matter if it's wider than the width.
第３図ａ乃至第７図ｂは、本発明を他の構造の
絶縁ゲート型電界効果トランジスタに実施した第
２乃至第６の実施例である。 3a to 7b show second to sixth embodiments in which the present invention is applied to insulated gate field effect transistors having other structures.
これらの図において、第２図ａ、第２図ｂと同
一所は同一番号を記す。 In these figures, the same parts as in FIGS. 2a and 2b are designated by the same numbers.
第３図ａおよび第３図ｂは高耐圧化の為に有効
な、N-導電型層２３を設けたオフセツトゲート
型電界効果型トランジスタにおいて本発明を実施
した第２の実施例である。 3a and 3b show a second embodiment of the present invention in an offset gate field effect transistor provided with an N - conductivity type layer 23, which is effective for increasing the withstand voltage.
第４図ａおよび第４図ｂは、短チヤネル化の可
能な二重拡散型電界効果トランジスタにおいて本
発明を実施した第３の実施例である。第３の実施
例は前記絶縁ゲート型電界効果型トランジスタと
は異なり、Ｐ導電型拡散領域がベースとなつてい
る。２４はN-導電型基板である。 FIGS. 4a and 4b show a third embodiment in which the present invention is implemented in a double-diffused field effect transistor that can have a short channel. The third embodiment differs from the insulated gate field effect transistor in that it is based on a P-conductivity type diffusion region. 24 is an N − conductivity type substrate.
第５図ａおよび第５図ｂは、Ｖ溝が形成され電
流を縦方向に流すことにより集積度の向上を図つ
たＶ溝型電界効果トランジスタにおいて本発明を
実施した第４の実施例である。縦型構造の為、Ｖ
溝形成面の反対面にN+導電型ドレーン１３およ
びドレーン電極１６が設けられている。 Figures 5a and 5b show a fourth embodiment of the present invention in a V-groove field effect transistor in which a V-groove is formed and the degree of integration is improved by allowing current to flow vertically. . Due to the vertical structure, V
An N + conductivity type drain 13 and a drain electrode 16 are provided on the surface opposite to the groove forming surface.
第６図ａおよび第６図ｂは、二重拡散型構造で
縦型構造電界効果トランジスタにおいて本発明を
実施した第５の実施例である。 FIGS. 6a and 6b show a fifth embodiment of the invention in a vertically structured field effect transistor with a double diffused structure.
第７図ａおよび第７図ｂは、高耐圧化の為にＮ
導電型層２６が設けられ第６図ａ及び第６図ｂの
構造とは異なり、ゲート電極１４がチヤネル上に
のみ形成されているため帰還容量が小さくできる
縦型電界効果トランジスタにおいて、本発明を実
施した第６の実施例である。 Figures 7a and 7b show N
The present invention is applied to a vertical field effect transistor in which the conductivity type layer 26 is provided and the gate electrode 14 is formed only on the channel, so that the feedback capacitance can be reduced. This is the sixth example carried out.
以上述べたように、本発明によれば、多くの構
造の絶縁ゲート型電界効果トランジスタの高集積
化が可能となる。 As described above, according to the present invention, it is possible to highly integrate insulated gate field effect transistors having many structures.
なお、本発明の第１乃至第６の実施例では、Ｎ
チヤネル型電界効果トランジスタについて述べた
が、Ｐチヤネル型でも勿論かまわない。 Note that in the first to sixth embodiments of the present invention, N
Although a channel type field effect transistor has been described, a P channel type may of course be used.
第１図ａおよび第１図ｂは、従来の絶縁ゲート
型電界効果トランジスタ断面図および平面図を示
す。第２図ａおよび第２図ｂは本発明の第１の実
施例を示す絶縁ゲート型電界効果トランジスタの
断面図および平面図、第３図ａおよび第３図ｂは
本発明を他の構造の第１の絶縁ゲート型電界効果
トランジスタに実施した場合の断面図および平面
図を示す。第４図ａおよび第４図ｂはさらに第２
の絶縁ゲート型電界効果トランジスタに実施した
場合の断面図および平面図を示す。第５図ａおよ
び第５図ｂ、第６図ａおよび第６図ｂ、第７図ａ
および第７図ｂはいずれもさらに異なつた絶縁ゲ
ート型電界効果トランジスタに実施した場合の断
面図および平面図を示す。尚、図において、
１，１１……Ｐ導電型基板、２，１２……N+
導電型ソース、３，１３……N+導電型ドレーン、
４，１４……ゲート電極、５，１５……ソース電
極およびベース電極、６，１６……ドレーン電
極、７，１７……P+導電型領域、８，１８……
絶縁膜、９，１９……ソース電極およびベース電
極のコンタクト窓、１０，２０……ドレーン電極
のコンタクト窓、１１，２１……素子部１、１
２，２２……素子部２、２３……N-導電型層、
２４……N-導電型基板、２５……Ｐ導電型ベー
ス、２６……Ｎ導電型領域。
FIGS. 1a and 1b show a cross-sectional view and a plan view of a conventional insulated gate field effect transistor. 2a and 2b are cross-sectional views and plan views of an insulated gate field effect transistor according to a first embodiment of the present invention, and FIGS. 3a and 3b are sectional views and FIGS. A cross-sectional view and a plan view when implemented in a first insulated gate field effect transistor are shown. Figures 4a and 4b are further illustrated in the second diagram.
A cross-sectional view and a plan view are shown when the invention is implemented in an insulated gate field effect transistor. Figures 5a and 5b, Figures 6a and 6b, Figure 7a
and FIG. 7b each show a cross-sectional view and a plan view when implemented in further different insulated gate field effect transistors. In the figure, 1, 11...P conductivity type substrate, 2, 12...N +
conductive type source, 3,13...N + conductive type drain,
4,14...gate electrode, 5,15...source electrode and base electrode, 6,16...drain electrode, 7,17...P + conductivity type region, 8,18...
Insulating film, 9, 19... Contact window for source electrode and base electrode, 10, 20... Contact window for drain electrode, 11, 21... Element section 1, 1
2, 22...Element portion 2, 23...N - conductivity type layer,
24...N - conductivity type substrate, 25...P conductivity type base, 26...N conductivity type region.
Claims (1)
に一方向に延在して設けられた他の導電型の複数
条の第１の半導体領域と、該複数条の第１の半導
体領域のうち相隣接するものの間の前記一主面に
前記一方向に延在してそれぞれ設けられた１条以
上の第２の半導体領域と、前記第１の半導体領域
と前記第２の半導体領域との間の前記一主面上に
それぞれ前記一方向に延在して設けられた複数条
のゲート電極と、前記複数条の第１の半導体領域
に共通して接続された第１の電極と、前記第２の
半導体領域に接続された第２の電極とを有する電
界効果トランジスタにおいて、前記第２の半導体
領域は前記半導体層に少なくともその底部が接し
て設けられた前記一導電型の複数の第３の半導体
領域と前記他の導電型の複数の第４の半導体領域
とを前記一方向に交互に有し、前記第２の電極は
前記第３の半導体領域の前記一方向とは垂直な他
の方向における幅よりも狭い幅を該他の方向にお
いて有し、前記一方向に延在して前記第３の半導
体領域及び前記第４の半導体領域に共通に接続し
て設けられていることを特徴とする電界効果トラ
ンジスタ。1. A semiconductor layer of one conductivity type, a plurality of first semiconductor regions of another conductivity type extending in one direction on one main surface of the semiconductor layer, and the plurality of first semiconductor regions of the other conductivity type. one or more second semiconductor regions extending in the one direction and provided on the one main surface between adjacent regions; and the first semiconductor region and the second semiconductor region. a plurality of gate electrodes each extending in the one direction on the one main surface between the gate electrodes; and a first electrode commonly connected to the plurality of first semiconductor regions. , a field effect transistor having a second electrode connected to the second semiconductor region; The third semiconductor region and the plurality of fourth semiconductor regions of the other conductivity type are alternately arranged in the one direction, and the second electrode is perpendicular to the one direction of the third semiconductor region. It has a narrower width in the other direction than the width in the other direction, extends in the one direction, and is commonly connected to the third semiconductor region and the fourth semiconductor region. A field effect transistor featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16595379A JPS5688363A (en) | 1979-12-20 | 1979-12-20 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16595379A JPS5688363A (en) | 1979-12-20 | 1979-12-20 | Field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5688363A JPS5688363A (en) | 1981-07-17 |
| JPH0237114B2 true JPH0237114B2 (en) | 1990-08-22 |
Family
ID=15822147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16595379A Granted JPS5688363A (en) | 1979-12-20 | 1979-12-20 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5688363A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0564693U (en) * | 1992-02-03 | 1993-08-27 | 碧南特殊機械株式会社 | Drying cart for ceramic products |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58111373A (en) * | 1981-12-21 | 1983-07-02 | テキサス・インスツルメンツ・インコ−ポレイテツド | D-mos semiconductor device and method of producing same |
| JPS6076160A (en) * | 1983-10-03 | 1985-04-30 | Seiko Epson Corp | Mos type semiconductor integrated circuit |
| JPS60229368A (en) * | 1984-04-27 | 1985-11-14 | Olympus Optical Co Ltd | Solid-state image pickup device |
| US4809045A (en) * | 1985-09-30 | 1989-02-28 | General Electric Company | Insulated gate device |
| US4857977A (en) * | 1987-08-24 | 1989-08-15 | General Electric Comapny | Lateral metal-oxide-semiconductor controlled triacs |
| JPH01140773A (en) * | 1987-11-27 | 1989-06-01 | Hitachi Ltd | Insulated-gate transistor |
| JP3307481B2 (en) * | 1993-11-05 | 2002-07-24 | 三菱電機株式会社 | Semiconductor device |
| JP3120389B2 (en) | 1998-04-16 | 2000-12-25 | 日本電気株式会社 | Semiconductor device |
| DE19828494B4 (en) | 1998-06-26 | 2005-07-07 | Robert Bosch Gmbh | MOSFET device with protective device against switching through a parasitic transistor |
| EP1538678B1 (en) * | 2003-12-05 | 2008-07-16 | STMicroelectronics S.r.l. | DMOS structure and method of making the same |
| EP1538677A1 (en) | 2003-12-05 | 2005-06-08 | STMicroelectronics S.r.l. | LDMOS structure and method of making the same |
| JP5078273B2 (en) * | 2006-03-31 | 2012-11-21 | 株式会社リコー | Semiconductor device |
| JP5700649B2 (en) * | 2011-01-24 | 2015-04-15 | 旭化成エレクトロニクス株式会社 | Manufacturing method of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5045574A (en) * | 1973-08-24 | 1975-04-23 |
-
1979
- 1979-12-20 JP JP16595379A patent/JPS5688363A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5045574A (en) * | 1973-08-24 | 1975-04-23 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0564693U (en) * | 1992-02-03 | 1993-08-27 | 碧南特殊機械株式会社 | Drying cart for ceramic products |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5688363A (en) | 1981-07-17 |
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