JPS58111373A - D-mos semiconductor device and method of producing same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a D-MO8 semiconductor device, and more particularly, the present invention relates to a D-MO8 semiconductor device having a comb-shaped source back gate.
8 relating to semiconductor devices.

Description of the Prior Art D-MO8 semiconductor devices are lateral elements constructed within a semiconductor material. Generally, in the process of constructing a D-MO8 device, an N-type surface layer is taxially grown on a P-type substrate. Additionally, highly doped P-type regions are selectively formed and extend through the thickness of the epitaxial layer to provide isolation between the components by PN junctions. Next, a low level doped P-type region (D-well)
is selectively formed in an insulated and isolated part of the epitaxial growth layer where individual D-MO8 elements are made, and the D-MO8
Configure the backdate of B. for each device, a moderately doped P-type region is formed in at least a portion of the lightly doped P-type region (D-well);
Configure the D-MO8 pack r-tote.

Additionally, highly l-doped N-type regions are selectively formed. One N-type region is formed near its end within a lightly doped P-type region to form the source of the D-MOB. This allows D-M to be located between the source and the undiffused N-type epitaxial layer.
A channel region of the OB is formed. Another N-type region is formed and becomes the drain of the D-MOB. This second
The N-type region is located away from the lightly doped P-type region and along the edge of the low-level r-doped P-type region adjacent to the D-MO8 channel.

A tate oxide layer is formed over the D-MO8 channel region, the oxide is selectively removed to form through holes for the electrodes, and the metallization process is performed to form the electrodes and any necessary interconnections. It is formed. Forming such an interconnect connects the back gate to the source of the D-MO8 device.

MOB (D-MO) with double number diffusion shown below.
B) The device is parasitic in nature and has an NPN transistor. Parasitic NPN) lanzosters affect the operating voltage performance of the D-uog device. The NPN transistor has a BVD8B avalanche breakdown voltage (
It has an associated VCBEO breakdown voltage (typically 60 volts) significantly lower than VCBEO (typically 200 volts or more). The actual reverse bias voltage across the collector-emitter of an NPN transistor is BVCBO.
When the avalanche breakdown voltage is exceeded, defects are created due to destruction. Therefore, the D-MO8 device cannot be operated at voltages higher than the BYCEO breakdown voltage. However, it is desirable to operate the D-MO8 device at voltages higher than the BVCEO breakdown voltage without compromising reliability (it is therefore desirable to eliminate the parasitic NPN transistor or increase its BVCEO breakdown voltage). There is.

Park with the conventional D-MO8 device structure? - The gate and source have a comb-shaped structure to lower the resistance value of backdate and reduce the parasitic N.
None showed an arrangement pattern in which the PN l-transistor was removed.

SUMMARY OF THE INVENTION The present invention has a D-MO8 device with significantly lower resistance between the back gate electrode and the D-MO8 channel region. An epitaxial growth layer of N-type material is grown over the P-type substrate. A lightly doped P-type region is formed within the N-type layer. Zara lko, medium lko doped P! ! ! ! A region is formed within a lightly doped P-type region.

The moderately doped P-type region forms the packed r-) electrode of the D-MOS device. Two highly doped N-type regions are then formed. The first region is formed in selected portions of the lightly doped P-type region and the moderately doped P-type region. After diffusion, the highly doped N-type region is formed adjacent to and extending along the cross-section of the lightly doped P-type region. This becomes the MOS channel of the D-MOS device. A second N-type region is formed in the N-type layer extending along its cross-section at a location away from the low-level P-type region containing the D-MOS channel. The second N type region is the D-MOS of the D-MOS device.
The first N-type region forms the source of the D-MOS. During the formation process, the N-type regions within the lightly doped P-type regions are combined into a comb shape of the moderately doped regions S'. During the metallization process, the protruding source fingers extending into the moderately doped P-type regions are connected to the moderately doped P-type regions therebetween by a metallization layer. Thus, a single electrode is formed for both the packed gate and the source. This allows the source and back P of the D-MOS device to
- The surface area required for printing can be significantly reduced. Additionally, the physical distance between the active portion of the D-MOS channel and the packed date electrode is reduced. Providing a moderately r-doped P-type region extending between portions of the source type region significantly reduces the distance between the active packed date region and the packed date electrode near the gate of the D-MOS device. This can be achieved by bringing them closer together.

N-type region and pack that become the source of D-MOS? When combined in a comb-like manner with a moderately P-type region that
- The resistance between the active area of the MOS channel and the packed date electrode is significantly reduced. Furthermore, such a configuration eliminates the parasitic NPN) Lanzoster and makes the D-Mo
d device becomes operational up to its BVI)DB avalanche breakdown voltage. Therefore, the reliability of the D-MOS device is increased.

The various processing steps described above may be performed using any suitable procedure. For example, a moderately doped P-type region can be formed before forming a lightly doped pg region. Various N type or PW
Diffusion is generally used to form the regions.

An advantage of the present invention is that D-MOS with fairly high breakdown voltage
is to get the equipment.

A second advantage of the present invention is that it provides a D-MOS device with a single metal electrode for both the source and the packed gate.

Another advantage of the present invention is that it provides a D-MOS device that utilizes a very small surface area.

Another advantage of the invention is to obtain a D-MOS device in which the source and the pack date are formed in a comb-shaped structure.Another advantage of the invention is to obtain a D-MOS device in which the parasitic NPN It is to obtain.

Another advantage of the present invention is that the D-M further improves reliability.
The goal is to obtain an OS device.

Another advantage of the present invention is that it reduces the physical distance between the active D-MO8 channel area and the pack r-t.

A further advantage of the present invention is that it prevents the occurrence of pinch effects within the D-MOS channel caused by diffusion of the D-MOS source.

<Description of Examples> Hereinafter, the present invention will be described in detail in connection with Examples with reference to the drawings.

Referring to the drawings, in particular, Figure 1 (conventional D-MOS
), the silicon single crystal P-type substrate 20 has a resistivity of 10 to 20 ohm centimeters, preferably about 15 ohm centimeters. An epitaxial layer 22 is then grown on the substrate 29 and doped to have a resistivity of 5 ohm centimeters to 8 ohm centimeters, preferably <halo, 5 ohm centimeters. N-type conductivity is provided. A lightly doped P-type region 24 is shown formed within the Nfi layer 22. A moderately seeded P-type region 26 is formed by diffusion into the lightly doped P-type region 24. Area 2 @ ii, D-
This is the D-MO8 pack dirt electrode number of the MO8 device 28. Packed with a thin metal layer? -) Used for connecting the electrode 3o. The highly doped N-type region 3°2 is also
- Diffusion is performed in the middle of a lightly doped P-type region 24 using MO8 self-aligned techniques. A thin metal layer on the surface of the region 82 forms the source electrode 3 of the D-MO8 device 28.
form 4. Region 32 is lightly doped with P.
It is located in close proximity to the boundary area between type region 24 and N-type region 22. This border area is the D-MO8 channel af! It is also known as binding. Oxide layer 38 provides the necessary insulation between date electrode 40 and D-MO8 channel 36.

Another highly doped N-type region 42 is formed by diffusion within layer 22 at a location remote from region 24 and specifically remote from channel 36.

Region 42 forms the drain of the D-MO8 device 28 and has a metal electrode 44 = when a suitable voltage is present on the date electrode 40, the D-MO8 device is connected between the channel 86 and the region of layer 22. In most applications, conduction is established between regions 32 and 42 through portions of substrate 20.
Pack date electrode 30 is connected to source electrode 34 by connections being made at several points in various metal layers of the overlying integrated circuit.

The D-MO8 device 28 of FIG. 1 is shown schematically in FIG. D-MO8 device 28 has a source 48, a drain 46, a drain 50, and a back gate 52. D-MO8 device 28 essentially has a parasitic NPN transistor 54 with region 24 as the pace, region 32 as the emitter, and region 42 as the collector.

The voltage potential between the drain and source is limited by the VEBCO of the parasitic NPN) Lanzoster 54. If a voltage exceeding the VEBCO of transistor 54 is applied, catastrophic damage to D-MO8 device 28 will occur.

As shown in FIG. 8, the pattern diagram of regions 82 and 26 shows that both are rectangular, with region 26 having a substantially narrower and slightly longer shape than region 32. These regions are each provided along one long side and in close proximity to the @electrode! 4 is area 82
◇
Since the pack day 30 is a narrow area, it is placed centrally above the area 26.

The process of manufacturing a D-MO8 device 60 according to the present invention will be described in connection with FIGS. 3-7.

The D-MOS drain and date electrodes for D-MO8 device 60 are formed similar to those electrodes formed for D-MO8 device 28 (of FIG. 1). A substrate 61 similar to the substrate 20 of FIG. 1 is prepared, and a drain (not shown) similar to the drain 42 is formed on the layer 6 so that an epitaxially grown layer 62 similar to the layer 22 of FIG. 1 can be formed.
Formed in 2.

D-M08 device 8(1) 17) Other features are D-MO
8 device 28, all features other than the essential features of the present invention are omitted in FIGS. 3-7.

In FIG. 3, N-type region 62 has an oxide layer 64 grown by standard oxidation techniques. layer 62
An opening 66 is etched into the oxide layer 64 and patterned to expose a surface 68 of the oxide layer 64 . A lightly doped P-type region 70 is formed in layer 62 by diffusion.

As shown in FIG. 4, the oxide layer is grown again using an oxidation process. The surface 68 within the region of the opening 66 is
It is now covered by an oxide layer.

In FIG. 5, oxide layer 64 is again patterned and opening 12 is formed in a portion of surface 68 within lightly doped P-type region 70. In FIG. A moderately doped P layer region 74 is then formed in region 70 by diffusion through open lower 2 . Generally, the open lower portion 2 is formed with a size considerably smaller than the opening 66.

The oxidation step is carried out again and an oxide layer is grown on the surface 68, including the portions of the open lower 2 that were exposed overnight. As shown in FIG. 7, pattern formation is performed once again.
An etch is performed to form an open aperture in surface 68. Diffusion is performed into a lightly doped P-type region 70;
A highly doped N-type region 78 is formed. The position of the wall surface 80 of the oxide layer 64 is as shown in FIG.
Note that standard MO8 self-alignment techniques are utilized since this is the same location as wall 82 of 4. Moderately doped P-type region 7 as shown in FIG.
It is shown that a portion of 4 remains under N-type region 78. Dotted lines 85 and 86 indicate moderately doped P
It shows the position of the area previously occupied by the type area 1to.

As shown in FIG. 9, only a predetermined portion of the P-type region 14 is
It is covered by a mold region 78 . Region 78 is essentially rectangular and has branches or fingers 8g-98 extending outwardly from one long side of the body, over and beyond region 74. When observed from above, area 1
4 has a basically rectangular shape that is narrower in most parts than region 78 and slightly longer in the long side direction. Region 74 extends beyond the branches 88 and 93 that are farthest from each other. Branch go-as extends completely through region 74 to a point just i beyond. Surface of region 78 and branches 88-9
A metal electrode 96 is formed in a portion of the region 74 reaching up to 3. The shape of the region 74 is a rectangle, and the electrode 96 is formed in the center parallel to the longer side of the region 74.

The D-MO8 channel 98 (FIG. 7) is connected to the N-type region 18.
and extends between the portion of unaltered layer 62 and the boundary of P-type region 70 . Region 74 contains the back gate of D-MOS device 60, and region 78 contains the back gate of D-MOS device 60.
Contains the source of the O8 device 60.

Therefore, electrode 96 can connect both the back gate and the source at the same time. As can be seen by comparing FIG. 1 and FIG.
is closer than the distance of By reducing the physical distance between the backdating electrode and the channel (second
Parasitic NPN transistors (such as transistor 64 shown in the figure) can be eliminated. A gate oxide layer and a metal layer are formed over the date region over channel 98. Metallization and patterning steps are performed using standard techniques.

The shapes of the masks forming the openings Aro and 72 are shown in FIGS. 10 and 11, respectively. Figure 10 shows area 1
A mask 100 is a pattern for forming a region 74. Figure 8, Figure 9,
Geometric shapes other than patterns such as those shown in FIGS. 10 and 11 can also be used in the present invention. For example,
An oxide layer is provided in the area between dotted lines 103 and 104, leaving the oxide layer above the area, and the dotted line 10
The portion of the surface of layer 62 corresponding to the region indicated between 3 and 104 is prevented from undergoing diffusion to create region 74 . Dotted lines 106, 107, 108, 109, 112 and 1
13. Do the same between 115 and 116.

The result of these processing steps is the formation of a plurality of moderately doped regions separated from each other by region holes therein. However, the special arrangements shown in FIGS. 7 and 9 have been found to be effective.

Back as above? By creating a comb-shaped structure for the gate and source, it is possible to lower the resistance value of the back/l'' gate and eliminate the naturally formed parasitic transistor.Therefore, it is possible to use a considerably high operating voltage. This improves the reliability of the device.Furthermore, since the present invention forms a single electrode for both back-to-back and source connections, the economy of surface area is improved. It has very advantageous characteristics.Therefore, it has achieved its original purpose and is suitable for manufacturing LSI circuits in the future.
An MO8 semiconductor device can be provided.

Although the present invention has been described in particular embodiments with reference to the accompanying drawings, other modifications departing from the examples shown and inferred herein are also within the spirit of the invention. I believe it will happen.

4. Simple drawing explanation FIG. 1 is an enlarged sectional view of the Ri-MO8 device.

Figure 2 shows a D-MO8 with a parasitic NPN) transistor.
FIG. 2 is a schematic diagram of the device.

6 to 7 are enlarged cross-sectional views showing the fabrication and healing process of the D-MO8 device according to the present invention.

FIG. 8 is a layout diagram showing the source and back f-) of the D-Mol' device.

FIG. 9 is a layout diagram of the source and pack P-) of the D-MO8 device made according to the present invention.

FIG. 10 is a top view showing a part of the mask pattern used in the present invention.

FIG. 11 is a top view showing a part of the mask pattern used in the present invention.

Claims (1)

[Claims] (1) (a) step 2 of taxially growing a single crystal N-type surface layer on a substrate; (b) a selectively low-level doped P-type region in said layer; (C1 selectively forming a moderately doped P-type region within the lightly doped PW region to form a D-MO8 backdated electrode) (d) a first highly doped N region selectively along a predetermined boundary region spaced from the lightly doped Pm region;
forming a type region to form the drain of the D-MOS; (e) selectively forming a second N-type region located within the lightly doped P region; D having a plurality of fingers extending into the lightly doped P-type region and located in close proximity to the predetermined boundary region of the lightly doped P-type region to form a D-MO8 channel. - A method for manufacturing a D-MO8 semiconductor device, comprising: - forming an MO8 source. (2) the manufacturing method further comprises selectively forming a metal electrode over portions of the plurality of fingers and the moderately doped P-type region adjacent to the fingers;
The method of claim 1 including the step of interconnecting a source and said D-MO8 backdate. (3) Claims in which the manufacturing method includes the steps of selectively forming a date oxide layer over the D-MOS source and selectively forming a metal layer over the date oxide layer. Manufacturing method according to item 1. (4) The manufacturing method according to claim 1, wherein the above steps (dl and (e)) are performed simultaneously. (5) The manufacturing method according to claim 1, wherein the above steps (cl) are performed before step (d). (6) The manufacturing method according to claim 1, in which the step (b) is performed before the step (C). The manufacturing method according to claim 1. (8) The manufacturing method according to claim 1, in which the step (d) is performed before the step (e). (9) (a) The first insulated part an epitaxial layer of a conductivity type; (b) a region of a second conductivity type which is doped to a low level by diffusion; and (c) a predetermined boundary region in the layer spaced apart from the region of the second conductivity type. (d) forming a source located in close proximity to said boundary region and doping at a high level with a first diffusion forming a drain region; (d) forming a source located in close proximity to said boundary region; said second forming a channel;
A second layer highly doped by diffusion into the conductivity type region.
a region of a first conductivity type; a plurality of moderately doped second conductivity type regions within said second conductivity type regions; (f) said plurality of moderately doped second conductivity type regions and said second conductivity type regions located therebetween; A D-MO8 semiconductor device comprising: a metal electrode connecting a portion of the first conductivity type region; D-M of claim 9 having a metal r-t
O8 semiconductor device. aυ A patent claim characterized by said plurality of moderately doped P-type heads with a relatively thin moderately doped P-type head extending below said portion of said second N-type material. A D-MO8 semiconductor device in the range No. 9. α2(a) a substrate; (1)) an N-type region in the substrate; (e) a first low-level doped P-type region extending to a predetermined depth within the N-type region; (,i) a plurality of moderately doped P-type heads within said first region; a highly doped N-type region extending between the type heads; (f) each of said plurality of moderately doped P-type heads, a portion of said highly doped N-type region; and a gold layer electrode connected to each of the semiconductor devices. Q3. The semiconductor device according to claim 12, wherein the plurality of P-type head regions extend along the surface of the substrate in a predetermined direction. α-N. The plurality of P-shaped regions are connected by a relatively thin P-shaped region extending in the predetermined direction below the portion of the highly doped n+ region. A semiconductor device according to Scope 16. A haze (&) single crystal substrate; (b) an epitaxially grown single crystal N-type layer on the substrate; (C) a low level extending from the surface of the layer to the interior of the N-type layer. (d) an N-type region extending from the surface of said layer to the interior of said lightly doped P-type head; (e) an N-type region extending from the surface of said layer to the interior of said lightly doped P-type head; Extends to the inside of the P-type head area doped to the level,
(f) a plurality of moderately doped P-type heads separated from each other by portions of said N-type regions; (f) said plurality of moderately doped P-type heads sandwiched therebetween; and a metal electrode on the surface of the layer connecting portions of the N-type region. α119 (a) Two single-crystal N-type surface layers on the substrate.
taxially growing: (b) selectively forming a lightly doped P-type region over the layer; (C) selectively forming a plurality of regions within the lightly doped P-type region; (d) forming a lightly doped P-type head region to backdate the D-MOS; (d) forming a heavily doped P-type head region in the layer away from the lightly doped N-type region along its predetermined boundary region; A first highly doped N-type region is selectively formed to form the drain of the D-MOB, and a first highly doped N-type region is selectively formed in the lower doped P-layer region adjacent to the interface region. - selectively forming a second highly doped N-type region constituting an MO8 source, with a plurality of fingers extending between said plurality of moderately doped P-type regions; Create a channelD
- A method for manufacturing an MO8 semiconductor device. 17. The method of claim 16, including the step of selectively forming metal electrodes for said plurality of fingers and said plurality of moderately doped P-type regions. 17. The method of claim 16, comprising the steps of selectively forming a date oxide layer on the D-MO8 channel and selectively forming a metal layer on the oxide layer.