KR0170287B1 - Lay out method of buffer transistor - Google Patents
Lay out method of buffer transistor Download PDFInfo
- Publication number
- KR0170287B1 KR0170287B1 KR1019950054727A KR19950054727A KR0170287B1 KR 0170287 B1 KR0170287 B1 KR 0170287B1 KR 1019950054727 A KR1019950054727 A KR 1019950054727A KR 19950054727 A KR19950054727 A KR 19950054727A KR 0170287 B1 KR0170287 B1 KR 0170287B1
- Authority
- KR
- South Korea
- Prior art keywords
- buffer transistor
- transistor
- gate
- drain
- layout method
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 반도체 장치의 레이아웃방법에 관한 것으로서, 특히 채널 폭이 큰 버퍼 트랜지스터의 레이아웃방법에 관한 것으로서, N+혹은 P+층으로 소스(source) 및 드레인(drain)을 구성하고, 폴리실리콘층으로 게이트(gate)를 구성하는 버퍼 트랜지스터의 레이아웃방법에 있어서, 상기 폴리실리콘층을 사선으로 교차하도록 구성하여 상기 소스(source), 드레인(drain) 및 게이트(gate)를 구성함을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout method of a semiconductor device, and more particularly to a layout method of a buffer transistor having a large channel width, comprising a source and a drain formed of an N + or P + layer, and a polysilicon layer. In the layout method of a buffer transistor constituting a gate, the source, the drain (drain) and the gate (gate) is configured by crossing the polysilicon layer diagonally.
따라서, 사선방향으로 교차하도록 폴리실리콘을 배치함으로써 동일한 트랜지스터를 구현함에 있어 면적을 줄일 수 있는 효과를 제공한다. 또한, 트랜지스터의 채널 저항의 감소를 갖는 효과를 제공한다.Therefore, by arranging polysilicon to cross in an oblique direction, the area can be reduced in implementing the same transistor. It also provides the effect of reducing the channel resistance of the transistor.
Description
제1도는 종래 기술의 버퍼(buffer) 트랜지스터의 레이아웃을 보이는 도면이다.1 is a view showing the layout of a buffer transistor of the prior art.
제2도는 본 발명에 따른 버퍼 트랜지스터의 레이아웃 방법을 도시한 도면이다.2 is a diagram illustrating a layout method of a buffer transistor according to the present invention.
본 발명은 반도체 장치의 레이아웃방법에 관한 것으로서, 특히 채널폭이 큰 버퍼 트랜지스터의 레이아웃방법에 관한 것이다.The present invention relates to a layout method of a semiconductor device, and more particularly to a layout method of a buffer transistor having a large channel width.
반도체 장치가 점차 고집적화되고 소형화함에 따라 일정한 면적에 더 많은 트랜지스터를 구성하도록 설계가 이루어진다. 즉, 트랜지스터 등 각 소자들의 레이아웃이 조화있게 이루어져 실리콘 면적을 최소화할 필요성이 있는 것이다.As semiconductor devices become increasingly integrated and miniaturized, designs are designed to construct more transistors in a given area. In other words, the layout of each device such as a transistor is harmonized, so there is a need to minimize the silicon area.
제1도는 종래 기술의 버퍼(buffer) 트랜지스터의 레이아웃을 보이는 도면이다. 제1도에 있어서, 참조부호 100(111방향)은 소스(source)이고, 102(111방향)는 드레인(drain)이고, 104는 게이트(gate)이고, 106은 액티브(active)이다. 제1도에 도시된 트랜지스터가 채널(channel)의 폭(width)/길이(length)(이하 'W/L'라 함)가 200㎛/2㎛라고 하면, 이는 50㎛/2㎛인 폴리실리콘(polysilicon)4개로 배치된 레이아웃을 갖는다.1 is a view showing the layout of a buffer transistor of the prior art. In FIG. 1, reference numeral 100 (111 directions) is a source, 102 (111 directions) is a drain, 104 is a gate, and 106 is active. If the transistor shown in FIG. 1 has a width / length (hereinafter, 'W / L') of a channel of 200 μm / 2 μm, it is polysilicon having 50 μm / 2 μm (polysilicon) has 4 layouts.
따라서, 본 발명의 목적은 상술한 바와 같은 필요성에 입각하여 안출된 것으로서, 사선방향으로 교차하도록 폴리실리콘(polysilicon)을 배치함으로써 동일한 트랜지스터를 구현함에 있어 채널의 폭(width)을 증가하도록 하는 버퍼 트랜지스터의 레이아웃방법을 제공함에 있다.Accordingly, an object of the present invention has been made in view of the necessity as described above, and a buffer transistor for increasing the width of a channel in implementing the same transistor by arranging polysilicon to cross diagonally. To provide a layout method of.
상술한 바와 같은 목적을 달성하기 위한 버퍼 트랜지스터의 레이아웃방법은 N+혹은 P+층으로 소스(source) 및 드레인(drain)을 구성하고, 폴리실리콘층으로 게이트(gate)를 구성하는 버퍼 트랜지스터의 레이아웃방법에 있어서,The layout method of the buffer transistor for achieving the above object is the layout of the buffer transistor to form a source (drain) and drain (drain) in the N + or P + layer, and the gate (gate) in a polysilicon layer In the method,
상기 폴리실리콘층을 사선으로 교차하도록 구성하여 상기 소스(source), 드레인(drain) 및 게이트(gate)를 구성함을 특징으로 한다.The polysilicon layer is formed to cross the diagonal lines to form the source, the drain, and the gate.
이하, 첨부된 도면을 참조하여 본 발명을 보다 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described the present invention in more detail.
제2도는 본 발명에 따른 버퍼 트랜지스터의 레이아웃방법을 도시한 도면이다. 제2도에 있어서, 참조부호는 제1도와 동일한 관계로 그 설명을 생략한다. 다만, 204는 게이트를 나타낸다.2 is a diagram illustrating a layout method of a buffer transistor according to the present invention. In Fig. 2, the reference numerals are the same as in Fig. 1 and the description thereof is omitted. 204 denotes a gate.
제2도에서 보이는 바와 같이 폴리실리콘(polysilicon)을 사선으로 교차하도록 배치함으로써 제1도와 동일한 면적에 채널(channel)의 W/L가 약 370㎛/2㎛가 된다.As shown in FIG. 2, polysilicon is disposed to cross diagonally so that the W / L of the channel is about 370 µm / 2 µm in the same area as that of FIG.
상술한 바와 같이 구성한 버퍼 트랜지스터의 레이아웃방법은 사선방향으로 교차하도록 폴리실리콘을 배치함으로써 동일한 트랜지스터를 구현함에 있어 면적을 줄일 수 있는 효과를 제공한다. 또한, 트랜지스터의 채널 저항의 감소를 갖는 효과를 제공한다.The layout method of the buffer transistor configured as described above provides the effect of reducing the area in implementing the same transistor by arranging polysilicon to cross in the diagonal direction. It also provides the effect of reducing the channel resistance of the transistor.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950054727A KR0170287B1 (en) | 1995-12-22 | 1995-12-22 | Lay out method of buffer transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950054727A KR0170287B1 (en) | 1995-12-22 | 1995-12-22 | Lay out method of buffer transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970053786A KR970053786A (en) | 1997-07-31 |
| KR0170287B1 true KR0170287B1 (en) | 1999-02-01 |
Family
ID=19443284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950054727A KR0170287B1 (en) | 1995-12-22 | 1995-12-22 | Lay out method of buffer transistor |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0170287B1 (en) |
-
1995
- 1995-12-22 KR KR1019950054727A patent/KR0170287B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR970053786A (en) | 1997-07-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE60223910D1 (en) | METHOD OF MANUFACTURING SOI SEMICONDUCTOR ELEMENTS | |
| KR930006737B1 (en) | Semiconductor device | |
| KR970076043A (en) | Thin film transistor and liquid crystal display having the thin film transistor | |
| KR980006525A (en) | Semiconductor Device Semiconductor Integrated Device and Manufacturing Method of Semiconductor Device | |
| KR960002880A (en) | Silicon on Insulator (SOI) Transistors | |
| KR950004600A (en) | Polycrystalline silicon thin film transistor | |
| KR0170287B1 (en) | Lay out method of buffer transistor | |
| KR930010083B1 (en) | Semiconductor integrated circuit of standard cell system | |
| KR970053846A (en) | Transistor of electrostatic protection circuit and manufacturing method thereof | |
| KR940004807A (en) | Semiconductor integrated circuit device and manufacturing method thereof | |
| KR980006227A (en) | Semiconductor device with static electricity protection circuit | |
| KR920003550A (en) | Semiconductor devices | |
| JPH037142B2 (en) | ||
| JPS62150740A (en) | Semiconductor integrated circuit device | |
| KR930003414A (en) | Semiconductor integrated circuit device | |
| KR960030442A (en) | Power Metal Oxide Semiconductor (MOS) Transistors | |
| KR980006276A (en) | Semiconductor device having variable drain current transistor | |
| JP2978504B2 (en) | MOS transistor | |
| KR920022535A (en) | Semiconductor integrated circuit | |
| KR900019198A (en) | Semiconductor integrated circuit device | |
| JP3070542B2 (en) | Semiconductor device | |
| KR0144243B1 (en) | I / O cell layout method of gate array | |
| JP2981326B2 (en) | Power cell layout method in semiconductor device | |
| JPS62186549A (en) | Field effect semiconductor device | |
| KR100228373B1 (en) | Mos transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20060928 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |