JPH0669649A - Manufacture of printed wiring board - Google Patents

Manufacture of printed wiring board

Info

Publication number
JPH0669649A
JPH0669649A JP4222744A JP22274492A JPH0669649A JP H0669649 A JPH0669649 A JP H0669649A JP 4222744 A JP4222744 A JP 4222744A JP 22274492 A JP22274492 A JP 22274492A JP H0669649 A JPH0669649 A JP H0669649A
Authority
JP
Japan
Prior art keywords
solder
resist
wiring board
layer
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4222744A
Other languages
Japanese (ja)
Inventor
Hironobu Suda
廣伸 須田
Mitsuaki Kamata
光昭 鎌田
Yasuhiro Ikemura
康弘 池村
Yoshihiro Momota
吉宏 百田
Hiroshi Shibato
弘史 柴戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Printing Co Ltd filed Critical Toppan Printing Co Ltd
Priority to JP4222744A priority Critical patent/JPH0669649A/en
Publication of JPH0669649A publication Critical patent/JPH0669649A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks
    • H05K3/062Etching masks consisting of metals or alloys or metallic inorganic compounds
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/425Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To make the thickness of solder uniform so as to prevent the occurrence of tilting or insufficient continuity of surface-mounted parts by selectively removing the solder so that the solder can be left at necessary parts only. CONSTITUTION:A photoresist 3 is formed on the upper surface of a plated layer except pads 1 for mounting electronic parts, parts of the surrounding areas of through holes 5, and wiring layer forming areas 2 and, at the same time, a thick copper layer is stuck to the part of the plated layer exposed through the resist layer 3. Then, after forming a solder layer on the surface of the copper, the resist 3 is removed and the plated layer is etched off except the pads 1, the internal surfaces and parts of the surrounding areas of the holes 5, and the parts 2 and an outer wiring layer is formed. Then a dry film is vacuum-laminated on the wiring board and a resist 6 is formed on the pads 1 and in the surrounding areas of the holes 5. When the resist 6 is removed thereafter, the solder remains on the pads 1 and internal surfaces and surrounding areas of the holes 5 and a printed wiring board on which the copper of wiring pattern is exposed is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、最終仕上げのプリント
配線板に電子実装部品が実装され易いようにパッド及び
部品ランドに半田が施されている多層プリント配線板の
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer printed wiring board in which pads and component lands are soldered so that electronically mounted components can be easily mounted on a final printed wiring board.

【0002】[0002]

【従来の技術】従来、最終仕上げにソルダーレジストを
形成したプリント配線板は、パッド及び部品ランドに部
品を実装する際のはんだぬれ性をよくするために、プリ
ント配線板に半田を塗布してくこと(以下、ソルダーコ
ート処理と呼ぶ)が、通常であり、ソルダーコート処理
を施すプリント配線板の製造方法として、以下の2通り
の方法がある。以下その説明を多層プリント配線板を例
にとって概略を説明すると、銅箔により形成された電気
配線層を有する複数枚の内層回路板を、外層用銅箔と共
に絶縁性の接着剤であるプリプレグ(ガラス不織布にエ
ポキシ樹脂を含浸させ、半硬化させたもの)を介して積
層し、内層回路板と外層回路板の電気配線層を導通させ
る為にスルーホールを穿設し、このスルーホールの内壁
面を銅にて覆い導通させる為に無電解銅めっき及び電解
銅めっきを施しめっき層を積層体表面とスルーホール内
壁面にそれぞれ形成する。
2. Description of the Related Art Conventionally, a printed wiring board having a solder resist formed on its final finish must be coated with solder in order to improve solder wettability when components are mounted on pads and component lands. (Hereinafter, referred to as solder coat treatment) is usual, and there are the following two methods as a method of manufacturing a printed wiring board to which the solder coat treatment is applied. The following is a brief description of the description using a multilayer printed wiring board as an example. A plurality of inner layer circuit boards each having an electric wiring layer formed of a copper foil, together with an outer layer copper foil, are prepregs (glass Non-woven fabric is impregnated with epoxy resin and is semi-cured) and laminated, and a through hole is drilled to connect the electrical wiring layers of the inner circuit board and the outer circuit board, and the inner wall surface of this through hole is Electroless copper plating and electrolytic copper plating are applied to cover with copper for electrical conduction, and plated layers are formed on the surface of the laminate and the inner wall surface of the through hole, respectively.

【0003】次いで、上記めっき層の面上にスルーホー
ル周辺の一部やパッド及び配線層形成部位を除きフォト
レジストをパターン状に形成し、このフォトレジスト層
から露出する部位即ち外層配線パターンとなるところに
硫酸銅めっきにより外層配線層の配線パターンとなると
ころに銅を厚付けし、銅表面に半田を電解めっきで形成
する。(この半田は、次にエッチングを行う時のエッチ
ングレジストとなる。)そして、上記のめっきレジスト
を剥離し、スルーホールの内壁面及び周辺の一部と配線
層形成部位以外をエッチングにより除去し、外層配線層
を形成する。
Next, a photoresist is formed in a pattern on the surface of the plating layer except for a part around the through hole, a pad and a wiring layer forming portion, which is a portion exposed from the photoresist layer, that is, an outer layer wiring pattern. Copper sulfate is plated on the outer wiring layer to form a wiring pattern, and copper is electrolytically plated on the surface of the copper. (This solder becomes an etching resist for the next etching.) Then, the plating resist is peeled off, and the inner wall surface of the through hole and a part of the periphery and a portion other than the wiring layer forming portion are removed by etching. An outer wiring layer is formed.

【0004】次いで、エッチングレジストとして使用し
た、半田を溶解除去し、銅が露出した外層板の配線層が
出来上がり、カーテンコート法により熱硬化性のソルダ
ーレジストを基板に塗布し、部品ランド等をマスクする
露光用フィルムを載せ、露光、現像し、ソルダーレジス
トを形成する。ソルダーレジストを形成した配線板は、
部品ランドに部品を実装する際のはんだぬれ性をよくす
るために、予め配線板に半田を塗布してソルダーコート
処理が必要であり、そのソルダーコート処理とは、23
0〜240℃の溶融半田槽に配線板を3〜5秒浸漬さ
せ、配線板を鉛直方向に引き上げたあと余分なソルダー
を熱風エアーで吹き飛ばし部品ランドとスルーホールに
のみに半田を付加させ、半田処理を施した多層プリント
配線板を得る方法である。
Next, the solder used as the etching resist is dissolved and removed, and the wiring layer of the outer layer plate with the exposed copper is completed. The thermosetting solder resist is applied to the substrate by the curtain coating method, and the component land and the like are masked. The exposure film is placed, exposed and developed to form a solder resist. The wiring board with the solder resist is
In order to improve the solder wettability when mounting a component on a component land, it is necessary to apply solder to the wiring board in advance and perform a solder coat treatment. The solder coat treatment is 23
Dip the wiring board in a molten solder bath at 0 to 240 ° C for 3 to 5 seconds, pull up the wiring board in the vertical direction, blow off excess solder with hot air, and add solder only to the component land and through hole. It is a method for obtaining a treated multilayer printed wiring board.

【0005】ソルダーコート処理については、上記方法
の他に以下の方法がある。以下その説明を多層プリント
配線板を例にとって概略を説明すると、エッチングを行
うまでの工程は上記の従来の工程と同一工程で行い、エ
ッチングを終了した配線板は、次に、パッドやランドの
半田を残す部分にピールーコートインキで印刷し、パッ
ドやランド以外の例えば配線パターンの半田は溶解除去
し、前記のピールコートインキを剥離し、露出した半田
を加熱処理して一旦溶融し均質合金化する。所謂フュー
ジングを行うということである。配線パターンの部分に
は、フュージングの際、配線パターンと配線パターンの
間が狭いと、溶けた半田により間隙不良となることがあ
り、また部品が実装されることはないので、不要なとこ
ろの半田は除去しておく必要があるのである。ところ
で、半田めっきは、正しくはすず・鉛合金めっきであ
り、一旦溶融することによって共晶はんだ組織が完成さ
れ、はんだぬれ性が向上する。そして、フュージングを
かけたあとの配線板にソルダーレジスト印刷してプリン
ト配線板を製造する。
As for the solder coat treatment, there are the following methods in addition to the above method. In the following, the explanation will be given by taking a multilayer printed wiring board as an example.The steps up to etching are performed in the same steps as the conventional steps described above. Print on the part that leaves the area with Peeloo coat ink, dissolve and remove the solder of the wiring pattern, for example, except for the pads and lands, peel off the peel coat ink, heat the exposed solder and once melt it to form a homogeneous alloy. To do. This is what is called fusing. In the wiring pattern, if there is a narrow space between the wiring patterns during the fusing, the melted solder may cause a gap defect, and the parts will not be mounted. Need to be removed. By the way, the solder plating is properly tin-lead alloy plating, and once melted, the eutectic solder structure is completed and the solder wettability is improved. Then, the printed wiring board is manufactured by performing solder resist printing on the wiring board after the fusing.

【0006】[0006]

【発明が解決しようとする課題】上記の溶融半田槽に配
線板を浸漬する方法の場合を更に詳しく述べると、23
0〜240℃の溶融半田槽に配線板を3〜5秒浸漬さ
せ、配線板の半田塗布面を鉛直方向と平行にして配線板
を引き上げ、半田の液面から一定の高さにある熱風吹き
上げ手段から半田塗布面に熱風を吹き上げて半田層を均
一化させるのだが、常に一定の速さ(約230mm/S
ec)で引き上げられる配線板に常に一定の圧力(4.
8Kg/cm2 )の熱風を吹き付けて、余分に塗布され
た半田を除去するとともに半田層の均一化を行うように
している。近年、プリント配線板の半田塗布工程では、
ICチップのプリント基板に対する座りの安定化、接点
不良防止等の理由により、プリント配線板の所定部位の
表面に均一な厚さの半田層を形成することが要求されて
いる。
The method of immersing a wiring board in the molten solder bath will be described in more detail.
The wiring board is immersed in a molten solder bath at 0 to 240 ° C for 3 to 5 seconds, the solder application surface of the wiring board is parallel to the vertical direction and the wiring board is pulled up, and hot air is blown at a certain height from the liquid surface of the solder. Hot air is blown from the means to the solder application surface to make the solder layer uniform, but at a constant speed (about 230 mm / S).
constant pressure (4.
Hot air of 8 kg / cm 2 ) is blown to remove excess solder applied and to make the solder layer uniform. In recent years, in the solder coating process for printed wiring boards,
It is required to form a solder layer having a uniform thickness on the surface of a predetermined portion of the printed wiring board for reasons such as stabilization of sitting of the IC chip on the printed board and prevention of contact failure.

【0007】しかしながら、従来の半田塗布方法では、
プリント配線板を常に一定の速さで引き上げつつ、半田
塗布面の上部から下部にわたる全域に一定の圧力の熱風
を吹き付けているが、半田槽から引き上げられたプリン
ト配線板の半田塗布面では、塗布された半田がその自重
により常に半田塗布面の上部から下部へ流れて下部で溜
まり、また半田は経時的に固化してくる。この結果、半
田層の厚さは、上方が薄く、下方が厚くなり、全体とし
て半田層の厚さに許容し難い不均一が生じるという問題
がある。
However, in the conventional solder coating method,
While the printed wiring board is always pulled up at a constant speed, hot air with a constant pressure is blown over the entire area from the top to the bottom of the solder application surface. Due to its own weight, the deposited solder always flows from the upper part to the lower part of the solder application surface and accumulates in the lower part, and the solder solidifies with time. As a result, the thickness of the solder layer becomes thinner in the upper part and thicker in the lower part, and there is a problem in that the thickness of the solder layer as a whole becomes unacceptable and uneven.

【0008】また、半田を残す部分にピールコートイン
キ等でレジストを形成し、部分的に残した半田にフュー
ジングをかける方法では、フュージングをかける前にピ
ールコートインキ等のレジストを剥離する際に、部品を
実装するための部品孔やスルーホールにインキがつま
り、手作業で詰まったインキを除かなければならない。
といいう不都合があり、作業性が極めて低いという問題
がある。また、半田を剥離する為のレジストとして、ド
ライフィルムをラミネートする方法もあるが、ラミネー
ト時に皺がよりやすく、レジスト不良となって、半田剥
離の際に残すべき半田を剥離してしまう。という問題が
あった。
Further, in a method of forming a resist with a peel coat ink or the like on a portion where the solder is left and fusing the partially left solder, when peeling the resist such as the peel coat ink before the fusing, Ink gets stuck in component holes and through holes for mounting components, and it is necessary to remove ink that has been manually clogged.
However, there is a problem that workability is extremely low. There is also a method of laminating a dry film as a resist for peeling the solder, but wrinkles are more likely to occur during lamination, resulting in resist failure, and the solder that should be left when peeling the solder is peeled off. There was a problem.

【0009】[0009]

【課題を解決するための手段】すなわち、本発明は、銅
張積層板に、半田をエッチングレジストとしてエッチン
グを行い外層の配線層を形成し、レジストとして使用し
た半田を剥離して配線パターンを得る多層プリント配線
板の製造方法に於いて、前記エッチング工程を終了した
配線層形成後の配線板に真空ラミネート機によりドライ
フィルムを真空ラミネートし、該ドライフィルムが所望
の部分に残るようにパターン状にレジストを形成し、次
に半田を剥離する際に前記ドライフィルムをレジストと
して部分的に半田を残すことを特徴とするプリント配線
板の製造方法。
That is, according to the present invention, a copper clad laminate is etched by using solder as an etching resist to form an outer wiring layer, and the solder used as the resist is peeled off to obtain a wiring pattern. In the method for producing a multilayer printed wiring board, a dry film is vacuum laminated on a wiring board after the formation of the wiring layer after the etching step by a vacuum laminating machine, and the dry film is formed into a pattern so that the dry film remains at a desired portion. A method for manufacturing a printed wiring board, which comprises forming a resist and then partially leaving the solder by using the dry film as a resist when the solder is peeled off.

【0010】[0010]

【作用】このような製造方法によれば、電解めっきで半
田を形成し、その半田めっきをエッチングレジストとし
てエッチングを行い、外層配線層形成後、真空ラミネー
ター機により、ドライフィルムを真空ラミネートしてレ
ジストを形成するので、レジストを精度よく形成するこ
とが出来、よって半田を確実に残すことができる。そし
て、プリント配線板を加熱処理することにより半田を溶
融、均質合金化する処理を行うことにより、プリント配
線板の電気実装部品(例えばICパッケージ)を実装す
る為のパッド等の半田の厚みが均一となり、ICチップ
のプリント基板に対する座りの安定化が得られ、更に、
接点不良を防止することができるものである。
According to such a manufacturing method, solder is formed by electrolytic plating, etching is performed by using the solder plating as an etching resist, and after forming an outer wiring layer, a dry film is vacuum laminated by a vacuum laminator machine to form a resist. Since the resist is formed, the resist can be formed with high accuracy, and thus the solder can be surely left. Then, by heating the printed wiring board to melt the solder and homogenize the solder, the thickness of the solder such as pads for mounting the electrical mounting components (for example, IC package) of the printed wiring board is uniform. It is possible to stabilize the sitting of the IC chip on the printed circuit board.
The contact failure can be prevented.

【0011】[0011]

【実施例】図1から図3は本発明のプリント配線板の製
造工程図である。図1は本発明実施例においてドライフ
ィルムにより外層パターン形成時のプリント配線板の平
面図、図2はエッチング後のプリント配線版の平面図、
図3はドライフィムを真空ラミネートし、レジストを形
成したプリント配線版の平面図である。本発明は、銅箔
により形成された電気配線層を有する内層回路板を、外
層用銅箔と共にプリプレグを介して加熱加圧して積層し
終わった外層用銅箔に、内層回路板と外層回路板の導通
させる為にスルーホールを穿設し、このスルーホールの
内壁面を胴にて覆い導通させる為に無電解めっきおよび
電解胴めっきを施しめっき層を積層体表面とスルーホー
ル内壁面のそれぞれ形成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 3 are manufacturing process diagrams of a printed wiring board of the present invention. 1 is a plan view of a printed wiring board when an outer layer pattern is formed by a dry film in an embodiment of the present invention, and FIG. 2 is a plan view of a printed wiring board after etching,
FIG. 3 is a plan view of a printed wiring board in which a dry film is vacuum laminated to form a resist. The present invention relates to an inner layer circuit board having an electric wiring layer formed of a copper foil, an inner layer circuit board and an outer layer circuit board, which have been laminated by heating and pressurizing the inner layer circuit board with an outer layer copper foil through a prepreg. To form a plated layer on the surface of the laminated body and on the inner wall surface of the through hole by performing electroless plating and electrolytic cylinder plating to cover the inner wall surface of this through hole To do.

【0012】次いで、上記めっきの上面に電子部品実装
用のパッド(1)とスルーホール周辺の一部と配線層形
成部位(2)を除き図1のようにフォトレジスト(3)
をパターン状に形成すると共に、このフォトレジスト層
から露出する部位に硫酸銅めっきにより外層回路の配線
パターンとなるところに銅を厚付けする。そして、銅表
面に半田を1A/dm2 で25分の電解めっきで形成
し、20μの半田層を形成し、前記のフォトレジスト
(3)を剥離し電子部品実装用のパッドとスルーホール
の内壁面及び周辺の一部と配線層形成部位以外を図2の
ようにエッチングにより除去し、外層配線層を形成す
る。この時、厚さ20μmの前記半田は、後にフュージ
ングを行うときに、有効な半田厚膜を得るために必要な
半田厚膜である。更に、電子実装部品を表面に実装する
場合通常クリームはんだをパッドの上にのせ、ICパッ
ケージ等のリードをその上に設置し、加熱してクリーム
はんだを一旦溶融させはんだ付けする方法がとられてい
るが、この実施例の場合は半田の厚さが厚く均一である
為、クリームはんだは用いず予めプリント配線板に厚く
コーティングした半田を一旦溶融させ実装することがで
きる。
Next, as shown in FIG. 1, a photoresist (3) is formed on the upper surface of the plating except for the electronic component mounting pad (1), a part around the through hole, and a wiring layer forming portion (2).
Is formed in a pattern, and copper is thickly applied to a portion exposed from the photoresist layer by copper sulfate plating in a portion to be a wiring pattern of an outer layer circuit. Then, solder is formed on the copper surface by electrolytic plating at 1 A / dm 2 for 25 minutes to form a 20 μ solder layer, and the photoresist (3) is peeled off to remove the electronic component mounting pad and through hole. Except for the wall surface and a part of the periphery and the portion where the wiring layer is formed, the outer wiring layer is formed by etching as shown in FIG. At this time, the solder having a thickness of 20 μm is a solder thick film necessary for obtaining an effective solder thick film when the fusing is performed later. Further, when mounting an electronic mounting component on the surface, a method is usually used in which cream solder is placed on a pad, leads of an IC package or the like are placed on the pad, and the cream solder is once melted to be soldered. However, in the case of this embodiment, since the thickness of the solder is thick and uniform, cream solder is not used, and the solder previously thickly coated on the printed wiring board can be once melted and mounted.

【0013】エッチングを終えたプリント配線板(4)
に、ドライフィルムを重ね、残したい半田の部分をぬい
たネガフィルムを重ね合わせ、そして、真空ラミネータ
ー機を使用して2mbの真空状態でプリント配線板とド
ライフィルムを密着させ、それを85℃のプラテン(シ
リコンレバー)で60秒はさみこんでラミネートする。
次に、60mJの光量で露光し、現像し、図3のように
電子実装部品を表面実装するためのパッド(1)及びス
ルーホール(5)の周辺にレジスト(6)を形成する。
この時、ドライフィルムを密着させないとレジストの精
度が悪くなり、パッド上にレジストが確実に残らないた
め、半田剥離の際に必要な半田が除去されてしまった
り、パッド付近の導体にレジストが残ることにより、半
田が残ってしまい、フュージングの際にショートしたり
する。以上のことからもレジストの精度は重要であるの
で、ドライフィルムを真空状態で密着させることにより
パッドとレジストの設定を確実に行うことができ、レジ
ストの精度をあげることができる。また、ラミネート時
の皺の問題も、真空ラミネーター機を使用することによ
り、解決できる。
Printed wiring board (4) after etching
Overlaid with a dry film, a negative film from which the portion of the solder to be left is removed is overlaid, and a vacuum laminator machine is used to bring the printed wiring board and dry film into close contact with each other at a temperature of 85 ° C. Laminate with a platen (silicone lever) for 60 seconds.
Next, it is exposed with a light amount of 60 mJ and developed to form a resist (6) around the pad (1) and the through hole (5) for surface-mounting the electronic component as shown in FIG.
At this time, if the dry film is not adhered, the accuracy of the resist will deteriorate and the resist will not remain on the pad reliably, so that the solder necessary for solder peeling will be removed or the resist will remain on the conductor near the pad. As a result, the solder remains, which may cause a short circuit during fusing. Since the accuracy of the resist is also important from the above, it is possible to reliably set the pad and the resist by adhering the dry film in a vacuum state, and it is possible to improve the accuracy of the resist. Also, the problem of wrinkles during lamination can be solved by using a vacuum laminator machine.

【0014】以上のように、ドライフィルムを真空ラミ
ネーター機を使用してプリント配線板に重ね合わせるの
で、プリント電子実装部品を表面実装するためのパッド
の幅が狭い場合でも、精度善くレジストを形成すること
ができるので、半田を確実に残すことができる。
As described above, since the dry film is superposed on the printed wiring board by using the vacuum laminator machine, the resist can be accurately formed even if the width of the pad for surface mounting the printed electronic mounting component is narrow. Therefore, the solder can be surely left.

【0015】レジストを形成したプリント配線板は、配
線層形成部位(2)を含むその他の部分の半田は溶解除
去する。そして、前記レジスト(6)を水酸化ナトリウ
ム溶液や水酸化カリウム溶液により、通常のパターニン
グに使用するドライフィルムの剥膜のようにして、剥膜
すると、電子実装部品を表面実装するためのパッド及び
スルーホール(5)の内壁面とその周辺には半田が残
り、配線パターンには銅が露出したプリント配線板が得
られる。上記のような方法によりレジストを剥離する
と、スルーホール(5)の穴内にレジストが残ることは
ない。
In the printed wiring board on which the resist is formed, the solder in other portions including the wiring layer forming portion (2) is dissolved and removed. Then, when the resist (6) is peeled off with a sodium hydroxide solution or a potassium hydroxide solution like peeling of a dry film used for normal patterning, a pad for surface-mounting electronic mounting components and Solder remains on the inner wall surface of the through hole (5) and its periphery, and a printed wiring board in which copper is exposed in the wiring pattern is obtained. When the resist is peeled off by the above method, the resist does not remain in the through hole (5).

【0016】しかし、上記のままの半田は、そまままで
は外層配線パターン形成途中で、エッチングのレジスト
として使用したのでエッチングの際にその表面が荒れい
るので、一旦溶融することにより表面をフラットにする
とともに、半田を溶融することにより、オーバーハング
になったソルダーフィレットによるパッド同士の短絡を
防止し、パッド側壁の錆を防止し、また、錫と鉛の共晶
はんだ組織にすることによりはんだぬれ性を向上させ
る。
However, the above-mentioned solder is used as a resist for etching during the formation of the outer layer wiring pattern, and the surface is roughened during etching. Therefore, the solder is once melted to flatten the surface. In addition, by melting the solder, short circuit between pads due to overfilled solder fillet is prevented, rust on the side wall of the pad is prevented, and a eutectic solder structure of tin and lead is used for solder wetting. Improve sex.

【0017】上記の理由により、プリント配線板は、2
40℃の温度で5秒加熱し半田を一旦溶解し、フュージ
ングを行う。そして、電子実装部品を表面実装するため
のパッド(1)及びスルホール(5)の周辺を除いた外
層表面にソルダーレジストを塗布する。
For the above reasons, the printed wiring board has two
The solder is once melted by heating for 5 seconds at a temperature of 40 ° C., and fusing is performed. Then, a solder resist is applied to the outer layer surface excluding the periphery of the pad (1) and the through hole (5) for surface mounting the electronic mounting component.

【0018】[0018]

【発明の効果】以上のように、本発明によれば、従来の
ように、一度半田を剥離して再度溶融した半田槽にプリ
ント配線板を浸漬して鉛直方向に引き上げるような行法
をとらず、電解めっきにより形成した半田を選択的に剥
離し必要な部分だけ残し、その半田をフュージングする
ことにより、半田の厚さが均一となり、ICパッケージ
等の表面実装部品を実装した際に、部品がかしぐことが
なく、また、導通不良をおこすこともない。更に、半田
を必要な部分だけ残す為に、真空ラミネーター機によ
り、ドライフィルムをラミネートし、レジストを形成す
るので、半田を精度よく残すことが出来き、又、レジス
トを剥離する際にも、通常のドライフィルムの剥離のよ
うにしてレジストを剥離するので、スルーホールにレジ
ストが残ることがないので、従来のように手作業でレジ
ストを除去する必要がなくなり、作業性が向上する。
As described above, according to the present invention, the conventional method of dipping the printed wiring board in the solder bath in which the solder is once peeled and then melted again and pulled up in the vertical direction is adopted. Instead, the solder formed by electrolytic plating is selectively peeled off to leave only the necessary portion, and the solder is fused so that the thickness of the solder becomes uniform, and when the surface mount component such as an IC package is mounted, It does not cause scratches and does not cause poor continuity. Furthermore, in order to leave only the necessary part of the solder, the dry film is laminated by the vacuum laminator machine to form the resist, so the solder can be left with good accuracy, and when the resist is peeled off, Since the resist is peeled off in the same manner as the dry film peeling, the resist does not remain in the through holes, so that it is not necessary to manually remove the resist as in the conventional case, and the workability is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の製造過程のプリント配線板の平面図で
ある。
FIG. 1 is a plan view of a printed wiring board in the manufacturing process of the present invention.

【図2】本発明の製造過程のプリント配線板の平面図で
ある。
FIG. 2 is a plan view of the printed wiring board in the manufacturing process of the present invention.

【図3】本発明の製造過程のプリント配線板の平面図で
ある。
FIG. 3 is a plan view of the printed wiring board in the manufacturing process of the present invention.

【符号の説明】[Explanation of symbols]

1…パッド 2…配線層形成部位 3…フォトレジスト 4…エッチング後のプリント配線板 5…スルーホール 6…レジスト DESCRIPTION OF SYMBOLS 1 ... Pad 2 ... Wiring layer formation site 3 ... Photoresist 4 ... Printed wiring board after etching 5 ... Through hole 6 ... Resist

───────────────────────────────────────────────────── フロントページの続き (72)発明者 百田 吉宏 東京都台東区台東一丁目5番1号 凸版印 刷株式会社内 (72)発明者 柴戸 弘史 東京都台東区台東一丁目5番1号 凸版印 刷株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshihiro Momota 1-5-1, Taito, Taito-ku, Tokyo Toppan Printing Co., Ltd. (72) Hiroshi Shibato 1-5-1, Taito, Taito-ku, Tokyo Toppan Imprint Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】銅張積層板に半田をエッチングレジストと
してエッチングを行い外層の配線層を形成し、レジスト
として使用した半田を剥離して配線パターンを得る多層
プリント配線板の製造方法に於いて、 前記エッチング工程を終了した配線層形成後の配線板に
真空ラミネート機によりドライフィルムを真空ラミネー
トし、該ドライフィルムが所望の部分に残るようにパタ
ーン状にレジストを形成し、次に半田を剥離する際に前
記ドライフィルムをレジストとして部分的に半田を残す
ことを特徴とするプリント配線板の製造方法。
1. A method for producing a multilayer printed wiring board, wherein a copper clad laminate is etched with solder as an etching resist to form an outer wiring layer, and the solder used as the resist is peeled off to obtain a wiring pattern. A dry film is vacuum-laminated on the wiring board after the formation of the wiring layer after the etching step by a vacuum laminating machine, a resist is formed in a pattern so that the dry film remains at a desired portion, and then the solder is peeled off. A method for manufacturing a printed wiring board, characterized in that the dry film is used as a resist to partially leave solder.
JP4222744A 1992-08-21 1992-08-21 Manufacture of printed wiring board Pending JPH0669649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4222744A JPH0669649A (en) 1992-08-21 1992-08-21 Manufacture of printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4222744A JPH0669649A (en) 1992-08-21 1992-08-21 Manufacture of printed wiring board

Publications (1)

Publication Number Publication Date
JPH0669649A true JPH0669649A (en) 1994-03-11

Family

ID=16787229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4222744A Pending JPH0669649A (en) 1992-08-21 1992-08-21 Manufacture of printed wiring board

Country Status (1)

Country Link
JP (1) JPH0669649A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2427092A (en) * 2005-06-10 2006-12-13 Avago Technologies Wireless Ip Bandpass filter resonator network improves insertion loss with isolating/buffer amplifiers
JP2008047786A (en) * 2006-08-21 2008-02-28 Fuji Electric Device Technology Co Ltd Insulating film forming method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02226152A (en) * 1988-12-23 1990-09-07 E I Du Pont De Nemours & Co Improved construction of vacuum laminate solder mask covered printed circuit board by fluid pressurization

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02226152A (en) * 1988-12-23 1990-09-07 E I Du Pont De Nemours & Co Improved construction of vacuum laminate solder mask covered printed circuit board by fluid pressurization

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2427092A (en) * 2005-06-10 2006-12-13 Avago Technologies Wireless Ip Bandpass filter resonator network improves insertion loss with isolating/buffer amplifiers
GB2427092B (en) * 2005-06-10 2009-08-19 Avago Technologies Wireless Ip Bandpass filter network and method for bandpass filtering signals
JP2008047786A (en) * 2006-08-21 2008-02-28 Fuji Electric Device Technology Co Ltd Insulating film forming method

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