JPH0666352B2 - High frequency semiconductor device - Google Patents

High frequency semiconductor device

Info

Publication number
JPH0666352B2
JPH0666352B2 JP1036557A JP3655789A JPH0666352B2 JP H0666352 B2 JPH0666352 B2 JP H0666352B2 JP 1036557 A JP1036557 A JP 1036557A JP 3655789 A JP3655789 A JP 3655789A JP H0666352 B2 JPH0666352 B2 JP H0666352B2
Authority
JP
Japan
Prior art keywords
wires
wire
electrode
external connection
wire loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1036557A
Other languages
Japanese (ja)
Other versions
JPH02215137A (en
Inventor
守 安藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1036557A priority Critical patent/JPH0666352B2/en
Publication of JPH02215137A publication Critical patent/JPH02215137A/en
Publication of JPH0666352B2 publication Critical patent/JPH0666352B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To make possible the compatibility of a reduction in a parasitic capacity between wires and the parasitic inductances of the wires and a reduction in the size of the constitution of the title device by a method wherein external connecting electrodes on a ceramic substrate and the electrode pads of a high-frequency semiconductor device are folded back and are bonded together by first and second wire loops formed by being subjected to step bonding on the wires which respectively draw a different locus. CONSTITUTION:External connecting electrodes 12 on a ceramic substrate 11 end electrode pads 14 of a high-frequency semiconductor device 13 are folded back in parallel and are bonded together by first and second wire loops 16 and 19 formed by being subjected to step bonding on wires 15. Moreover, the two wires 15 respectively draw a different locus, the amount of a current per one of the wires, which are separated from each other so as to cross in their height direction, is reduced, s skin effect is reduced end with e parasitic capacity between the wires 15 and the parasitic inductances of the wires 15 reduced, an increase in the areas of the electrodes 12 is prevented by the separation of the wires in their height direction and a reduction in the size of the constitution of a device is contrived.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は、GaAsＦＥＴ等の高周波型の半導体装置に関す
るもので、特に接続ワイヤのインダクタンスを低減した
半導体装置に関する。The present invention relates to a high-frequency type semiconductor device such as GaAs FET, and more particularly to a semiconductor device in which the inductance of a connecting wire is reduced.

(ロ)従来の技術 一般にトランジスタの電極引き出し線（前記金属細線と
リードとを含む）は、微弱ではあるがそれ自体インダク
タンスを有し、又引き出し線相互の間には寄生容量があ
る。周波数の増加につれてこれらのリアクタンスを無視
することができなくなる。従って衛星放送やＣＡＴＶ受
像機のチューナ回路等の様に高周波（例えば１GHz以
上）で使用するトランジスタでは、引き出し線の直列イ
ンダクタンスが小さく、且つ線相互の間に容量が小さい
ことが要求される。このため前記高周波トランジスタに
おいては、モールド型、セラミック型共に素子の大きさ
を小さくして、内部の結線による直列インダクタンスを
減少させている（特開昭６２−２８１４５８）。(B) Conventional Technology In general, the electrode lead-out line (including the thin metal wire and the lead) of the transistor has a weak inductance but a parasitic capacitance between the lead-out lines. As the frequency increases, these reactances cannot be ignored. Therefore, a transistor used at a high frequency (for example, 1 GHz or more) such as a satellite broadcast or a tuner circuit of a CATV receiver is required to have a small series inductance of lead lines and a small capacitance between the lines. For this reason, in the high-frequency transistor, both the mold type and the ceramic type are made smaller in size to reduce the series inductance due to internal wiring (Japanese Patent Laid-Open No. 62-281458).

また、接続ワイヤのインダクタンスを低減する手法とし
て第７図に示す如く、チップ(1)上の電極パッド(2)と外
部接続電極(3)との間を、複数のリードワイヤ(4)で並列
にボンディングを行うことにより、ワイヤ(4)１本当り
の電流値を減らして表皮効果を緩和させ、等価インダク
タンス及び等価インピーダンスを低下することが本願発
明者により提案された。Further, as a method of reducing the inductance of the connecting wire, as shown in FIG. 7, a plurality of lead wires (4) are arranged in parallel between the electrode pad (2) on the chip (1) and the external connecting electrode (3). It has been proposed by the inventor of the present application to reduce the current value per wire (4) to alleviate the skin effect and lower the equivalent inductance and the equivalent impedance by performing the bonding.

(ハ)発明が解決しようとする課題 しかしながら、チップ(1)上の電極パッド(2)にワイヤ
(4)２本分のボンディングエリアを確保することは、電
極パッド(2)の面積を縮小できないので電極パッド(2)の
持つ寄生容量を低減できないという欠点があった。(C) Problems to be Solved by the Invention However, wire is provided on the electrode pad (2) on the chip (1).
(4) Securing two bonding areas has a drawback that the area of the electrode pad (2) cannot be reduced and thus the parasitic capacitance of the electrode pad (2) cannot be reduced.

また、２本のワイヤ(4)を平行にボンディングすると相
互インダクタンスを持つので夫々は互いにある程度の距
離を保つ必要があり、すると外部接続用電極(3)の面積
も必然的に大きくなる欠点があった。Also, if two wires (4) are bonded in parallel, they have mutual inductance, so it is necessary to keep a certain distance between them, which inevitably increases the area of the external connection electrode (3). It was

(ニ)課題を解決するための手段 本発明は上記従来の課題に鑑み成されたもので、ワイヤ
(15)をステッチボンドすることにより折り返しボンディ
ングとし、且つ２本のワイヤ(15)が高さ方向でクロスす
るように離間させることにより、寄生容量、寄生インダ
クタンスの減少と装置の小形化を両立させた高周波型半
導体装置を提供するものである。(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned conventional problems.
The (15) is stitch-bonded to form a folded bond, and the two wires (15) are separated so as to cross each other in the height direction, so that both parasitic capacitance and parasitic inductance are reduced and the device is downsized. And a high frequency type semiconductor device.

(ホ)作用 本発明によれば、ステッチボンドにより２本のループ(1
6)(19)を並列にホンディングするので、ワイヤ(15)１本
当りの電流値を減らして表皮効果を緩和させ、ワイヤ(1
5)相互の寄生容量と寄生インダクタンスを低下できる。
また、２本のワイヤ(15)が高さ方向で互いに離間するよ
うに第１と第２のループ(16)(19)を作るので、実質的に
ワイヤ(15)相互間のインダクタンスの増大を防げる。さ
らに、ステッチボンドにより電極パッド(14)面積の縮小
による寄生容量の低減が可能になる他、２本のワイヤ(1
5)が高さ方向で離間するような形状とすることにより、
外部接続電極(12)の面積増大をも防ぐことができる。(E) Action According to the present invention, two loops (1
6) Since (19) is honed in parallel, the current value per wire (15) is reduced to alleviate the skin effect and
5) Mutual parasitic capacitance and parasitic inductance can be reduced.
Moreover, since the first and second loops (16) and (19) are formed so that the two wires (15) are separated from each other in the height direction, the inductance between the wires (15) is substantially increased. Can be prevented. Furthermore, the stitch bond can reduce the parasitic capacitance by reducing the area of the electrode pad (14), and the two wires (1
By making the shape so that 5) is separated in the height direction,
It is possible to prevent an increase in the area of the external connection electrode (12).

(ヘ)実施例 以下に本発明の一実施例を図面を参照しながら詳細に説
明する。第１図は本発明のワイヤホンドを処して半導体
装置の側面を示す。同図において、(11)はセラミック基
体、(12)は基体(11)表面にマイクロストリップラインを
構成する外部接続用の電極、(13)は表面にＭＥＳ−ＦＥ
Ｔ、ショットキーダイオード等のマイクロ波用素子が形
成されたGaAsチップ、(14)はチップ(13)表面に形成され
たアルミニウム材料から成る電極パッド、(15)は直径２
５μ程の金ワイヤである。(F) Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a side view of a semiconductor device by treating a wire bond according to the present invention. In the figure, (11) is a ceramic substrate, (12) is an electrode for external connection constituting a microstrip line on the surface of the substrate (11), and (13) is MES-FE on the surface.
T, a GaAs chip on which a microwave element such as a Schottky diode is formed, (14) is an electrode pad made of an aluminum material formed on the surface of the chip (13), and (15) is a diameter 2
It is a gold wire of about 5μ.

ワイヤ(15)は先ず基体(11)側の外部接続用の電極(12)に
ボールボンドされ、続いてチップ(13)表面より高い位置
まで垂直に、又はチップ(13)から遠ざかるようにシフト
して上昇し、前記高い位置から弧を描いて斜めに下降し
始める。下降し始めたワイヤ(15)は、チップ(13)上の対
応する電極パッド(14)に向って略直線状に下降し、電極
パッド(14)上でセカンドボンドされる。ここまでのルー
プが第１のワイヤループ(16)を描く。The wire (15) is first ball-bonded to the electrode (12) for external connection on the substrate (11) side, and then vertically shifted to a position higher than the surface of the chip (13) or away from the chip (13). And rises, and begins to descend diagonally in an arc from the higher position. The wire (15) which has started to descend descends in a substantially straight line toward the corresponding electrode pad (14) on the chip (13) and is second-bonded on the electrode pad (14). The loop so far describes the first wire loop (16).

電極パッド(14)に接続されたワイヤ(15)は、そのまま連
続して折り返し、且つ電極パッド(14)上に弧を描く様に
上昇する。従って、折り返したワイヤ(15)は電極パッド
(14)上近傍において第１のワイヤループ(16)より高い位
置を通過する。上昇してある高さまで達したワイヤ(15)
は、外部接続用の電極(12)に向って略直線状に下降し始
める。下降し始めたワイヤ(15)は、第１のワイヤループ
(16)が前記高い位置から電極パッド(14)に向って直線状
に下降する部分の途中(17)で第１のワイヤループ(16)と
交差し、その先は外部接続用の電極(12)に向って直線状
に第１のワイヤループ(16)より低い位置を通過する。低
い位置を通過したワイヤ(15)は、今度は第１のワイヤル
ープ(16)が垂直に上昇する部分の途中(18)で再度交差
し、外部接続用の電極(12)に接続されて終端する。これ
が第２のワイヤループ(19)を描く。The wire (15) connected to the electrode pad (14) is continuously folded as it is, and rises in an arc on the electrode pad (14). Therefore, the folded wire (15) is
(14) Pass the position higher than the first wire loop (16) in the upper vicinity. Wires raised to a height (15)
Starts to descend in a substantially straight line toward the electrode (12) for external connection. The wire (15) that started to descend is the first wire loop
(16) intersects with the first wire loop (16) in the middle (17) of the portion where it linearly descends from the higher position toward the electrode pad (14), and beyond that the electrode (12) for external connection is connected. ) Straight below the first wire loop (16). The wire (15) passing through the lower position again crosses again in the middle (18) of the portion where the first wire loop (16) rises vertically, is connected to the electrode (12) for external connection, and terminates. To do. This describes the second wire loop (19).

上記第１と第２のワイヤループ(16)(19)は、上下方向
（高さ方向）で異る軌跡を描くことにより様々な形態を
とる。第２図右側の第１と第２のワイヤループ(16a)(19
a)は、第２のワイヤループ(19a)が常に第１のワイヤル
ープ(16a)より高い位置を通過する例、左側の第１と第
２のワイヤループ(16b)(19b)は第２のワイヤループ(19
b)が第１のワイヤループ(16b)と１点で交差し、外部接
続用の電極(12)への接続が第１のワイヤループ(16b)の
ものよりチップ(13)側へ近接した位置で行われた例であ
る。The first and second wire loops (16) and (19) take various forms by drawing different trajectories in the vertical direction (height direction). The first and second wire loops (16a) (19) on the right side of FIG.
a) is an example in which the second wire loop (19a) always passes higher than the first wire loop (16a), and the first and second wire loops (16b) (19b) on the left side are Wire loop (19
b) intersects the first wire loop (16b) at one point, and the connection to the electrode (12) for external connection is closer to the chip (13) side than that of the first wire loop (16b) It is an example performed in.

第３図はショットキーダイオード素子をセラミックパッ
ケージに固着した状態を示す平面図で、(11)はセラミッ
ク基体、(20)はセラミック基体(11)から導出された外部
接続リード、(12)は基体(11)の表面に形成され外部接続
リードと電気的に導通した外部接続用の電極、(13)は表
面に素子と電極パッド(14)が形成されたチップである。
チップ(13)はアノード側外部接続用の電極(12a)パター
ン上に半田等の材料でダイボンドされ、続いて夫々対応
する電極パッド(14)と外部接続用の電極(12)とを第１図
又は第２図に示した形状にワイヤ(15)でステッチボンド
する。その後、基体(11)の上に蓋体を固着することによ
り半導体チップ(13)を封止する。FIG. 3 is a plan view showing a state in which the Schottky diode element is fixed to the ceramic package. (11) is a ceramic base, (20) is an external connection lead derived from the ceramic base (11), and (12) is a base. An electrode for external connection formed on the surface of (11) and electrically connected to the external connection lead, and (13) is a chip having an element and an electrode pad (14) formed on the surface.
The chip (13) is die-bonded on the anode side external connection electrode (12a) pattern with a material such as solder, and then the corresponding electrode pad (14) and external connection electrode (12) are shown in FIG. Alternatively, a wire (15) is stitch-bonded to the shape shown in FIG. Then, the semiconductor chip (13) is sealed by fixing the lid on the base body (11).

第４図はGaAs・ＭＥＳＦＥＴ素子を同じくμ−Ｘ型と称
されるセラミックパッケージに固着した状態を示す平面
図で、ソース用外部接続電極(12S)パターン上にチップ
(13)が固着され、ゲート用の電極パッド(14G)とゲート
用外部接続電極(12G)を、ドレイン用の電極パッド(14D)
とドレイン用外部接続電極(12D)を夫々ワイヤ(15)で接
続すると共に、ソース用の電極パッド(14S)とソース用
外部接続電極(12S)とを第１図又は第２図に示した形状
にワイヤ(15)でステッチボンドしている。Fig. 4 is a plan view showing a state in which a GaAs MESFET device is fixed to a ceramic package also called the µ-X type, and a chip is formed on the source external connection electrode (12S) pattern.
(13) is fixed, the gate electrode pad (14G) and the gate external connection electrode (12G) are connected to the drain electrode pad (14D).
And the drain external connection electrode (12D) are connected by wires (15) respectively, and the source electrode pad (14S) and the source external connection electrode (12S) are shaped as shown in FIG. 1 or 2. Stitch bonded with wire (15).

ステッチボンドは、先ず第５図Ａに示すように、先端に
ボール部(21)を有するワイヤ(15)が挿通され、Ｘ方向及
びＹ方向に進退自在な取付部材に取付けられたボンディ
ングツール(22)を下降してボール部(21)を外部接続電極
(12)表面に圧接し、この状態でボンディングツール(22)
に超音波振動を与えることによりワイヤ(15)のボール部
(21)を外部接続電極(12)に超音波併用熱圧着する。In the stitch bond, as shown in FIG. 5A, first, a wire (15) having a ball portion (21) at its tip is inserted and attached to a bonding tool (22) attached to a mounting member that can move back and forth in the X and Y directions. ) To lower the ball (21) to the external connection electrode.
(12) Bonding tool (22) under pressure contact with the surface
By applying ultrasonic vibration to the ball part of the wire (15)
(21) is thermocompression bonded with ultrasonic waves to the external connection electrode (12).

次に第５図Ｂに示すように、ワイヤ(15)の固定を解除す
ると共にボンディングツール(22)を垂直方向に上昇さ
せ、チップ(13)より高いある高さまでワイヤ(15)を伸ば
す。Next, as shown in FIG. 5B, the wire (15) is unfixed and the bonding tool (22) is vertically raised to extend the wire (15) to a height higher than the chip (13).

次に第５図Ｃに示すように、ボンディングツール(22)を
チップ(13)側に移動させ、続いて下降することによりワ
イヤ(15)を電極パッド(14)表面に超音波併用熱圧着し、
これで第１のワイヤループ(16)を完成させる。Next, as shown in FIG. 5C, the bonding tool (22) is moved to the chip (13) side and then lowered to wire-bond the wire (15) to the surface of the electrode pad (14) by thermocompression bonding with ultrasonic wave. ,
This completes the first wire loop (16).

次に第５図Ｄに示すように、ワイヤ(15)を切断せずにそ
のままボンディングツール(22)を上昇させ、 第５図Ｅに示すように、電極パッド(14)上の折り返し点
からワイヤ(15)が弧を描くようにボンディングツール(2
2)を移動させ、 第５図Ｆに示すように、外部接続電極(12)上でボンディ
ングツール(22)を下降させることにより、ワイヤ(15)を
外部接続電極(12)表面に超音波併用熱圧着し、ボンディ
ングツール(22)を圧接させた状態でワイヤ(15)を図示せ
ぬクランパで固定し、引張ることによりワイヤ(15)を切
断する。これで第２のワイヤループ(19)が完成する。次
いでワイヤ(15)を固定したままボンディングツール(22)
を垂直に上昇させることにより、ボンディングツール(2
2)の先端にある程度の長さでワイヤ(15)を突出させる。Next, as shown in FIG. 5D, the bonding tool (22) is raised as it is without cutting the wire (15), and the wire is moved from the turning point on the electrode pad (14) as shown in FIG. 5E. Make sure that the bonding tool (2
2) is moved, and as shown in FIG. 5F, the bonding tool (22) is lowered on the external connection electrode (12), so that the wire (15) is ultrasonically used on the surface of the external connection electrode (12). The wire (15) is fixed by a clamper (not shown) in a state of being thermocompression bonded and the bonding tool (22) being in pressure contact with the wire, and then the wire (15) is cut. This completes the second wire loop (19). Next, with the wire (15) fixed, the bonding tool (22)
The bonding tool (2
The wire (15) is made to project to the tip of 2) with a certain length.

そして第５図Ｇに示すように、放電電極(23)とワイヤ(1
5)間の放電又はトーチ炎によるワイヤ(15)先端部への瞬
間的な熱処理により、ワイヤ(15)先端にボンディングツ
ール(22)のワイヤ(15)挿通孔の直径より大きいボール部
(21)を形成する。この時の瞬間的な熱処理により、ボン
ディングツール(22)から突出したワイヤ(15)の、特に放
電電極(23)に近接しチップ(13)とは反対側の表面が熱的
影響を受けて若干の焼入れ処理が不可避的に行われる。
焼入れが成されたワイヤ(15)は硬度が増して曲がりにく
くなるので、この部分が外部接続電極(12)上で第１のワ
イヤループ(16)が垂直に上昇する部分を形成し、第１の
ワイヤループ(16)の円弧を大きくできる要因となる。第
２のワイヤループ(19)は、前述した様な熱処理が無いの
で第１のワイヤループ(16)より小さな円弧を描き易い。Then, as shown in FIG. 5G, the discharge electrode (23) and the wire (1
5) A ball portion larger than the diameter of the wire (15) insertion hole of the bonding tool (22) is attached to the tip of the wire (15) by instantaneous heat treatment to the tip of the wire (15) due to discharge or torch flame between
Form (21). Due to the momentary heat treatment at this time, the surface of the wire (15) protruding from the bonding tool (22), particularly close to the discharge electrode (23) and on the side opposite to the chip (13), is thermally affected and may be slightly affected. Quenching treatment is unavoidably performed.
Since the hardened wire (15) increases in hardness and becomes hard to bend, this portion forms a portion where the first wire loop (16) rises vertically on the external connection electrode (12), and It becomes a factor that the arc of the wire loop (16) can be enlarged. Since the second wire loop (19) does not undergo the heat treatment as described above, it is easier to draw an arc smaller than that of the first wire loop (16).

ところで、２本のワイヤ(15)を近接させたことによる相
互インダクタンスの増加は両者間の距離と密接な関係が
ある。第６図はこの様な関係を示す特性図で、周波数ｆ
＝１２GHzの例を示す。同図から明らかな通り、相互イ
ンダクタンスはワイヤ(15)間の距離が０〜０．１mmの範
囲内で急速に減少し、それ以降はほぼ飽和状態となる。
従って、本願のワイヤ(15)構造は、電極パッド(14)上の
折り返し点を除いて、１点又は２点の交差する部分(17)
(18)を含み左右、上下及び斜め方向に少なくとも５０μ
ｍ以上の間隔をもって第１と第２のワイヤループ(16)(1
9)を形成すれば良いことが明らかである。By the way, the increase in mutual inductance due to the close proximity of the two wires (15) is closely related to the distance between them. FIG. 6 is a characteristic diagram showing such a relationship.
= 12 GHz is shown as an example. As is clear from the figure, the mutual inductance rapidly decreases within the range of the distance between the wires 15 of 0 to 0.1 mm, and thereafter becomes almost saturated.
Therefore, in the wire (15) structure of the present application, a portion (17) where one point or two points intersect except for a turning point on the electrode pad (14)
At least 50μ including left and right, up and down, and diagonally including (18)
First and second wire loops (16) (1
It is clear that 9) should be formed.

上記本願発明によれば、折り返しステッチボンディング
により複数本のワイヤループを形成するので、ワイヤ(1
5)１本当りの電流値を減らして表皮効果を緩和させ、半
導体装置が持つ等価インダクタンス及び等価インピーダ
ンスを低下させることができる。また、第１と第２のワ
イヤループ(16)(19)を第１図又は第２図に示す形状とす
ることにより、第１と第２のワイヤループ(16)(19)を上
下又は斜め方向に離間することができ、従って実質的に
２本のワイヤ(15)を離すことによりワイヤ(15)相互のイ
ンダクタンスをも低下させることができる。しかも、２
本のワイヤ(15)は立体的に離間しているので、電極パッ
ド(14)や外部接続電極(12)のパターンサイズを減少して
装置の小形化と等価インダクタンス及び寄生容量の更な
る低下をも可能にできる。According to the above invention of the present application, since a plurality of wire loops are formed by folding stitch bonding, the wire (1
5) The current value per wire can be reduced to alleviate the skin effect and the equivalent inductance and impedance of the semiconductor device can be reduced. In addition, by forming the first and second wire loops (16) and (19) into the shape shown in FIG. 1 or 2, the first and second wire loops (16) and (19) can be moved vertically or diagonally. The wires can be spaced apart in a direction, and thus substantially separating the two wires can reduce the mutual inductance of the wires. Moreover, 2
Since the wires (15) of the book are three-dimensionally separated, the pattern size of the electrode pad (14) and the external connection electrode (12) is reduced to reduce the device size and further reduce the equivalent inductance and parasitic capacitance. Can also be possible.

尚、本実施例はセラミックタイプのパッケージについて
詳述したが、エポキシ樹脂等によるモールドタイプのパ
ッケージについても同様である。また、２回，３回と折
り返して３本，４本のループを形成する際も同様であ
る。Although the present embodiment has described the ceramic type package in detail, the same applies to a mold type package made of epoxy resin or the like. The same applies when the loop is folded twice and three times to form three and four loops.

(ト)発明の効果 以上に説明した通り、本発明はワイヤ(15)を複数本化し
たので、ワイヤ(15)の持つインダクタンスを低減できる
利点を有する。また、第１と第２のワイヤループ(16)(1
9)が高さ方向で立体的に離間する形状としたので、ワイ
ヤ(15)相互のインダクタンスをも低減できる利点を有す
る。しかも、折り返しステッチボンドなので、電極パッ
ド(14)のパターンサイズを縮小することにより寄生容量
を低減できる可能性がある利点を有する他、前記立体的
に距離を保つので、外部接続電極(12)のパターンサイズ
をも縮小できる利点を有する。(G) Effect of the Invention As described above, the present invention has the plurality of wires (15), and thus has an advantage that the inductance of the wire (15) can be reduced. Also, the first and second wire loops (16) (1
Since the shape of 9) is three-dimensionally separated in the height direction, there is an advantage that the mutual inductance of the wires (15) can be reduced. Moreover, since it is a folded stitch bond, it has the advantage that the parasitic capacitance may be reduced by reducing the pattern size of the electrode pad (14), and since the distance is three-dimensionally maintained, the external connection electrode (12) There is an advantage that the pattern size can be reduced.

従って、従来よりもワイヤ(15)の低インダクタンス化を
実現し、高利得で安定した高周波半導体装置を提供でき
る。Therefore, the inductance of the wire (15) can be made lower than in the past, and a high-frequency and stable high-frequency semiconductor device can be provided.

【図面の簡単な説明】[Brief description of drawings]

第１図と第２図は本発明を説明する為の側面図、第３図
と第４図は本発明を説明する為の平面図、第５図Ａ乃至
第５図Ｇは本発明を説明する為の側面図、第６図は本発
明を説明する為の特性図、第７図は従来例を説明する為
の斜視図である。1 and 2 are side views for explaining the present invention, FIGS. 3 and 4 are plan views for explaining the present invention, and FIGS. 5A to 5G are for explaining the present invention. FIG. 6 is a side view for explaining the present invention, FIG. 6 is a characteristic view for explaining the present invention, and FIG. 7 is a perspective view for explaining a conventional example.

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】ＧａＡｓ半導体チップ上の電極と外部接続
用の電極との間を、前記外部接続用の電極から前記チッ
プ上の電極へと向かう第１のワイヤループと、該第１の
ワイヤループから連続し前記チップ上の電極で折り返し
て前記外部接続用の電極へと向かう第２のワイヤループ
とで接続した高周波半導体装置であって、 前記第１又は第２のワイヤループの一方は他方のワイヤ
ループの脇を高さ方向に１点又は２点でクロスした軌跡
を描き、 前記第１と第２のワイヤループは前記折り返した部分を
除き少なくとも５０μ以上の間隔を有することを特徴と
する高周波半導体装置。1. A first wire loop extending between an electrode on a GaAs semiconductor chip and an electrode for external connection from the electrode for external connection to an electrode on the chip, and the first wire loop. From the electrode on the chip and connected to a second wire loop extending toward the electrode for external connection, wherein one of the first or second wire loop is A high-frequency characterized by drawing a locus crossing the side of the wire loop at one point or two points in the height direction, and the first and second wire loops have an interval of at least 50 μ or more excluding the folded-back portion. Semiconductor device. 【請求項２】ＧａＡｓ半導体チップ上の電極と外部接続
用の電極との間を、前記外部接続用の電極から前記チッ
プ上の電極へと向かう第１のワイヤループと、該第１の
ワイヤループから連続し前記チップ上の電極で折り返し
て前記外部接続用の電極へと向かう第２のワイヤループ
とで接続した高周波半導体装置であって、 前記第１又は第２のワイヤループの一方は他方のワイヤ
ループより常に高い位置を通る軌跡を描くことを特徴と
する高周波半導体装置。2. A first wire loop extending from the electrode for external connection to the electrode on the chip between the electrode on the GaAs semiconductor chip and the electrode for external connection, and the first wire loop. From the electrode on the chip and connected to a second wire loop extending toward the electrode for external connection, wherein one of the first or second wire loop is A high-frequency semiconductor device characterized by drawing a locus that always passes through a position higher than the wire loop.
JP1036557A 1989-02-16 1989-02-16 High frequency semiconductor device Expired - Lifetime JPH0666352B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1036557A JPH0666352B2 (en) 1989-02-16 1989-02-16 High frequency semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1036557A JPH0666352B2 (en) 1989-02-16 1989-02-16 High frequency semiconductor device

Publications (2)

Publication Number Publication Date
JPH02215137A JPH02215137A (en) 1990-08-28
JPH0666352B2 true JPH0666352B2 (en) 1994-08-24

Family

ID=12473059

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1036557A Expired - Lifetime JPH0666352B2 (en) 1989-02-16 1989-02-16 High frequency semiconductor device

Country Status (1)

Country Link
JP (1) JPH0666352B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9812423B2 (en) * 2013-11-29 2017-11-07 Aoi Electronics Co., Ltd. Semiconductor device having wire formed with loop portion and method for producing the semiconductor device

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2567976B2 (en) * 1990-08-29 1996-12-25 シャープ株式会社 High frequency low noise semiconductor device
JP2525558Y2 (en) * 1991-01-11 1997-02-12 サンケン電気株式会社 Semiconductor device
JP2532304B2 (en) * 1991-01-14 1996-09-11 ローム株式会社 Wire bonding structure between the semiconductor chip and the substrate on which it is mounted
JP2728052B2 (en) * 1995-10-18 1998-03-18 日本電気株式会社 Semiconductor device
JP4629284B2 (en) * 2001-09-10 2011-02-09 ローム株式会社 Semiconductor device and manufacturing method thereof
US8016182B2 (en) 2005-05-10 2011-09-13 Kaijo Corporation Wire loop, semiconductor device having same and wire bonding method
US8008785B2 (en) * 2009-12-22 2011-08-30 Tessera Research Llc Microelectronic assembly with joined bond elements having lowered inductance
EP2688101A1 (en) * 2012-07-20 2014-01-22 ABB Technology AG Method for electrically connecting vertically positioned substrates
WO2015024597A1 (en) * 2013-08-21 2015-02-26 Osram Opto Semiconductors Gmbh Method for wire bonding and device produced thereby

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0625958Y2 (en) * 1987-06-16 1994-07-06 日本電気株式会社 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9812423B2 (en) * 2013-11-29 2017-11-07 Aoi Electronics Co., Ltd. Semiconductor device having wire formed with loop portion and method for producing the semiconductor device

Also Published As

Publication number Publication date
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