JP2728052B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2728052B2
JP2728052B2 JP7269942A JP26994295A JP2728052B2 JP 2728052 B2 JP2728052 B2 JP 2728052B2 JP 7269942 A JP7269942 A JP 7269942A JP 26994295 A JP26994295 A JP 26994295A JP 2728052 B2 JP2728052 B2 JP 2728052B2
Authority
JP
Japan
Prior art keywords
pad
semiconductor device
gnd
power supply
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP7269942A
Other languages
Japanese (ja)
Other versions
JPH09115945A (en
Inventor
正則 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
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Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP7269942A priority Critical patent/JP2728052B2/en
Publication of JPH09115945A publication Critical patent/JPH09115945A/en
Application granted granted Critical
Publication of JP2728052B2 publication Critical patent/JP2728052B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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  • Engineering & Computer Science (AREA)
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  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置に関
し、特に、配線におけるインダクタンスを低減させた半
導体装置に関する。The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having reduced wiring inductance.

【０００２】[0002]

【従来の技術】近年におけるＬＳＩデバイスは、高性能
化に伴い、低電圧かつ高速で多数の信号が動作するよう
に構成されている。そのため、旧来よりもノイズに対す
る余裕度が小さく、わずかなノイズによって誤動作を起
こす虞れが生じている。2. Description of the Related Art In recent years, LSI devices have been designed so that a large number of signals can be operated at a low voltage and at a high speed with the advance of performance. For this reason, the margin for noise is smaller than before, and there is a possibility that a slight noise may cause a malfunction.

【０００３】ＬＳＩデバイスの誤動作の原因となるノイ
ズは、データバス等における信号出力の多くが同時動作
（同時にハイレベルからローレベルに変化）する際に発
生する過渡電流ｉと、ＬＳＩデバイス素子内の電源／Ｇ
ＮＤ線に結合される配線に存在するインダクタンス及び
電気抵抗とによって発生し、その値は、以下の式で表さ
れる。[0003] Noise that causes malfunction of an LSI device includes a transient current i generated when many signal outputs on a data bus and the like operate simultaneously (change from a high level to a low level at the same time) and a noise in the LSI device element. Power / G
It is generated by the inductance and the electric resistance existing in the wiring coupled to the ND line, and its value is represented by the following equation.

【０００４】 δＶ＝ｎ・Ｌ・δｉ／δＴ＋ｎ・Ｒ・δｉ ・・・・・（式１） δＶ：電源／ＧＮＤの電位変動［Ｖ］＝ノイズ値 ｎ ：同時に動作する信号数［本］ Ｌ ：電源／ＧＮＤに結合される配線のインダクタンス
［Ｈ］ Ｒ ：電源／ＧＮＤに結合される配線の電気抵抗［Ω］ δｉ：電源電流の変化量［Ａ］ δｉ／δＴ：単位時間当たりの電源電流の変化［Ａ］＝
電源電流の立ち上がり ここで、（式１）からわかるように、ノイズを低減させ
るには以下の施策が考えられる。ΔV = n · L · δi / δT + n · R · δi (Equation 1) δV: Power supply / GND potential fluctuation [V] = Noise value n: Number of simultaneously operating signals [number] L : Inductance of wiring connected to power supply / GND [H] R: Electric resistance of wiring connected to power supply / GND [Ω] δi: Variation of power supply current [A] δi / δT: Power supply current per unit time Change [A] =
Here, as can be seen from (Equation 1), the following measures can be considered to reduce noise.

【０００５】同時に動作する信号本数を減らす。[0005] The number of simultaneously operating signals is reduced.

【０００６】電源／ＧＮＤに結合される配線のインダ
クタンスを低減させる。[0006] The inductance of the wiring coupled to the power supply / GND is reduced.

【０００７】電源電流の立ち上がりを鈍化させる。The rise of the power supply current is slowed down.

【０００８】電源／ＧＮＤに結合される配線の電気抵
抗を低減させる。[0008] The electric resistance of the wiring coupled to the power supply / GND is reduced.

【０００９】しかしながら、及びの施策において
は、ＬＳＩの性能を制限する施策であるため、実施する
ことは難しい。However, these measures are difficult to implement because they limit the performance of the LSI.

【００１０】また、例えば、電源／ＧＮＤに結合される
の配線のインダクタンスＬ＝１ｎＨ、電源／ＧＮＤに結
合される配線の電気抵抗Ｒ＝１００ｍΩ、同時に動作す
る信号本数ｎ＝１０本、電源電流の変化量δｉ＝１００
ｍＡ、立ち上がり時間δｔ＝１ｎｓｅｃの場合における
ノイズ値δＶを（式１）により求めると、ノイズ値δＶ
が全体で１．１Ｖになるのに対し、（式１）における第
１項（ｎ・Ｌ・δｉ／δＴ）の値が１Ｖとなり、ノイズ
値の大部分を占める。このことから、第２項（ｎ・Ｒ・
δｉ）によるノイズ値の影響は小さく、の実施による
ノイズ値の低減はあまり期待できない。Further, for example, the inductance L of the wiring coupled to the power supply / GND is 1 nH, the electric resistance R of the wiring coupled to the power supply / GND is 100 mΩ, the number of simultaneously operating signals n = 10, Change amount δi = 100
When the noise value δV in the case of mA and the rise time δt = 1 nsec is obtained by (Equation 1), the noise value δV
Becomes 1.1 V in total, whereas the value of the first term (n · L · δi / δT) in (Equation 1) becomes 1 V, which occupies most of the noise value. From this, the second term (n · R ·
The influence of the noise value due to δi) is small, and the reduction of the noise value by the implementation of δi) cannot be expected much.

【００１１】上記の理由から、の電源／ＧＮＤに結合
される配線のインダクタンスを低減させる施策を実施す
ることが、ノイズ値低減のために最も効果的である。For the above reasons, it is most effective to reduce the noise value by implementing a measure to reduce the inductance of the wiring coupled to the power supply / GND.

【００１２】ここで、インダクタンスは電気抵抗と同じ
ような性質を持っており、その値は、配線の長さに比例
し、また、配線が並列に接続された場合は、全体のイン
ダクタンスをＬ’とし、配線それぞれのインダクタンス
をＬとすると、Ｌ’＝１／｛Σ（１／Ｌi）｝と表現さ
れる。Here, the inductance has the same property as the electric resistance, and its value is proportional to the length of the wiring, and when the wiring is connected in parallel, the total inductance is L ′. And if the inductance of each wiring is L, it is expressed as L ′ = 1 / {(1 / L i )}.

【００１３】図４は、インダクタンスの値がＬである配
線をｎ本並列に接続した場合の全体のインダクタンスに
ついて説明するための図である。FIG. 4 is a diagram for explaining the overall inductance when n wirings having an inductance value of L are connected in parallel.

【００１４】図４に示すように、インダクタンスの値が
Ｌである配線をｎ本並列に接続した場合は、全体のイン
ダクタンスＬ’は、Ｌ’＝Ｌ／ｎとなり、１本の配線に
おけるインダクタンスの１／ｎ倍に減少する。As shown in FIG. 4, when n wirings having an inductance value of L are connected in parallel, the total inductance L 'is L' = L / n, and the inductance of one wiring is L '= L / n. It is reduced by a factor of 1 / n.

【００１５】ただし、配線を並列接続する場合は、配線
どうしの間隔を十分確保しないと相互インダクタンスの
影響により、並列接続の効果が薄れてしまい、全体のイ
ンダクタンスが１本の配線におけるインダクタンスの１
／ｎ倍まで減少しなくなる。例えば、ワイヤによる配線
を考えた場合、ワイヤどうしの間隔をワイヤ径の２倍以
上としなければ、相互インダクタンスの影響を受けるこ
とになる。However, when wirings are connected in parallel, if the spacing between the wirings is not sufficiently ensured, the effect of the parallel connection is reduced due to the influence of mutual inductance, and the overall inductance becomes one of the inductance of one wiring.
/ N times. For example, in the case of wiring using wires, unless the interval between the wires is set to be twice or more the wire diameter, the mutual inductance is affected.

【００１６】従来より、電源／ＧＮＤに結合される配線
のインダクタンスを低減させる施策としては、配線長を
短くしたり、並列接続を行う等の施策が実施されてきて
おり、以下に記載するような施策が考えられている。Conventionally, as measures for reducing the inductance of the wiring coupled to the power supply / GND, measures such as shortening the wiring length and performing parallel connection have been implemented. Measures are being considered.

【００１７】（１）特開昭６２−９８６３１号公報に開
示された施策 図５は、特開昭６２−９８６３１号公報に開示された施
策を示す図である。(1) Measures disclosed in Japanese Patent Application Laid-Open No. 62-98631 FIG. 5 is a diagram showing a measure disclosed in Japanese Patent Application Laid-Open No. 62-98631.

【００１８】図５に示すように本施策においては、半導
体素子１０５上に設けられた１つのボンディングパッド
（不図示）とステッチとなる電源／ＧＮＤ用リード１０
８とが複数のワイヤ１０２により接続されており、配線
の並列接続によりインダクタンスの低減が実現されてい
る。As shown in FIG. 5, in this measure, one bonding pad (not shown) provided on the semiconductor element 105 and a power / GND lead 10 serving as a stitch are provided.
8 are connected by a plurality of wires 102, and a reduction in inductance is realized by connecting the wires in parallel.

【００１９】（２）特開昭５９−１００５５０号公報に
開示された施策 図６は、特開昭５９−１００５５０号公報に開示された
施策を示す図である。(2) Measures disclosed in JP-A-59-100550 FIG. 6 is a diagram showing a measure disclosed in JP-A-59-100550.

【００２０】図６に示すように本施策においては、半導
体素子２０５に複数の電源／ＧＮＤ用パッド２０６が設
けられ、複数の電源／ＧＮＤ用パッド２０６がそれぞれ
異なるステッチ（不図示）と接続されており、配線の並
列接続によりインダクタンスの低減が実現されている。As shown in FIG. 6, in the present measure, the semiconductor element 205 is provided with a plurality of power / GND pads 206, and the plurality of power / GND pads 206 are connected to different stitches (not shown). Therefore, the inductance is reduced by connecting the wires in parallel.

【００２１】[0021]

【発明が解決しようとする課題】しかしながら、上述し
た従来の半導体装置においては以下に記載するような問
題点がある。However, the above-mentioned conventional semiconductor device has the following problems.

【００２２】（１）特開昭６２−９８６３１号公報に開
示されたものにおいて １つのボンディングパッドに複数のワイヤが接続される
構成であるが、多くの半導体素子においては、ボンディ
ング・パッドの大きさが□１５０μｍ程度と小さいた
め、１つのボンディング・パッドに複数のワイヤを設け
ることは困難である。特に、今後は、半導体装置の高集
積化の影響によりボンデイングパッド間の距離が短縮さ
れ、これに伴ってボンディングパッドのサイズも小さく
なるため、１つのボンディングパッドに複数のワイヤを
設けることは難しくなる。(1) In the structure disclosed in Japanese Patent Application Laid-Open No. 62-98631, a plurality of wires are connected to one bonding pad. However, in many semiconductor devices, the size of the bonding pad is large. Is as small as about 150 μm, it is difficult to provide a plurality of wires on one bonding pad. In particular, in the future, the distance between the bonding pads will be reduced due to the influence of the higher integration of the semiconductor device, and the size of the bonding pad will be reduced accordingly. Therefore, it is difficult to provide a plurality of wires on one bonding pad. .

【００２３】また、ボンディング・パッドを大きくした
場合においても、スペース的にはボンディングが可能と
なるが、度重なるボンディング時の応力によってパッド
及びその周辺に物理的ダメージ（クラック等）を受ける
虞れが生じ、半導体装置の信頼性が低下してしまう。Further, even when the bonding pad is enlarged, bonding can be performed in terms of space, but physical damage (cracks, etc.) may be caused on the pad and its periphery due to repeated stress during bonding. As a result, the reliability of the semiconductor device is reduced.

【００２４】（２）特開昭５９−１００５５０号公報に
開示されたものにおいて 図７は、半導体素子上にボンディングパッドを追加した
従来の一例を示す図であり、（ａ）は平面図、（ｂ）は
（ａ）に示すＡ−Ａ’断面図である。(2) In the device disclosed in Japanese Patent Application Laid-Open No. 59-100550, FIG. 7 is a diagram showing an example of a conventional device in which a bonding pad is added on a semiconductor element. FIG. (b) is an AA ′ cross-sectional view shown in (a).

【００２５】図７に示すように、半導体素子３０５上に
ボンディングパッド３０１の数を増やすために追加ボン
ディングパッド３０７を設けると、その分だけ半導体素
子３０５が大きくなってしまう。As shown in FIG. 7, when an additional bonding pad 307 is provided on the semiconductor element 305 in order to increase the number of bonding pads 301, the semiconductor element 305 becomes larger by that amount.

【００２６】例えば、ボンディングパッド３０１の大き
さを□１５０μｍ、ボンディングパッド３０１どうしの
間隔を３００μｍ，追加ボンディングパッド３０７の数
を５パッドとした場合、半導体素子３０５の大きさが、
追加ボンディングパッド３０７設置前に比べて約１．５
ｍｍ大きくなり、半導体素子の製造コストにおいてコス
トアップが生じてしまう。特に、今後は、半導体装置の
高速化の影響により発生するノイズ量が増加し、より多
くの追加ボンディング・パッドが必要とされるため、単
純にボンディング・パッドを追加する方法を採用した場
合は、製造コストの面におけるデメリットが大きい。For example, when the size of the bonding pads 301 is 150 μm, the interval between the bonding pads 301 is 300 μm, and the number of the additional bonding pads 307 is 5, the size of the semiconductor element 305 is
Approximately 1.5 compared to before installing additional bonding pad 307
mm, which leads to an increase in the manufacturing cost of the semiconductor element. In particular, in the future, the amount of noise generated due to the effect of the speeding up of the semiconductor device will increase and more additional bonding pads will be required. There are significant disadvantages in terms of manufacturing costs.

【００２７】本発明は、上述したような従来の技術が有
する問題点に鑑みてなされたものであって、半導体素子
に物理的ダメージを与えたり、半導体素子を大型化させ
たりすることなく、ノイズの発生を抑えることができる
半導体装置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the conventional technology, and has been made in consideration of noise reduction without physically damaging a semiconductor device or increasing the size of the semiconductor device. It is an object of the present invention to provide a semiconductor device capable of suppressing the generation of the semiconductor device.

【００２８】[0028]

【課題を解決するための手段】上記目的を達成するため
に本発明は、複数の信号用パッド及び電源／ＧＮＤ用パ
ッドからなる複数のボンディングパッドが端部において
１列に設けられた半導体素子と、複数のワイヤによって
前記ボンディングパッドのそれぞれと接続され、前記半
導体素子に対する信号の供給及び取込みを行うための複
数のステッチとを有してなる半導体装置において、前記
半導体素子上において前記電源／ＧＮＤ用パッドと接続
され、かつ、該電源／ＧＮＤ用パッドが接続されたステ
ッチと前記ワイヤによって接続される追加ボンディング
パッドを具備し、 該追加ボンディングパッドは、前記ボ
ンディングパッド列に対する垂直方向において、接続さ
れる前記電源／ＧＮＤ用パッドと同一線上に、かつ、前
記接続される電源／ＧＮＤ用パッドに対して前記半導体
素子の端部側に設置されていることを特徴とする。 According to the present invention, there is provided a semiconductor device having a plurality of bonding pads including a plurality of signal pads and a plurality of power / GND pads provided in a line at an end. A plurality of stitches connected to each of the bonding pads by a plurality of wires for supplying and taking in signals to and from the semiconductor element, wherein the power supply / GND for the power supply / GND is provided on the semiconductor element. It is connected to the pad, and includes an additional bonding pads power source / GND pads are connected by a connecting stitches with the wire, the additional bonding pad, the ball
Connection in the vertical direction to the
On the same line as the power / GND pad
The semiconductor for a power / GND pad to be connected
It is characterized by being installed on the end side of the element.

【００２９】[0029]

【００３０】また、複数の信号用パッド及び電源／ＧＮ
Ｄ用パッドからなる複数のボンディングパッドが端部に
おいて１列に設けられた半導体素子と、複数のワイヤに
よって前記ボンディングパッドのそれぞれと接続され、
前記半導体素子に対する信号の供給及び取込みを行うた
めの複数のステッチとを有してなる半導体装置におい
て、前記半導体素子上において前記電源／ＧＮＤ用パッ
ドと接続され、かつ、該電源／ＧＮＤ用パッドが接続さ
れたステッチと前記ワイヤによって接続される追加ボン
ディングパッドを具備し、 該追加ボンディングパッド
は、前記ボンディングパッド列に対する垂直方向におい
て、接続される前記電源／ＧＮＤ用パッドと同一線上に
並ばないように、かつ、前記接続される電源／ＧＮＤ用
パッドに対して前記半導体素子の端部側に設置されてい
ることを特徴とする。Further, a plurality of signal pads and a power supply / GN
Multiple bonding pads consisting of D pads at the end
Semiconductor elements and a plurality of wires
Therefore, it is connected to each of the bonding pads,
A signal is supplied to and taken into the semiconductor element.
Semiconductor device having a plurality of stitches
The power supply / GND package on the semiconductor element.
Connected to the power supply / GND pad.
Stitch and additional bon connected by said wire
Comprising a loading pad, 該追 pressure bonding pads, in a direction perpendicular to the bonding pad row, so not aligned on the power supply / GND pads of the same line connected, and power source / GND is the connection The semiconductor device is provided on an end side of the semiconductor element with respect to the pad.

【００３１】[0031]

【００３２】また、複数の信号用パッド及び電源／ＧＮ
Ｄ用パッドからなる複数のボンディングパッドが端部に
おいて１列に設けられた半導体素子と、複数のワイヤに
よって前記信号用パッドとそれぞれ接続され、前記半導
体素子に対する信号の供給及び取込みを行うための複数
のステッチとを有してなる半導体装置において、前記半
導体素子上に、前記ステッチと前記ワイヤによって接続
される追加ボンディングパッドを具備し、１つの前記電
源／ＧＮＤ用パッドに２つの前記追加ボンディングパッ
ドが接続され、前記２つの追加ボンディングパッドの位
置関係が、接続される電源／ＧＮＤ用パッドの中心を通
り前記ボンディングパッド列に垂直な軸に対して対象と
なることを特徴とする。Further, a plurality of signal pads and a power supply / GN
A plurality of bonding pads made up of D pads are provided at one end in a row, and a plurality of bonding pads are connected to the signal pads by a plurality of wires, respectively, for supplying and taking in signals to the semiconductor elements. A semiconductor device having an additional bonding pad on the semiconductor element, the additional bonding pad being connected to the stitch by the wire, and the power supply / GND pad having two additional bonding pads. The positional relationship between the connected and the two additional bonding pads is symmetrical with respect to an axis passing through the center of the connected power / GND pad and perpendicular to the bonding pad row.

【００３３】また、前記各ワイヤは、お互いに外径の２
倍以上離されて配設されていることを特徴とする。Each of the wires has an outer diameter of 2 mm.
It is characterized by being arranged at least twice as far apart.

【００３４】（作用）上記のように構成された本発明に
おいては、半導体素子上に電源／ＧＮＤ用パッドに接続
された追加ボンディングパッドが設けられているので、
電源／ＧＮＤ用パッドが接続されるステッチと追加ボン
ディングパッドとをワイヤにより接続すれば、ワイヤの
インダクタンス低減のために電源／ＧＮＤ用パッドに複
数のワイヤを接続することはない。(Function) In the present invention configured as described above, the additional bonding pad connected to the power / GND pad is provided on the semiconductor element.
If the stitches to which the power / GND pads are connected and the additional bonding pads are connected by wires, a plurality of wires are not connected to the power / GND pads to reduce the inductance of the wires.

【００３５】また、追加ボンディングパッドをボンディ
ングパッド列以外の場所に設ければ、追加ボンディング
パッドの設定により半導体素子が大型化することはな
い。Further, if the additional bonding pad is provided in a place other than the bonding pad row, the size of the semiconductor element does not increase due to the setting of the additional bonding pad.

【００３６】[0036]

【発明の実施の形態】以下に、本発明の実施の形態につ
いて図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００３７】（第１の実施の形態）図１は、本発明の半
導体装置の第１の実施の形態を示す図であり、（ａ）は
平面図、（ｂ）は（ａ）に示すＡ−Ａ’断面図である。(First Embodiment) FIGS. 1A and 1B are diagrams showing a first embodiment of a semiconductor device according to the present invention, wherein FIG. 1A is a plan view, and FIG. It is -A 'sectional drawing.

【００３８】本形態は図１に示すように、半導体素子５
と、半導体素子５への信号の供給及び半導体素子５から
の信号の取込みを行うための複数のステッチ３と、半導
体素子５上に設けられ、ステッチ３との信号のやりとり
を行うための複数のボンディングパッド１と、各ボンデ
ィングパッド１と各ステッチ３とを接続するワイヤ２と
から構成されており、ボンディングパッド１は、信号用
パッド８と、電源／ＧＮＤ用パッド６と、Ａｌ配線４に
よって電源／ＧＮＤ用パッド６と接続され、ワイヤ２の
インダクタンスを低減させるために設けられた追加ボン
ディングパッド７とから成っている。なお、追加ボンデ
ィングパッド７は、ボンディングパッド１の列に対する
垂直方向において電源／ＧＮＤ用パッド７と同一線上
に、かつ、電源／ＧＮＤ用パッド６に対して半導体素子
５の端部側に設置されている。In the present embodiment, as shown in FIG.
A plurality of stitches 3 for supplying a signal to the semiconductor element 5 and taking in a signal from the semiconductor element 5, and a plurality of stitches provided on the semiconductor element 5 for exchanging a signal with the stitch 3 The bonding pad 1 includes a bonding pad 1, a wire 2 connecting each bonding pad 1 and each stitch 3, and the bonding pad 1 is connected to a power supply by a signal pad 8, a power supply / GND pad 6, and an Al wiring 4. / GND pad 6 and an additional bonding pad 7 provided to reduce the inductance of the wire 2. The additional bonding pad 7 is provided on the same line as the power supply / GND pad 7 in a direction perpendicular to the column of the bonding pads 1 and on the end side of the semiconductor element 5 with respect to the power supply / GND pad 6. I have.

【００３９】以下に、図１に示した半導体装置の製造方
法について説明する。Hereinafter, a method of manufacturing the semiconductor device shown in FIG. 1 will be described.

【００４０】まず、半導体素子５を熱硬化性樹脂やロウ
材等の接着材によりパッケージ上の所定の位置に固着さ
せる（工程１）。First, the semiconductor element 5 is fixed at a predetermined position on the package with an adhesive such as a thermosetting resin or a brazing material (step 1).

【００４１】次に、半導体素子５上の追加ボンディング
パッド７と所定のステッチ３とをワイヤ２にてボンディ
ングにより接続する（工程２）。Next, the additional bonding pad 7 on the semiconductor element 5 and the predetermined stitch 3 are connected by bonding with the wire 2 (step 2).

【００４２】次に、半導体素子５上のボンディングパッ
ド１と所定のステッチ３とをワイヤ２にてボンディング
により接続する（工程３）。Next, the bonding pad 1 on the semiconductor element 5 is connected to a predetermined stitch 3 by bonding with a wire 2 (step 3).

【００４３】ここで、電源／ＧＮＤ用パッド６において
は、その電源／ＧＮＤ用パッド６とＡｌ配線４により接
続されている追加ボンディングパッド７と接続されてい
るステッチ３と接続されるようにする。Here, the power supply / GND pad 6 is connected to the stitch 3 connected to the additional bonding pad 7 connected to the power supply / GND pad 6 and the Al wiring 4.

【００４４】また、この際、電源／ＧＮＤ用パッド６と
接続されるワイヤ２と追加ボンディングパッド７と接続
されるワイヤ２との間隔は、ワイヤ２の外径の２倍以上
とする。At this time, the distance between the wire 2 connected to the power / GND pad 6 and the wire 2 connected to the additional bonding pad 7 is at least twice the outer diameter of the wire 2.

【００４５】その後、パッケージを樹脂や金属キャップ
等で封止する（工程４）。Thereafter, the package is sealed with a resin, a metal cap or the like (Step 4).

【００４６】上述した一連の工程においては、従来の半
導体装置の製造工程と比べてボンディングパッド１の数
とそれに伴うワイヤ２の数が増加したことのみが異なる
ものであるため、１つのボンディングパッド１に対して
複数のワイヤが接続されることはなく、ボンディングパ
ッド１が物理的ダメージを受けることはない。In the above-described series of steps, only the number of bonding pads 1 and the number of wires 2 associated therewith are different from those of the conventional semiconductor device manufacturing process. Is not connected to the bonding pad 1, and the bonding pad 1 is not physically damaged.

【００４７】また、ワイヤ２の配置においては図１
（ｂ）に示すように、３次元的にもワイヤ２どうしの間
隔を十分確保することができ、技術的にも現在のボンデ
ィング装置であればワイヤ形状を制御することが可能で
あるため、量産性に問題はない。このため、ボンディン
グ工程において通常の半導体装置より信頼性上劣ること
はない。FIG. 1 shows the arrangement of the wires 2.
As shown in (b), a sufficient space between the wires 2 can be ensured three-dimensionally, and the wire shape can be controlled technically with a current bonding apparatus. There is no problem in sex. For this reason, the reliability is not inferior to the ordinary semiconductor device in the bonding step.

【００４８】さらに、今後の半導体装置の高集積化を考
えた場合においても、ボンディングパッド１側における
製造工程は何ら通常のボンディングと変わらないため、
常に最先端のボンディング技術を利用することができ、
追加ボンディングパッド７を設けることによる技術的な
制約を受けることはない。また、ステッチ３側において
も、ステッチ３の幅として１５０μｍ以上あれば、２本
以上のワイヤ２をボンディングすることは通常のボンデ
イングと比べて技術的に大きな差はない。なお、ステッ
チ３側を２段構造とすれば、さらなる微細化にも対応す
ることができる。Further, even in the case where the integration of the semiconductor device is considered to be higher in the future, the manufacturing process on the bonding pad 1 side is not different from the normal bonding.
You can always use the most advanced bonding technology,
There is no technical restriction due to the provision of the additional bonding pad 7. Also, on the stitch 3 side, if the width of the stitch 3 is 150 μm or more, bonding of two or more wires 2 is not technically much different from ordinary bonding. If the stitch 3 side has a two-stage structure, it is possible to cope with further miniaturization.

【００４９】上記のように構成された半導体装置におい
ては、例えば、□１５０μｍ程度のサイズの追加ボンデ
ィングパッド７を設けた場合、半導体素子５のサイズを
約５００μｍ程度大きくするだけで、追加ボンディング
パッド７を制限なく増やすことができ、半導体素子５の
大型化を防ぐことができる。In the semiconductor device configured as described above, for example, when the additional bonding pad 7 having a size of about 150 μm is provided, the size of the semiconductor element 5 is increased by about 500 μm, and the additional bonding pad 7 is formed. Can be increased without limitation, and an increase in the size of the semiconductor element 5 can be prevented.

【００５０】これにより、ワイヤ２の数も制限なく増や
すことができ、ノイズの発生の低減を図ることができ
る。また、半導体素子５の大型化を防止することができ
ることから、半導体素子５の製造歩留まりを向上させ、
製造コストの低減を図ることができる。As a result, the number of wires 2 can be increased without limitation, and the occurrence of noise can be reduced. In addition, since the size of the semiconductor element 5 can be prevented from increasing, the production yield of the semiconductor element 5 can be improved,
Manufacturing costs can be reduced.

【００５１】（第２の実施の形態）図２は、本発明の半
導体装置の第２の実施の形態を示す図であり、（ａ）は
平面図、（ｂ）は（ａ）に示すＡ−Ａ’断面図である。(Second Embodiment) FIGS. 2A and 2B are views showing a semiconductor device according to a second embodiment of the present invention, wherein FIG. 2A is a plan view, and FIG. It is -A 'sectional drawing.

【００５２】本形態は図２に示すように、第１の実施の
形態において示したものと比べて、追加ボンディングパ
ッド１７が、ボンディングパッド１１の列に対して垂直
方向に電源／ＧＮＤ用パッド７と並ばないように設置さ
れている点のみが異なるものである。In this embodiment, as shown in FIG. 2, an additional bonding pad 17 is provided in the power supply / GND pad 7 in a direction perpendicular to the row of the bonding pads 11 as compared with that shown in the first embodiment. The only difference is that they are installed so that they do not line up with.

【００５３】本形態においては、第１の実施の形態にお
いて示したものと比べて、ワイヤ１２どうしの間隔を広
くすることができるため、ワイヤ１２どうしにおいて発
生する相互インダクタンスの影響を低減させることがで
きる。In this embodiment, since the distance between the wires 12 can be made wider than that shown in the first embodiment, the effect of mutual inductance generated between the wires 12 can be reduced. it can.

【００５４】（第３の実施の形態）図３は、本発明の半
導体装置の第３の実施の形態を示す図であり、（ａ）は
平面図、（ｂ）は（ａ）に示すＡ−Ａ’断面図である。(Third Embodiment) FIGS. 3A and 3B are views showing a semiconductor device according to a third embodiment of the present invention, wherein FIG. 3A is a plan view, and FIG. It is -A 'sectional drawing.

【００５５】本形態は図３に示すように、第１の実施の
形態において示したものと比べて、１つの電源／ＧＮＤ
用パッド２６に対して２つの追加ボンディングパッド２
７がＡｌ配線２４によってそれぞれ接続され、電源／Ｇ
ＮＤ用パッド２６に対して半導体素子２５の端部側に設
けられている点と、電源／ＧＮＤ用パッド２６にはワイ
ヤ２２が接続されていない点が異なるものである。な
お、２つの追加ボンディングパッド２７の設置位置関係
は、２つの追加ボンディングパッドが接続される電源／
ＧＮＤ用パッド２６の中心を通りボンディングパッド２
１の列に垂直な軸を設定した場合に、この軸に対して対
象となる関係である。In this embodiment, as shown in FIG. 3, one power supply / GND is different from that shown in the first embodiment.
Additional bonding pad 2 for pad 26
7 are connected by Al wiring 24, respectively,
It is different from the ND pad 26 in that the wire 22 is not connected to the power / GND pad 26 on the end side of the semiconductor element 25. The positional relationship between the two additional bonding pads 27 depends on the power supply / power supply to which the two additional bonding pads 27 are connected.
Bonding pad 2 passing through the center of GND pad 26
When a vertical axis is set in one column, the relation is an object to this axis.

【００５６】本形態においては、第１の実施の形態にお
いて示したものと比べて、ワイヤ２２の長さを短くする
ことができるため、ワイヤ２２におけるインダクタンス
を低減することができる。In the present embodiment, since the length of the wire 22 can be made shorter than that shown in the first embodiment, the inductance of the wire 22 can be reduced.

【００５７】また、ステッチ２３の幅を２５０μｍ以上
とすれば、電源／ＧＮＤ用パッド２６に対してもワイヤ
２２を接続することができ、ワイヤ２２の本数の増加に
より、より一層のインダクタンスの低減を図ることがで
きる。If the width of the stitch 23 is 250 μm or more, the wire 22 can be connected to the power / GND pad 26, and the inductance can be further reduced by increasing the number of wires 22. Can be planned.

【００５８】[0058]

【発明の効果】本発明は、以上説明したように構成され
ているので以下に記載するような効果を奏する。Since the present invention is configured as described above, it has the following effects.

【００５９】請求項１に記載のものにおいては、半導体
素子上において電源／ＧＮＤ用パッドと接続され、か
つ、該電源／ＧＮＤ用パッドが接続されたステッチとワ
イヤによって接続される追加ボンディングパッドを設け
たため、１つの電源／ＧＮＤ用パッドに複数のワイヤを
接続することによる半導体素子への物理的ダメージを与
えることなく、ワイヤのインダクタンスの低減を図るこ
とができる。According to the first aspect of the present invention, an additional bonding pad is provided on the semiconductor element, which is connected to the power supply / GND pad and which is connected by a wire to a stitch to which the power supply / GND pad is connected. Therefore, it is possible to reduce the inductance of the wire without physically damaging the semiconductor element by connecting a plurality of wires to one power / GND pad.

【００６０】それにより、製造工程において従来のボン
ディング技術をそのまま利用でき、また、装置の信頼性
を高めることができ、さらに、ノイズの発生を低減させ
ることができる。As a result, the conventional bonding technique can be used as it is in the manufacturing process, the reliability of the device can be improved, and the generation of noise can be reduced.

【００６１】また、追加ボンディングパッドを、ボンデ
ィングパッド列に対する垂直方向において、接続される
電源／ＧＮＤ用パッドと同一線上に、かつ、接続される
電源／ＧＮＤ用パッドに対して半導体素子の端部側に設
けたため、半導体素子を大型化させることなく、ワイヤ
のインダクタンスの低減を図ることができる。[0061] Moreover, an additional bonding pad, in the direction perpendicular to the bonding pad row, connected to the power supply / GND pads on the same line, and the end side of the semiconductor element to the connected the power supply / GND pads , The wire inductance can be reduced without increasing the size of the semiconductor element.

【００６２】それにより、ノイズ発生低減のためのコス
トアップを抑えることができる。As a result, an increase in cost for reducing noise generation can be suppressed.

【００６３】請求項２に記載のものにおいては、追加ボ
ンディングパッドを、ボンディングパッド列に対する垂
直方向において、接続される電源／ＧＮＤ用パッドと同
一線上に並ばないように、かつ、接続される電源／ＧＮ
Ｄ用パッドに対して半導体素子の端部側に設けたため、
請求項１に記載のものと同様の効果を奏する。According to the second aspect of the present invention, the additional bonding pads are arranged so as not to be arranged on the same line as the power supply / GND pad to be connected in the direction perpendicular to the row of bonding pads and to the power supply / GN
Because it was provided on the end side of the semiconductor element with respect to the pad for D,
An effect similar to that of the first aspect is obtained.

【００６４】[0064]

【００６５】請求項３に記載のものにおいては、電源／
ＧＮＤ用パッドとステッチとのワイヤによる接続を行わ
ず、追加ボンディングパッドを介して電源用パッドとス
テッチとの接続を行う構成としたため、ワイヤの長さを
短くすることができ、さらにインダクタンスの低減を図
ることができる。According to the third aspect of the present invention, the power supply /
The configuration is such that the connection between the power supply pad and the stitch is performed via the additional bonding pad without connecting the GND pad and the stitch by wire, so that the length of the wire can be shortened and the inductance can be further reduced. Can be planned.

【００６６】請求項４に記載のものにおいては、各ワイ
ヤを、お互いに外径の２倍以上離さして配設したため、
相互インダクタンスの発生を防ぐことができる。According to the fourth aspect of the present invention, since the wires are arranged at a distance of at least twice the outer diameter from each other,
The occurrence of mutual inductance can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体装置の第１の実施の形態を示す
図であり、（ａ）は平面図、（ｂ）は（ａ）に示すＡ−
Ａ’断面図である。FIGS. 1A and 1B are diagrams showing a first embodiment of a semiconductor device of the present invention, wherein FIG. 1A is a plan view, and FIG.
It is A 'sectional drawing.

【図２】本発明の半導体装置の第２の実施の形態を示す
図であり、（ａ）は平面図、（ｂ）は（ａ）に示すＡ−
Ａ’断面図である。FIGS. 2A and 2B are diagrams showing a second embodiment of the semiconductor device of the present invention, wherein FIG. 2A is a plan view, and FIG.
It is A 'sectional drawing.

【図３】本発明の半導体装置の第３の実施の形態を示す
図であり、（ａ）は平面図、（ｂ）は（ａ）に示すＡ−
Ａ’断面図である。FIGS. 3A and 3B are diagrams showing a third embodiment of the semiconductor device of the present invention, wherein FIG. 3A is a plan view, and FIG.
It is A 'sectional drawing.

【図４】インダクタンスの値がＬである配線をｎ本並列
に接続した場合の全体のインダクタンスについて説明す
るための図である。FIG. 4 is a diagram for explaining an overall inductance when n wirings having an inductance value of L are connected in parallel;

【図５】特開昭６２−９８６３１号公報に開示された施
策を示す図である。FIG. 5 is a diagram showing a measure disclosed in Japanese Patent Application Laid-Open No. 62-98631.

【図６】特開昭５９−１００５５０号公報に開示された
施策を示す図である。FIG. 6 is a diagram showing a measure disclosed in JP-A-59-100550.

【図７】半導体素子上にボンディングパッドを追加した
従来の一例を示す図であり、（ａ）は平面図、（ｂ）は
（ａ）に示すＡ−Ａ’断面図である。FIGS. 7A and 7B are diagrams showing an example of the related art in which a bonding pad is added on a semiconductor element, wherein FIG. 7A is a plan view, and FIG.

【符号の説明】[Explanation of symbols]

１，１１，２１ ボンディングパッド ２，１２，２２ ワイヤ ３，１３，２３ ステッチ ４，１４，２４ Ａｌ配線 ５，１５，２５ 半導体素子 ６，１６，２６ 電源／ＧＮＤ用パッド ７，１７，２７ 追加ボンディングパッド ８，１８，２８ 信号用パッド 1,11,21 Bonding pad 2,12,22 Wire 3,13,23 Stitch 4,14,24 Al wiring 5,15,25 Semiconductor element 6,16,26 Power supply / GND pad 7,17,27 Additional bonding Pad 8,18,28 Signal pad

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 複数の信号用パッド及び電源／ＧＮＤ用
パッドからなる複数のボンディングパッドが端部におい
て１列に設けられた半導体素子と、複数のワイヤによっ
て前記ボンディングパッドのそれぞれと接続され、前記
半導体素子に対する信号の供給及び取込みを行うための
複数のステッチとを有してなる半導体装置において、 前記半導体素子上において前記電源／ＧＮＤ用パッドと
接続され、かつ、該電源／ＧＮＤ用パッドが接続された
ステッチと前記ワイヤによって接続される追加ボンディ
ングパッドを具備し、 該追加ボンディングパッドは、前記ボンディングパッド
列に対する垂直方向において、接続される前記電源／Ｇ
ＮＤ用パッドと同一線上に、かつ、前記接続される電源
／ＧＮＤ用パッドに対して前記半導体素子の端部側に設
置されていることを特徴とする半導体装置。 A semiconductor element having a plurality of bonding pads including a plurality of signal pads and a power supply / GND pad provided in a row at an end, and a plurality of wires connected to each of the bonding pads; In a semiconductor device having a plurality of stitches for supplying and receiving a signal to and from a semiconductor element, the power supply / GND pad is connected to the semiconductor element and the power supply / GND pad is connected to the semiconductor device. It comprises an additional bonding pads connected by stitching to the wire that is, the additional bonding pads, the bonding pads
The power supply / G connected in the vertical direction to the columns
Power supply on the same line as the ND pad and connected to the ND pad
/ Provided on the end side of the semiconductor element with respect to the GND pad.
A semiconductor device, comprising: 【請求項２】 複数の信号用パッド及び電源／ＧＮＤ用
パッドからなる複数のボンディングパッドが端部におい
て１列に設けられた半導体素子と、複数のワイヤによっ
て前記ボンディングパッドのそれぞれと接続され、前記
半導体素子に対する信号の供給及び取込みを行うための
複数のステッチとを有してなる半導体装置において、 前記半導体素子上において前記電源／ＧＮＤ用パッドと
接続され、かつ、該電源／ＧＮＤ用パッドが接続された
ステッチと前記ワイヤによって接続される追加ボンディ
ングパッドを具備し、 該追 加ボンディングパッドは、前記ボンディングパッド
列に対する垂直方向において、接続される前記電源／Ｇ
ＮＤ用パッドと同一線上に並ばないように、かつ、前記
接続される電源／ＧＮＤ用パッドに対して前記半導体素
子の端部側に設置されていることを特徴とする半導体装
置。2. A plurality of signal pads and a power supply / GND
Multiple bonding pads consisting of pads
Semiconductor devices arranged in a row and multiple wires.
And connected to each of the bonding pads,
For supplying and taking in signals to semiconductor devices
In a semiconductor device having a plurality of stitches, the power / GND pad and the semiconductor device may be provided.
Connected and the power / GND pad is connected
Additional bondy connected by stitches and said wires
Comprising a Ngupaddo, 該追 pressure bonding pads, in a direction perpendicular to the bonding pad row, the power supply / G is connected
A semiconductor device, wherein the semiconductor device is provided so as not to be arranged on the same line as an ND pad and at an end of the semiconductor element with respect to the connected power supply / GND pad. 【請求項３】 複数の信号用パッド及び電源／ＧＮＤ用
パッドからなる複数のボンディングパッドが端部におい
て１列に設けられた半導体素子と、複数のワイヤによっ
て前記信号用パッドとそれぞれ接続され、前記半導体素
子に対する信号の供給及び取込みを行うための複数のス
テッチとを有してなる半導体装置において、 前記半導体素子上に、前記ステッチと前記ワイヤによっ
て接続される追加ボンディングパッドを具備し、 １つの前記電源／ＧＮＤ用パッドに２つの前記追加ボン
ディングパッドが接続され、前記２つの追加ボンディン
グパッドの位置関係が、接続される電源／ＧＮＤ用パッ
ドの中心を通り前記ボンディングパッド列に垂直な軸に
対して対象となることを特徴とする半導体装置。 3. A semiconductor device in which a plurality of bonding pads including a plurality of signal pads and a power / GND pad are provided at one end in a line, and the plurality of bonding pads are connected to the signal pads by a plurality of wires, respectively. A semiconductor device having a plurality of stitches for supplying and taking in signals to and from a semiconductor element, comprising: an additional bonding pad connected to the stitch and the wire on the semiconductor element; Two additional bonding pads are connected to a power / GND pad, and a positional relationship between the two additional bonding pads is determined with respect to an axis passing through the center of the connected power / GND pad and perpendicular to the bonding pad row. A semiconductor device, which is an object. 【請求項４】 請求項１乃至３のいずれか１項に記載の
半導体装置において、 前記各ワイヤは、お互いに外径
の２倍以上離されて配設されていることを特徴とする半
導体装置。 4. The semiconductor device according to any one of claims 1 to 3, wherein each wire is a semiconductor device characterized by more than 2 times the outer diameter of isolated and are disposed to one another .
JP7269942A 1995-10-18 1995-10-18 Semiconductor device Expired - Lifetime JP2728052B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7269942A JP2728052B2 (en) 1995-10-18 1995-10-18 Semiconductor device

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Application Number Priority Date Filing Date Title
JP7269942A JP2728052B2 (en) 1995-10-18 1995-10-18 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH09115945A JPH09115945A (en) 1997-05-02
JP2728052B2 true JP2728052B2 (en) 1998-03-18

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JP (1) JP2728052B2 (en)

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