JP2706167B2 - IC chip mounting structure - Google Patents
IC chip mounting structureInfo
- Publication number
- JP2706167B2 JP2706167B2 JP2006417A JP641790A JP2706167B2 JP 2706167 B2 JP2706167 B2 JP 2706167B2 JP 2006417 A JP2006417 A JP 2006417A JP 641790 A JP641790 A JP 641790A JP 2706167 B2 JP2706167 B2 JP 2706167B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- conductor layer
- mounting structure
- bonding wire
- metal body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49112—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49174—Stacked arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Description
【発明の詳細な説明】 概要 高速信号処理用ICに適したICチップの実装構造に関
し、 実装されたICチップにおける入出力間の漏話を抑圧す
ることを目的とし、 第１の導体層、第１の絶縁体層、第２の導体層、第２
の絶縁体層及び第３の導体層をこの順に積層してなる回
路基板と、ICチップとを該ICチップの上面と上記第２の
導体層とが概略同一平面上に位置するように金属体上に
固着するようにしたICチップの実装構造において、上記
第２の導体層は高速信号用の伝送ラインと、該伝送ライ
ンの近傍に設けられた、上記第１及び第３の導体層に導
通する接地パターンとを含んでなり、上記ICチップの上
面には、上記伝送ラインが第１のボンディングワイヤに
より接続される信号用パッドと該信号用パッドを囲むよ
うにして設けられた接地用パッドとが形成されており、
該接地用パッドは上記接地パターン及び第３の導体層と
第２のボンディングワイヤにより接続されるようにして
構成する。The present invention relates to a mounting structure of an IC chip suitable for a high-speed signal processing IC, and aims at suppressing crosstalk between input and output of the mounted IC chip. Insulator layer, second conductor layer, second conductor layer
A circuit board formed by laminating an insulator layer and a third conductor layer in this order, and an IC chip such that the upper surface of the IC chip and the second conductor layer are positioned substantially on the same plane. In the mounting structure of the IC chip fixed to the upper side, the second conductor layer is connected to the transmission line for high-speed signal and the first and third conductor layers provided near the transmission line. A signal pad to which the transmission line is connected by a first bonding wire and a ground pad provided so as to surround the signal pad are formed on the upper surface of the IC chip. Has been
The ground pad is configured to be connected to the ground pattern and the third conductor layer by a second bonding wire.
産業上の利用分野 本発明は、光中継器等に使用される高速信号処理用IC
に適したICチップの実装構造に関する。The present invention relates to a high-speed signal processing IC used for an optical repeater or the like.
The present invention relates to a mounting structure of an IC chip suitable for a device.
近年、光伝送路として極めて広帯域なものが実用され
るようになり、高速伝送システムの適用範囲が大幅に拡
大されつつある。今日では、1.6Gb/sシステムの幹線系
への導入が進められており、将来的には更に高速化が予
想される。このような所謂マイクロ波領域の信号を取り
扱うシステムを実現するためには、マイクロ波領域で動
作が可能なICチップの設計が必要になることはもちろん
のこと、この種の高速信号処理用ICチップの実装構造の
最適化が必要になる。具体的には、５〜10Gb/sの信号を
取り扱うシステムにおいて光／電気変換回路で変換され
た信号レベルを高めるための等化増幅回路やタイミング
信号を抽出するためのタイミング抽出回路では、広帯域
且つ高利得（60dB程度）な特性が必要になるので、これ
らの回路が実現されるICチップにあっては、そのICチッ
プを実装したときに、入出力間の漏話が少なくとも10GH
zまでの信号に対して十分に抑圧されていることが必要
になる。In recent years, extremely wideband optical transmission lines have come into practical use, and the application range of high-speed transmission systems has been greatly expanded. Today, 1.6 Gb / s systems are being introduced into the trunk system, and further increases in speed are expected in the future. In order to realize such a system that handles signals in the so-called microwave range, it is necessary to design an IC chip that can operate in the microwave range, as well as this kind of high-speed signal processing IC chip. It is necessary to optimize the mounting structure. Specifically, in a system that handles signals of 5 to 10 Gb / s, an equalizing amplifier circuit for increasing a signal level converted by an optical / electrical conversion circuit and a timing extraction circuit for extracting a timing signal have a wide band and Since high gain (about 60dB) characteristics are required, the crosstalk between input and output should be at least 10 GHz when the IC chip is mounted on these IC chips.
It is necessary that the signal up to z be sufficiently suppressed.
従来の技術 従来、高速信号処理用のICチップであって高利得を有
したICチップを実装する場合の入出力間漏話抑圧対策と
しては次のようなものがある。2. Description of the Related Art Conventionally, there are the following countermeasures against crosstalk between input and output when an IC chip for high-speed signal processing and having a high gain is mounted.
ICチップを大型なチップサイズにして、入力パッド
と出力パッド間の距離を大きくとる。Increase the distance between input pads and output pads by making the IC chip a large chip size.
３層の導体層の間に２層の絶縁体層を挟み込んで構
成されるトリプレート型の回路基板を用いて、伝送線路
間での空間結合を抑圧する。Spatial coupling between transmission lines is suppressed by using a triplate-type circuit board formed by sandwiching two insulator layers between three conductor layers.
発明が解決しようとする課題 上述の、の対策を行った場合、ICチップの入出力
パッドに対してボンディングワイヤ接続を行っていない
状態では、10GHzまでの周波数に対しては約70dB程度の
漏話減衰量を確保することができるが、実際にICチップ
の入出力パッドと回路基板の伝送線路とをボンディング
ワイヤ接続すると、10GHzの周波数で漏話減衰量が約30d
B程度にまで低下し、そのICチップが高利得の回路が実
現されているものである場合には、回路が発振してしま
うことになる。Problems to be Solved by the Invention When the above-mentioned measures are taken, when no bonding wire is connected to the input / output pads of the IC chip, the crosstalk attenuation of about 70 dB for frequencies up to 10 GHz. However, when the input / output pads of the IC chip and the transmission line of the circuit board are actually connected by bonding wires, the crosstalk attenuation at the frequency of 10 GHz is about 30 d.
If the IC chip has a high gain circuit, the circuit will oscillate.
本発明はこのような技術的課題に鑑みて創作されたも
ので、実装されたICチップにおける入出力間の漏話を抑
圧することを目的としている。The present invention has been made in view of such a technical problem, and has as its object to suppress crosstalk between input and output in a mounted IC chip.
課題を解決するための手段 上述した技術的課題を解決するためになされた本発明
のICチップの実装構造は、第１図に示すように、第１の
導体層２、第１の絶縁体層４、第２の導体層６、第２の
絶縁体層８及び第３の導体層10をこの順に積層してなる
回路基板12と、ICチップ14とを該ICチップ14の上面と上
記第２の導体層６とが概略同一平面上に位置するように
金属体16上に固着するようにしたICチップの実装構造に
おいて、上記第２の導体層６は高速信号用の伝送ライン
6aと、該伝送ライン6aの近傍に設けられた、上記第１及
び第３の導体層2,10に導通する接地パターン6bとを含ん
でなり、上記ICチップ14の上面には、上記伝送ライン6a
が第１のボンディングワイヤ18により接続される信号用
パッド20と該信号用パッド20を囲むようにして設けられ
た接地用パッド22とが形成されており、該接地用パッド
22は上記接地パターン6b及び第３の導体層10と第２のボ
ンディングワイヤ（24）により接続されているものであ
る。Means for Solving the Problems The mounting structure of the IC chip of the present invention made to solve the above-mentioned technical problems includes a first conductor layer 2, a first insulator layer, as shown in FIG. 4, a circuit board 12 formed by laminating a second conductor layer 6, a second insulator layer 8, and a third conductor layer 10 in this order, and an IC chip 14 with the upper surface of the IC chip 14 and the second In the mounting structure of the IC chip, the second conductor layer 6 is fixed to the metal body 16 so that the second conductor layer 6 is positioned substantially on the same plane as the second conductor layer 6.
6a and a ground pattern 6b provided in the vicinity of the transmission line 6a and connected to the first and third conductor layers 2 and 10. 6a
Are formed with a signal pad 20 connected by the first bonding wire 18 and a ground pad 22 provided so as to surround the signal pad 20.
Reference numeral 22 denotes a connection between the ground pattern 6b and the third conductor layer 10 via a second bonding wire (24).
ICチップ14は、図示のように絶縁用の基板26を介して
金属体16上に固着されていても良いし、絶縁用の基板26
を介さずに直接金属体16上に固着されていても良い。The IC chip 14 may be fixed on the metal body 16 via an insulating substrate 26 as shown in the drawing, or may be
It may be fixed directly on the metal body 16 without any intervening.
作用 本発明の構成によると、伝送ライン6aと信号用パッド
20とを接続する第１のボンディングワイヤ18が、接地電
位にある第２のボンディングワイヤ24により取り囲まれ
る構造が実現されるので、第１のボンディングワイヤ18
からの電界の漏れをシールドして、このICチップの入出
力間の空間結合を有効に抑圧することができるようにな
る。よって、本発明によると、高利得回路に対応可能な
漏話減衰量の確保が可能になる。According to the configuration of the present invention, the transmission line 6a and the signal pad
Thus, a structure in which the first bonding wire 18 connecting to the first bonding wire 18 is surrounded by the second bonding wire 24 at the ground potential is realized.
It is possible to shield the electric field from leaking, thereby effectively suppressing the spatial coupling between the input and output of the IC chip. Therefore, according to the present invention, it is possible to secure a crosstalk attenuation amount that can support a high gain circuit.
ところで、ICチップが例えばSi系のものである場合に
は、ICチップの下面側（サブストレート）が最も低い電
位になるような実装構造を採用する必要があり、マイナ
ス極性の電源を使用する回路形式である場合等のよう
に、ICチップを接地電位である金属体に直接接触させる
ことができないことがある。従って、ICチップを絶縁用
の基板を介して金属体上に固着するようにした構造は、
このような場合に適している。ICチップを絶縁用の基板
を介して金属体上に固着した場合、ICチップにおける接
地はボンディングワイヤを介して行わざるを得ないの
で、本発明の構造はこのような場合に接地を強化する上
でも有効である。By the way, when the IC chip is, for example, an Si-based one, it is necessary to adopt a mounting structure in which the lower surface side (substrate) of the IC chip has the lowest potential, and a circuit using a negative polarity power supply is required. In some cases, for example, the IC chip cannot be brought into direct contact with a metal body that is at the ground potential. Therefore, the structure in which the IC chip is fixed on the metal body via the insulating substrate is as follows:
It is suitable for such a case. If the IC chip is fixed on a metal body via an insulating substrate, the grounding of the IC chip must be performed via bonding wires, so the structure of the present invention enhances the grounding in such a case. But it is effective.
実 施 例 以下本発明の実施例を第２図及び第３図により説明す
る。第１図におけるものと実質的に同一の部分には同一
の符号を付してある。Embodiment An embodiment of the present invention will be described below with reference to FIG. 2 and FIG. Parts substantially the same as those in FIG. 1 are denoted by the same reference numerals.
第２図は本発明の実施例を示す光中継器用の装置の斜
視図である。この装置は、光ファイバを介して伝送され
た高速光信号を電気信号に変換し、これを複数の比較的
低速な信号に時分割して出力するように機能する。FIG. 2 is a perspective view of an apparatus for an optical repeater showing an embodiment of the present invention. This device functions to convert a high-speed optical signal transmitted through an optical fiber into an electric signal, and output the electric signal in a time-division manner into a plurality of relatively low-speed signals.
12はICチップ14が収容される切欠きを有する回路基板
であり、この回路基板12は、第１、第２の導体層2,6が
形成された第１の絶縁体層４とこれよりも僅かに小さい
第２の絶縁体層８とにより第２の導体層６を挟み込むよ
うにして構成されている。第２の絶縁体層８上には第３
の導体層10が形成されている。第１の絶縁体層４の外周
縁部には、外部回路との接続をなすための複数のパッケ
ージリード28が第２の導体層６と接続されるように設け
られている。30,16はそれぞれ回路基板12の上面及び下
面に固着されたCuWからなる第１、第２の金属体であ
る。第１の金属体30はICチップ14が収容される回路基板
12の切欠きに対応する位置に開口を有しており、第２の
金属体16はICチップ14を固定するスペースを有してい
る。第２の金属体16の側面には、溶接が可能なコバール
からなる側板32が接合されている。34はこの装置内に光
ファイバを導入するためのコバールからなるパイプ部材
であり、このパイプ部材34は、例えばレーザ溶接により
側板32の所定位置に固定される。第１の金属体30の各IC
チップ14に対応する位置に形成された開口の縁にはそれ
ぞれ枠部材36が固着されており、この枠部材36にコバー
ルからなる蓋部材38を溶接固定することによって、この
装置は密閉されている。Reference numeral 12 denotes a circuit board having a notch in which an IC chip 14 is accommodated. The circuit board 12 includes a first insulator layer 4 having first and second conductor layers 2 and 6 formed thereon and The second conductor layer 6 is sandwiched between a slightly smaller second insulator layer 8. The third insulating layer 8 has a third
Conductor layer 10 is formed. A plurality of package leads 28 for connecting to an external circuit are provided on the outer peripheral edge of the first insulator layer 4 so as to be connected to the second conductor layer 6. Reference numerals 30 and 16 denote first and second metal members made of CuW fixed to the upper and lower surfaces of the circuit board 12, respectively. The first metal body 30 is a circuit board on which the IC chip 14 is housed.
An opening is provided at a position corresponding to the 12 notch, and the second metal body 16 has a space for fixing the IC chip 14. A side plate 32 made of Kovar that can be welded is joined to a side surface of the second metal body 16. Reference numeral 34 denotes a pipe member made of Kovar for introducing an optical fiber into the apparatus. The pipe member 34 is fixed to a predetermined position of the side plate 32 by, for example, laser welding. Each IC of the first metal body 30
A frame member 36 is fixed to each edge of the opening formed at a position corresponding to the chip 14, and the apparatus is sealed by welding and fixing a lid member 38 made of Kovar to the frame member 36. .
第３図にICチップ14の実装部の近傍の破断斜視図を示
す。第１の絶縁体層４上に形成された第２の導体層６
は、ICチップ14への入力信号を伝送する入力側の伝送ラ
イン6aと、出力信号を伝送する出力側の伝送ライン6a′
と、多数のビア40によって第１の導体層２及び第２の導
体層10に導通する接地パターン6bと、電源供給用等に供
される通電ライン6cとからなる。ICチップ14は、この実
施例では第２の金属体16上に固定された絶縁用の基板26
上に固着されている。絶縁用の基板26は、例えば、窒化
アルミニウムからなる誘電体層と金等からなる導電体層
とを交互に複数層（数層乃至数十層）積層したものであ
る。このような基板26を用いることによって、一様な絶
縁体からなる同等厚みの絶縁用の基板を用いている場合
と比較して、ICチップ14の下面と第２の金属体16との間
のキャパシタンスを増大させることができる。その結
果、高周波は漏話成分は、ICチップ14の入力側から出力
側に到達することなく、高キャパシタンスな基板26を介
して第２の金属体16に逃げるようになり、漏話特性が改
善される。FIG. 3 is a cutaway perspective view of the vicinity of the mounting portion of the IC chip 14. Second conductor layer 6 formed on first insulator layer 4
Is a transmission line 6a on the input side for transmitting an input signal to the IC chip 14, and a transmission line 6a 'on the output side for transmitting an output signal.
And a ground pattern 6b that is electrically connected to the first conductor layer 2 and the second conductor layer 10 by a large number of vias 40, and an energizing line 6c used for power supply and the like. In this embodiment, the IC chip 14 includes an insulating substrate 26 fixed on the second metal body 16.
Fixed on top. The insulating substrate 26 is formed by alternately laminating a plurality of layers (several to several tens of layers) of dielectric layers made of aluminum nitride and conductive layers made of gold or the like. By using such a substrate 26, the distance between the lower surface of the IC chip 14 and the second metal body 16 can be reduced as compared with the case where an insulating substrate of uniform thickness made of a uniform insulator is used. Capacitance can be increased. As a result, the high-frequency crosstalk component escapes to the second metal body 16 via the high-capacitance substrate 26 without reaching the output side from the input side of the IC chip 14, and the crosstalk characteristic is improved. .
ICチップ14上の相対する縁部には、それぞれ伝送ライ
ン6a,6a′に対向するように入出力信号用の信号用パッ
ド20が設けられており、信号用パッド20と伝送ライン6
a,6a′とは第１のボンディングワイヤ18により接続され
ている。信号用パッド20の周囲には、ICチップ14の上面
縁部を除きコの字型の接地用パッド22が設けられてお
り、この接地用パッド22は接地パターン6b及び第３の導
体層10と第２のボンディングワイヤ24により接続されて
いる。この実施例では、第２のボンディングワイヤ24は
一つのパッドに対して５本設けられており、これらの第
２のボンディングワイヤ24により第１のボンディングワ
イヤ18が取り囲まれるようにして、良好なシールド性を
確保している。この実施例では、第１のボンディングワ
イヤ18だけでなく信号用パッド20及び伝送ライン6aも第
２のボンディングワイヤ24により取り囲まれるようにな
っているので、漏話減衰量を著しく大きくすることがで
きる。複数の第２のボンディングワイヤ24を設ける場
合、これらをこの実施例のように概略平行に配置するの
ではなく、互いに交叉するように配置しても良い。On opposite edges of the IC chip 14, signal pads 20 for input / output signals are provided so as to face the transmission lines 6a and 6a ', respectively.
a, 6a 'are connected by a first bonding wire 18. Around the signal pad 20, a U-shaped grounding pad 22 is provided except for the upper surface edge of the IC chip 14, and the grounding pad 22 is connected to the ground pattern 6 b and the third conductor layer 10. They are connected by a second bonding wire 24. In this embodiment, five second bonding wires 24 are provided for one pad, and these second bonding wires 24 surround the first bonding wire 18 so that a good shield is provided. Is secured. In this embodiment, not only the first bonding wire 18 but also the signal pad 20 and the transmission line 6a are surrounded by the second bonding wire 24, so that the amount of crosstalk attenuation can be significantly increased. When a plurality of second bonding wires 24 are provided, they may be arranged so as to cross each other, instead of being arranged substantially in parallel as in this embodiment.
この実施例では、信号用パッド20が入出力ようにそれ
ぞれ一つずつ設けられている場合が示されているが、そ
れぞれ複数の信号用パッドが設けられている場合にも本
発明は適用可能である。In this embodiment, a case is shown in which one signal pad 20 is provided for each input and output, but the present invention is also applicable to a case in which a plurality of signal pads are provided. is there.
この実施例では、第２のボンディングワイヤ24を採用
している他、トリプレート構造の回路基板12を採用し、
伝送ライン6a,6a′の近傍に接地パターン6bを配すると
ともに多数のビア40を介して接地パターン6bを電位安定
性が高い第１及び第２の金属体30,16に導通させている
ので、高利得（例えば60dB 程度）の回路用のICチップ
に十分対処可能な漏話特性を確保することができる。そ
の結果、５〜10Gb/sの超高速なシステムを比較的容易に
実現することができるようになる。In this embodiment, in addition to employing the second bonding wires 24, the circuit board 12 having a triplate structure is employed,
Since the ground pattern 6b is arranged near the transmission lines 6a, 6a 'and the ground pattern 6b is connected to the first and second metal members 30, 16 having high potential stability through a large number of vias 40, Crosstalk characteristics that can sufficiently cope with a high-gain (for example, about 60 dB) circuit IC chip can be secured. As a result, an ultra-high-speed system of 5 to 10 Gb / s can be realized relatively easily.
発明の効果 以上説明したように、本発明のICチップの実装構造に
よれば、実装されたICチップにおける入出力間の漏話の
抑圧が可能になるという効果を奏する。Effect of the Invention As described above, according to the mounting structure of the IC chip of the present invention, it is possible to suppress crosstalk between input and output of the mounted IC chip.
第１図は本発明の原理説明図、 第２図は本発明の実施例を示す光中継器用の装置の斜視
図、 第３図は第２図に示された装置におけるICチップ近傍の
破断斜視図である。 ２……第１の導体層、 ４……第１の絶縁体層、 ６……第２の導体層、 ８……第２の絶縁体層、 10……第３の導体層、 12……回路基板、 14……ICチップ、 16……金属体、 18……第１のボンディングワイヤ、 20……信号用パッド、 22……接地用パッド、 24……第２のボンディングワイヤ、 6a……伝送ライン、 6b……接地パターン。FIG. 1 is a view for explaining the principle of the present invention, FIG. 2 is a perspective view of an apparatus for an optical repeater showing an embodiment of the present invention, and FIG. 3 is a cutaway perspective view near an IC chip in the apparatus shown in FIG. FIG. 2 1st conductor layer 4 4 1st insulator layer 6 2nd conductor layer 8 2nd insulator layer 10 3rd conductor layer 12 ... Circuit board, 14 IC chip, 16 metal body, 18 first bonding wire, 20 signal pad, 22 ground pad, 24 second bonding wire, 6a Transmission line, 6b …… ground pattern.
Claims (2)
（４）、第２の導体層（６）、第２の絶縁体層（８）及
び第３の導体層（10）をこの順に積層してなる回路基板
（12）と、ICチップ（14）とを該ICチップ（14）の上面
と上記第２の導体層（６）とが概略同一平面上に位置す
るように金属体（16）上に固着するようにしたICチップ
の実装構造において、 上記第２の導体層（６）は高速信号用の伝送ライン（6
a）と、該伝送ライン（6a）の近傍に設けられた、上記
第１及び第３の導体層（2,10）に導通する接地パターン
（6b）とを含んでなり、 上記ICチップ（14）の上面には、上記伝送ライン（6a）
が第１のボンディングワイヤ（18）により接続される信
号用パッド（20）と該信号用パッド（20）を囲むように
して設けられた接地用パッド（22）とが形成されてお
り、 該接地用パッド（22）は上記接地パターン（6b）及び第
３の導体層（10）と第２のボンディングワイヤ（24）に
より接続されていることを特徴とするICチップの実装構
造。A first conductor layer (2), a first insulator layer (4), a second conductor layer (6), a second insulator layer (8) and a third conductor layer (10). ) And an IC chip (14) in which the upper surface of the IC chip (14) and the second conductor layer (6) are positioned substantially on the same plane. In the mounting structure of an IC chip fixed to a metal body (16), the second conductor layer (6) is provided with a transmission line (6) for a high-speed signal.
a) and a ground pattern (6b) provided near the transmission line (6a) and connected to the first and third conductor layers (2, 10). ) On the transmission line (6a)
Are formed with a signal pad (20) connected by a first bonding wire (18) and a ground pad (22) provided so as to surround the signal pad (20). (22) A mounting structure of an IC chip, wherein the mounting structure is connected to the ground pattern (6b) and the third conductor layer (10) by a second bonding wire (24).
を介して上記金属体（16）上に固着されていることを特
徴とする請求項１に記載のICチップの実装構造。2. The IC chip (14) is an insulating substrate (26).
The mounting structure of an IC chip according to claim 1, wherein the mounting structure is fixed on the metal body (16) through a hole.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006417A JP2706167B2 (en) | 1990-01-17 | 1990-01-17 | IC chip mounting structure |
| EP19900115235 EP0412528A3 (en) | 1989-08-11 | 1990-08-08 | Electronic circuit package and production thereof |
| US07/564,345 US5150280A (en) | 1989-08-11 | 1990-08-08 | Electronic circuit package |
| CA002023070A CA2023070C (en) | 1989-08-11 | 1990-08-10 | Electronic circuit package and production thereof |
| US07/902,884 US5206986A (en) | 1989-08-11 | 1992-06-23 | Method of producing an electronic circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006417A JP2706167B2 (en) | 1990-01-17 | 1990-01-17 | IC chip mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03211842A JPH03211842A (en) | 1991-09-17 |
| JP2706167B2 true JP2706167B2 (en) | 1998-01-28 |
Family
ID=11637796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006417A Expired - Lifetime JP2706167B2 (en) | 1989-08-11 | 1990-01-17 | IC chip mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2706167B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5416871A (en) * | 1993-04-09 | 1995-05-16 | Sumitomo Electric Industries, Ltd. | Molded optical connector module |
| JP2728052B2 (en) * | 1995-10-18 | 1998-03-18 | 日本電気株式会社 | Semiconductor device |
| US7947908B2 (en) | 2007-10-19 | 2011-05-24 | Advantest Corporation | Electronic device |
-
1990
- 1990-01-17 JP JP2006417A patent/JP2706167B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03211842A (en) | 1991-09-17 |
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