JP2023003740A - Semiconductor device and manufacturing method for the same - Google Patents

Abstract

To provide a semiconductor device that can be easily miniaturized while making it possible to relax the restrictions of the movable area of a wire bond device due to pre-wired wires.SOLUTION: The semiconductor device includes a lead frame and a semiconductor element. The semiconductor element is mounted on the lead frame. The semiconductor element is inclined to a mounting area of the top surface of the lead frame in which the semiconductor element is mounted. A first wire is bonded to a first location on the top surface of the semiconductor element. A second wire is bonded to a second location on the top surface of the semiconductor element. The second location is higher from the mounting area than the first location.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device.

A wire bonding method is disclosed in Patent Document 1.

JP 2012-015242 A

2. Description of the Related Art In a semiconductor device, a plurality of wires may be bonded to a semiconductor element. When there are a plurality of wires to be bonded to a semiconductor element, there is a problem that it is difficult to reduce the size of the semiconductor device because the already-wired wires limit the movable area of the wire bonding device.

The present disclosure is intended to solve such a problem, and an object thereof is to provide a semiconductor device that can alleviate restrictions on the movable area of a wire bonding device due to pre-wired wires and that can be easily miniaturized.

A semiconductor device according to the present disclosure includes a lead frame and a semiconductor element. The semiconductor element is mounted on the lead frame. a first wire bonded to a first point on the top surface of the semiconductor element; a second wire bonded to a second point on the top surface of the semiconductor element; A portion of the semiconductor device is higher than the first portion from the mounting area.

According to the present disclosure, it is possible to provide a semiconductor device that can relax the restrictions on the movable area of a wire bonding device due to pre-wired wires and that can be easily miniaturized.

1 is a cross-sectional view of the semiconductor device of Embodiment 1; FIG. 1 is a diagram extracting and showing a part of the semiconductor device of the first embodiment; FIG. FIG. 4 is a diagram showing an example of a method of applying a bonding material in the method of manufacturing a semiconductor device according to the first embodiment; FIG. 4 is a diagram showing a state after semiconductor elements are arranged in the method of manufacturing a semiconductor device according to the first embodiment; FIG. 10 is a diagram showing movement of capillaries in a wire bond; FIG. 10 is a diagram showing movement of capillaries in a wire bond; FIG. 10 is a diagram showing a method of obliquely arranging a semiconductor element in the method of manufacturing a semiconductor device according to the second embodiment; FIG. 10 is a diagram showing a state after semiconductor elements are arranged in the method of manufacturing a semiconductor device according to the second embodiment; FIG. 13 is a diagram showing a part of the semiconductor device of the third embodiment; FIG. 13 is a diagram showing a part of the semiconductor device of the fourth embodiment; FIG. 15 is a diagram showing a state in the middle of manufacturing the semiconductor device of the fifth embodiment; FIG. 13 is a diagram showing a part of the semiconductor device of the fifth embodiment; 1 is a plan view of a lead frame used in a semiconductor device; FIG. 1 is a side view of a lead frame used in a semiconductor device; FIG. It is a figure which shows the state which mounted the semiconductor element on the lead frame. 4 is a diagram showing a state in which a semiconductor element 13 and lead terminals are connected by wires; FIG. 4 is a diagram showing a state in which a semiconductor element 6 and lead terminals are connected by wires; FIG. 4 is a diagram showing a state in which a semiconductor element 6 and a semiconductor element 13 are connected by wires; FIG. It is a figure which shows the state which joined the lead frame and the insulating substrate. It is a figure which shows the state which resin-sealed a part of lead frame and the semiconductor element. It is a figure which shows the state after removing a part of lead frame part. It is a figure which shows the state after performing a bending process to a lead terminal. It is a bottom view which shows the state after bending to a lead terminal. 4 is a flowchart of a method for manufacturing the semiconductor device of Embodiment 1; 4 is a flow chart showing a method of mounting a semiconductor element on a lead frame in the manufacturing method of the semiconductor device of Embodiment 1; 10 is a flow chart showing a method of mounting a semiconductor element on a lead frame in the method of manufacturing a semiconductor device according to Embodiment 2; 11 is a flow chart showing a method of mounting a semiconductor element on a lead frame in a method of manufacturing a semiconductor device according to a third embodiment; 14 is a flow chart showing a method of mounting a semiconductor element on a lead frame in a method of manufacturing a semiconductor device according to a fourth embodiment; 14 is a flow chart showing a method of mounting a semiconductor element on a lead frame in a method of manufacturing a semiconductor device according to a fifth embodiment; It is a figure which shows the flowchart of a wire-bonding process. It is a figure which shows a part of wire-bonding apparatus. It is a figure which shows the state in the middle of manufacture of the semiconductor device of a comparative example. FIG. 10 is a diagram showing movement of capillaries in a wire bond; FIG. 10 is a diagram showing movement of capillaries in a wire bond; It is a figure which shows the semiconductor device of a comparative example.

In the following description, terms such as "up" and "down" are used to indicate directions. Or it does not limit the direction at the time of use.

<Comparative example>
First, taking the semiconductor device 200 of the comparative example as an example, the wire bonding process in manufacturing the semiconductor device will be described.

FIG. 35 is a diagram showing a semiconductor device 200 of a comparative example. A semiconductor device 200 includes a lead frame 8 , a semiconductor element 6 and a semiconductor element 13 . The lead frame 8 includes lead terminals 80 a , die pads 81 and die pads 82 .

The semiconductor element 6 and the die pad 81 are bonded with the bonding material 7 . The semiconductor element 13 and the die pad 82 are bonded with the bonding material 7 . Semiconductor element 6 and lead terminal 80a are connected by wire 3a. Semiconductor element 6 and semiconductor element 13 are connected by wire 3b.

FIG. 31 is a diagram showing part of the wire bonding apparatus 101. As shown in FIG. As shown in FIG. 31, the wire bonding apparatus 101 includes a US (ultrasonic, ultrasonic) horn 1, a capillary 2 and a spark rod 5. As shown in FIG. A capillary 2 is attached to the tip side of the US horn 1 . The capillary 2 is tubular. A metal wire 3 runs through the tubular capillary 2 . One end of the wire 3 extends from the tip side of the capillary 2 .

FIG. 30 shows a flow chart of the wire bonding process for wire 3a or wire 3b.

First, in step S<b>101 , FAB (Free Air Ball) 4 is formed at the tip of wire 3 extending from the tip of capillary 2 .

When electric discharge is applied to the tip of the metal wire, the wire is partially melted and a metal ball having a diameter of about 0.5 to 3.0 times the diameter of the wire is formed at the tip of the wire. This metal ball is called FAB.

When forming the FAB 4 by the wire bonding apparatus 101, the spark rod 5 is brought close to the wire 3 and electric discharge is generated from the spark rod 5 toward the tip portion of the wire 3, thereby melting the tip portion of the wire 3 and forming the FAB 4. do. This action in forming FAB4 is called the spark action.

Next, in step S102, the FAB 4 is bonded to the electrode of the semiconductor element 6, which is one surface to be bonded. FIG. 32 is a diagram showing part of a semiconductor device 200 in the process of being manufactured. FIG. 32 shows the semiconductor element 6 bonded to the die pad 81 via the bonding material 7 . In step S2, first, the capillary 2 is moved to press the FAB 4 against the semiconductor element 6. As shown in FIG. Then, while the FAB 4 is pressed against the semiconductor element 6 , ultrasonic waves are applied to the FAB 4 by the US horn 1 to bond the FAB 4 to the semiconductor element 6 . A method of forming an FAB at one end of a wire and then bonding the FAB to a surface to be bonded is called ball bonding. In the following description, FAB is also referred to as FAB when it is pressed and crimped onto a surface to be bonded such as a semiconductor element.

Next, in step S103, the wire 3 is shaped. FIG. 33 shows the moving path 11a of the capillary 2 in the wirebonding step S103 of the wire 3a. In the wire bonding of the wire 3a, after bonding the FAB 4 to the semiconductor element 6, the wire 3 which becomes the wire 3a is formed by moving the capillary 2 in the height direction and the in-plane direction, as shown in the path 11a. be. Wire 3a has, for example, a trapezoidal shape. When forming the wire 3 into a trapezoidal shape, the reverse operation 111 and the reverse operation 112, in which the capillary 2 temporarily moves in the direction opposite to the original wiring direction with respect to the in-plane direction, cause the bent portion 3a1 and the bent portion of the wire 3a. 3a2 are formed.

Next, in step S<b>104 , a portion of the wire 3 other than the portion bonded to the semiconductor element 6 is bonded to the other surface to be bonded electrically connected to the semiconductor element 6 . In the wire bonding of the wire 3a, a portion of the wire 3 other than the portion bonded to the semiconductor element 6 is bonded to the lead terminal 80a. The wire 3 and the lead terminal 80a are bonded by pressing the wire 3 against the surface to be bonded of the lead terminal 80a and applying ultrasonic waves. By joining the wire 3 and the lead terminal 80a, as shown in FIG. 33, the semiconductor element 6 and the lead terminal 80a are connected by the wire 3a.

The above is the outline of the wire bonding process. Although the wire bonding of the wire 3a is used as a specific example in the above description, the wire bonding process of the wire 3b is the same as the wire bonding process of the wire 3a except that the surfaces to be bonded are different. In the wire bonding of the wire 3b, a portion of the wire 3 other than the portion bonded to the semiconductor element 6 is bonded to the semiconductor element 13 in step S104. The semiconductor element 13 is, for example, a power semiconductor element.

Generally, in a semiconductor device, there are a plurality of wires that are wired through the wire bonding process as described above. As shown in FIG. 35, in the semiconductor device 200, a plurality of wires are bonded to the upper surface of the semiconductor element 6 via FAB4.

FIG. 34 shows the path 11b along which the capillary 2 moves when performing wiring with the wire 3b. If the space 12 between the already-wired wire 3a and the path 11b is not sufficiently wide when performing the wiring with the wire 3b after performing the wiring with the wire 3a, the wire 3a and the capillary 2 come into contact with each other, and the wire 3a is deformed. There is a risk of Since the deformed wire 3a may come close to or come into contact with surrounding components, the deformation of the wire 3a may make it difficult to obtain desired characteristics of the semiconductor device. If an attempt is made to avoid contact between the wire 3a and the capillary 2, the movable area of the capillary 2 is restricted.

As described above, in the semiconductor device 200 of the comparative example, the movable area of the wire bonding device 101 is restricted by the wired wires 3a.

In each embodiment described later, the semiconductor element 6 is mounted in an inclined state with respect to the lead frame 8 . This alleviates the restriction of the space in which the wire bonding apparatus 101 operates by the wire 3a when wiring the wire 3b to be wired later.

By relaxing restrictions on the movable region of the wire bonding apparatus 101, for example, it is possible to narrow the distance between a plurality of wires bonded to a semiconductor element. This allows, for example, the reduction of semiconductor devices. For example, the cost can be improved by downsizing an IC chip as a semiconductor element. In this way, the restrictions on the movable area of the wire bonding device 101 due to the already-wired wires are relaxed, so that, for example, it is possible to improve the profit rate by improving the cost or reduce the size of the semiconductor device.

<A. Embodiment 1>
<A-1. Configuration>
FIG. 1 is a cross-sectional view of a semiconductor device 40 of Embodiment 1. FIG. FIG. 2 is a diagram showing a part of the semiconductor device 40 extracted.

FIG. 22 is a top view of the semiconductor device 40. FIG. FIG. 23 is a bottom view of the semiconductor device 40. FIG.

As shown in FIG. 1, the semiconductor device 40 includes a semiconductor element 6, a semiconductor element 13a, a semiconductor element 13b, a radiator plate 22, an insulating substrate 23, and a lead frame 8. When the semiconductor elements 13a and 13b are not distinguished from each other, the semiconductor elements 13a and 13b are referred to as semiconductor elements 13, respectively.

As shown in FIGS. 1, 22 and 23, the lead frame 8 includes lead terminals 80a, 80b and 80c, a die pad 81 and a die pad .

The lead frame 8 has electrical conductivity. Through the lead frame 8, the semiconductor elements 6, 13a, and 13b can be energized from the outside of the semiconductor device 40. FIG.

Lead terminals 80 a , 80 b , and 80 c each have a portion sealed with resin 21 and a portion exposed from resin 21 so as to be electrically connectable to the outside of semiconductor device 40 . Resin 21 is an insulator. The lead terminal 80b is integrated with the die pad 82. As shown in FIG.

The semiconductor element 6 is bonded onto the upper surface of the die pad 81 via the bonding material 7 .

The semiconductor element 6 is inclined with respect to a mounting area 810 which is an area on which the semiconductor element 6 is mounted on the upper surface of the die pad 81 .

The semiconductor element 6 is, for example, a small semiconductor element. The planar shape of the semiconductor element 6 is, for example, a shape with a width of 3.5 mm or less in at least one direction. The planar shape of the semiconductor element 6 is, for example, a rectangle, and the length of the short side of the rectangle is, for example, 3.5 mm or less. The planar shape of the semiconductor element 6 is, for example, a shape contained in a rectangle having short sides of 3.5 mm and long sides of 7 mm. The planar shape of the semiconductor element 6 is, for example, a rectangle, the length of the short side of the rectangle is 3.5 mm or less, and the length of the long side of the rectangle is 7 mm or less. Moreover, the thickness of the semiconductor element 6 is, for example, 0.5 mm or less. The planar shape of the semiconductor element 6 is the shape when the semiconductor element 6 is viewed in plan, and is different from the shape when the mounting region 810 is viewed in plan.

As shown in FIG. 1, a wire 3a and a wire 3b are joined to the upper surface of the semiconductor element 6. As shown in FIG. That is, at least two wires are bonded to the upper surface of the semiconductor element 6 . The number of wires bonded to the upper surface of the semiconductor element 6 may be two or may be three or more.

On the upper surface of the semiconductor element 6, the distance between a portion 6a (an example of a first portion) to which the wire 3a is bonded and a portion 6b (an example of a second portion) to which the wire 3b is bonded is 500 μm or less, for example.

The wire 3a extends from the point 6a toward the opposite side to the point 6b with respect to the in-plane direction.

The wire 3b extends from the point 6b toward the side opposite to the point 6a with respect to the in-plane direction.

The wires 3a and 3b are each, for example, gold, silver, copper or aluminum wire. Wire diameters of the wires 3a and 3b are, for example, 10 μm or more and 75 μm or less.

The wires 3a and 3b are respectively bonded to the upper surface of the semiconductor element 6 by ball bonding.

The semiconductor element 6 is, for example, a horizontal semiconductor element. A semiconductor element having a horizontal structure is a semiconductor element having a structure in which current flows in the in-plane direction. Unlike a vertical semiconductor device, such as an IGBT, which preferably has a relatively large area in a plan view to reduce conduction loss, a horizontal semiconductor device has a reduced area in a plan view. is preferred. A vertical structure semiconductor element is a semiconductor element having a structure in which a current flows between both main surfaces.

The semiconductor element 6 is, for example, an IC (Integrated Circuit) element that controls the semiconductor element 13a.

A semiconductor element with a horizontal structure, like the semiconductor element 6, needs to have at least two wire bonds on one main surface that are not connected to each other by stitches. Here, a stitch refers to a joining point in the middle of a wire when the wire is joined to the surfaces to be joined not only at both ends but also at the middle.

The semiconductor element 13a and the semiconductor element 13b are each bonded onto the die pad 82 with the bonding material 7 interposed therebetween.

The semiconductor elements 13a and 13b are, for example, power semiconductors. The semiconductor element 13a is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor element 13b is, for example, a diode.

The upper surface of semiconductor element 6 and lead terminal 80a are electrically connected by wire 3a. The upper surface of semiconductor element 13a and the upper surface of semiconductor element 6 are electrically connected by wire 3b. The upper surface of semiconductor element 13a and the upper surface of semiconductor element 13b are electrically connected by wire 3c. The upper surface of semiconductor element 13b and lead terminal 80c are electrically connected by wire 3c. Wires 3c are, for example, gold, silver, copper, or aluminum wires.

Semiconductor element 13a is controlled by a signal input from semiconductor element 6 via wire 3b.

The semiconductor device 40 may include an RC-IGBT (Reverse-Conducting IGBT) instead of the semiconductor elements 13a and 13b. In that case, semiconductor element 6 and RC-IGBT are connected by wire 3b.

The semiconductor element 6 is inclined with respect to a mounting area 810 which is an area on which the semiconductor element 6 is mounted on the upper surface of the die pad 81 . The semiconductor element 6 is inclined with respect to the mounting area 810 so that the portion 6b to which the wire 3b is bonded is higher than the portion 6a to which the wire 3a is bonded. The semiconductor element 6 is inclined, for example, from 8 degrees to 14 degrees with respect to the mounting region 810 . That is, the angle α shown in FIG. 5 is, for example, 8 degrees or more and 14 degrees or less. A dashed line 811 in FIG. 5 is a line parallel to the mounting area 810 .

The inclination of the semiconductor element 6 with respect to the mounting area 810 is such that the semiconductor element 6 is lower from the mounting area 810 on the side closer to the lead terminals 80a than on the side farther from the lead terminals 80a.

The heat sink 22 is made of metal. The radiator plate 22 is exposed from the resin 21 below the semiconductor device 40 .

An insulating substrate 23 is bonded onto the heat sink 22 . The insulating substrate 23 is an insulator. The radiator plate 22 and the insulating substrate 23 are bonded together by, for example, a bonding material (not shown).

A die pad 82 is bonded onto the insulating substrate 23 . The insulating substrate 23 and the die pad 82 are bonded by, for example, a bonding material (not shown).

<A-2. Method for manufacturing a semiconductor device>
FIG. 24 is a flow chart showing the manufacturing method of the semiconductor device 40. As shown in FIG.

First, in step S1, the lead frame 8, the semiconductor element 6, the semiconductor element 13a, and the semiconductor element 13b are prepared. FIG. 13 is a plan view showing the entire lead frame 8 used in the semiconductor device 40. As shown in FIG. The lead frame 8 has a frame 800 as shown in FIG. 13 when it is prepared in step S1. Lead terminals 80 a , 80 b , and 80 c , die pad 81 and die pad 82 are integrated by frame 800 at the stage of preparation in step S 1 of lead frame 8 . FIG. 14 is a side view of the lead frame 8 prepared in step S1. As shown in FIG. 14, the die pad 82 is different in height from other portions of the lead frame 8 .

Next, in step S2, semiconductor element 6, semiconductor element 13a, and semiconductor element 13b are mounted on lead frame 8. As shown in FIG. Step S2 will be detailed later. The state after step S2 is finished is shown in FIG.

Next, in step S3, wire bonding is performed to connect the semiconductor elements 13a and 13b to the lead terminals 80c by the wires 3c. The state after step S3 is finished is shown in FIG.

Next, in step S4, wire bonding is performed to connect the semiconductor element 6 and the lead terminals 80a with the wires 3a. In step S4, for example, one end of the wire is bonded to the top surface of the semiconductor element 6 by ball bonding, and then the other end of the wire is bonded to the top surface of the lead terminal 80a. The state after step S4 is finished is shown in FIG.

Next, in step S5, wire bonding is performed to connect the semiconductor element 6 and the semiconductor element 13a with the wire 3b. The state after step S5 is finished is shown in FIG. In step S5, for example, one end of the wire is bonded to the upper surface of the semiconductor element 6b by ball bonding, and then the other end of the wire is bonded to the upper surface of the semiconductor element 13a. The state after step S5 is finished is shown in FIG. In step S<b>5 , the inclination of capillary 2 with respect to mounting region 810 is smaller than the inclination of capillary 2 with respect to the upper surface of semiconductor element 6 . The capillary 2 is not tilted with respect to the mounting area 810, for example.

Next, in step S6, the die pad 82 and the insulating substrate 23 are bonded. The die pad 82 and the insulating substrate 23 are bonded by, for example, a bonding material (not shown). The state after step S6 is completed is shown in FIG.

Next, in step S7, the insulating substrate 23 and the radiator plate 22 are joined. The insulating substrate 23 and the heat dissipation plate 22 are bonded by, for example, a bonding material (not shown).

Next, in step S<b>8 , the semiconductor element 6 , the semiconductor element 13 and part of the lead frame 8 are sealed with the resin 21 . The state after step S8 is finished is shown in FIG.

Next, in step S9, the portion of the lead frame 8 exposed from the resin 21 is plated.

Next, in step S10, a part of the lead frame 8 is removed by punching with a die. At step S10, the frame 800 of the lead frame 8 is removed. The state after step S10 is finished is shown in FIG.

Next, in step S11, the lead terminal 80a, the lead terminal 80b, and the lead terminal 80c are bent. The bending process is performed using, for example, a mold. Thereby, as shown in FIGS. 1, 22 and 23, the portions of lead terminals 80a, 80b and 80c that are not sealed with resin 21 are bent.

Next, in step S12, a function test is performed to confirm whether the semiconductor device 40 functions normally.

Through the above steps, the semiconductor device 40 is completed.

Wire bonding in steps S4 and S5 is performed in the same manner as the method described using the flowchart of FIG. 30 for the semiconductor device 200 in <Comparative Example>. However, the semiconductor device 40 differs from the semiconductor device 200 of the comparative example in that the semiconductor element 6 is inclined with respect to the mounting region 810 .

FIG. 25 is a flow chart showing a method of mounting semiconductor element 6, semiconductor element 13a, and semiconductor element 13b on lead frame 8 in step S2.

First, in step S211, the bonding material 7 for the semiconductor element 6 is arranged on the die pad 81 (see FIG. 3). The bonding material 7 is silver paste, for example. The bonding material 7 is arranged on the die pad 81 by being applied on the die pad 81, for example. The bonding material 7 is arranged on the die pad 81 so as to have different thickness depending on the position in the mounting area 810 according to the inclination of the semiconductor element 6 in the semiconductor device 40 . The difference in the thickness of the bonding material 7 depending on the position in the mounting region 810 is adjusted so that the inclination of the semiconductor element 6 in the semiconductor device 40 with respect to the mounting region 810 is preferable.

Next, in step S212, the bonding material 7 for the semiconductor element 13 is arranged on the die pad 82. As shown in FIG. The bonding material 7 for the semiconductor element 13 is silver paste, for example. The bonding material 7 for the semiconductor element 13 and the bonding material 7 for the semiconductor element 6 are, for example, the same silver paste. The bonding material 7 is arranged on the die pad 82 by being applied on the die pad 82, for example.

Next, in step S213, the pick-up collet 15 is used to place the semiconductor element 6 on the bonding material 7 applied on the die pad 81, as shown in FIG. At this time, for example, the pickup collet 15 carries the semiconductor element 6 parallel to the mounting area 810 and places the semiconductor element 6 on the bonding material 7 applied on the die pad 81 . FIG. 4 shows the state after the semiconductor element 6 is arranged in step S213. Due to the dead weight of the semiconductor element 6 and the load of the pick-up collet 15, the bonding material 7 under the semiconductor element 6 is deformed from the shape when arranged in step S212, and adheres tightly to the semiconductor element 6 and the die pad 81 as shown in FIG. do. In step S212, the bonding material 7 is arranged so that the thickness of the bonding material 7 differs depending on the position in the mounting area 810, so that the semiconductor element 6 after S213 is in an inclined state with respect to the mounting area 810. .

Next, in step S214, the pick-up collet 15 is used to arrange the semiconductor element 13 on the bonding material 7 applied on the die pad 82. As shown in FIG.

Next, in step S215, the bonding material 7 is cured by heating. As a result, the die pad 81 and the semiconductor element 6 and the die pad 82 and the semiconductor element 13 are bonded. When heating the bonding material 7, for example, a clean oven (not shown) is used.

As described above, in the manufacturing method of the semiconductor device of the present embodiment, the lead frame 8 and the semiconductor element 6 are prepared, and the semiconductor element 6 is inclined with respect to the mounting region 810 of the lead frame 8. After bonding the semiconductor element 6 onto the mounting region 810 of the lead frame 8 and bonding the wire 3a to the point 6a on the upper surface of the semiconductor element 6, the wire 3b is bonded to the point 6b on the upper surface of the semiconductor element 6. FIG. After the wire 3b is joined to the portion 6b by using the capillary 2 at one end of the wire 3b, the capillary 2 is moved toward the portion 6a from the portion 6b in the in-plane direction. A portion of the wire 3b other than the one end joined to the portion 6b is attached to the portion opposite to the portion 6a (that is, the upper surface of the semiconductor element 13a) with respect to the in-plane direction using the capillary 2. Join. The portion of the wire 3b other than the one end joined to the point 6b is, for example, the end of the wire 3b opposite to the one end joined to the point 6b.

As described above, in the semiconductor device 40, the semiconductor element 6 is inclined with respect to the mounting area 810, which is the area of the upper surface of the lead frame 8 where the semiconductor element 6 is mounted. The inclination of the semiconductor element 6 with respect to the mounting region 810 is, for example, 8 degrees or more and 14 degrees or less. The larger the inclination of the semiconductor element 6 with respect to the mounting area 810, the greater the effect of alleviating the limitation of the movable area of the wire bonding apparatus 101 by the wires 3a in step S5. If the inclination of the capillary 2 with respect to the semiconductor element 6 is too large in step S4 or step S5, the quality of wire bonding to the upper surface of the semiconductor element 6 will be degraded. Since the inclination of the semiconductor element 6 with respect to the mounting region 810 is 14 degrees or less, deterioration in the bonding quality of the wire to the upper surface of the semiconductor element 6 can be suppressed.

In steps S4 and S5, the wires 3a and 3b are shaped to have trapezoidal shapes, respectively, as shown in FIG. 2, for example. The trapezoidal shape of the wire provides the following two effects.

First, it becomes easy to secure the distance between the side surfaces of the semiconductor element 6 and the semiconductor element 13 and the wire, and to secure a margin for insulation. Since the wire has a trapezoidal shape, the height of the intermediate portion of the wire that connects two points can be suppressed, and the distance between the side surfaces of the semiconductor element 6 and the semiconductor element 13 and the wire can be secured. Thereby, the quality of the semiconductor device 40 can be improved without enlarging the outer shape of the semiconductor device 40 .

Second, it facilitates visual inspection in the manufacturing process. In the appearance inspection performed in the manufacturing process, the inspection is performed in an enlarged field of view using, for example, a stereomicroscope. In such examinations, the trapezoidal shaped wire is easier to focus. In addition, by using the bent point of the trapezoidal shape as a reference, it becomes easy to inspect the positional relationship and the shape of the main parts constituting the semiconductor device 40 .

In order to form a trapezoidal wire, a reverse operation is required to temporarily move the bond head, especially the capillary 2, in the opposite direction to the original wiring direction. It is important to avoid contact between the wired wires and the capillary 2 during this reverse operation in order to obtain desired characteristics of the semiconductor device such as insulation performance and withstand voltage performance.

In the semiconductor device 200 of the comparative example as well, contact between the wires and the capillaries 2 can be suppressed by laying out the electrodes of the semiconductor elements so that the capillaries 2 do not come into contact with the wired wires even in reverse operation. In this case, it becomes difficult to reduce the size of the semiconductor device. In order to reduce the price by increasing the number of semiconductor elements such as IC chips that can be obtained from one wafer, it is necessary to reduce the size of the semiconductor elements themselves such as IC chips.

In the semiconductor device 40, as shown in FIG. 1, the semiconductor element 6 is inclined with respect to a mounting area 810, which is an area of the top surface of the die pad 81 where the semiconductor element 6 is mounted. In the semiconductor device 40, the wires 3a bonded to the lower side of the upper surface of the semiconductor element 6 are wired first, and the wires 3b bonded to the higher side are wired later. restrictions are relaxed. Moreover, even when the semiconductor element 6 is reduced in size, contact between the wire 3a and the capillary 2 can be suppressed.

FIG. 5 is a diagram showing movement of the capillary 2 in wire bonding at step S5. In the semiconductor device 40, the semiconductor element 6 is mounted such that the portion 6a on the upper surface of the semiconductor element 6 where the wires 3a are bonded is lower than the portion 6b where the wires 3b on the upper surface of the semiconductor element 6 are bonded from the mounting area 810. By being inclined with respect to the region 810, compared with the case of the semiconductor device 200, the path 11b along which the tip of the capillary 2 moves when wiring the wire 3b moves vertically upward relative to the wire 3a. As a result, assuming that the capillary 2 moves in the same manner, the distance 12 between the path 11b in which the tip of the capillary 2 moves and the wired wire 3a when manufacturing the semiconductor device 40 is the same as that of the capillary when manufacturing the semiconductor device 200. 2 is wider than the distance 120 (see FIG. 34) between the path 11b along which the tip of the wire 3 moves and the wire 3a already wired.

As described above, in the semiconductor device 40, restrictions on the movable area of the wire bonding device 101 due to the wired wires 3a are relaxed. By relaxing the restrictions on the movable area of the wire bonding apparatus 101 by the wires 3a, it is possible to make the portion 6a to which the wire 3a is bonded and the portion 6b to which the wire 3b are bonded on the upper surface of the semiconductor element 6 closer to each other. , the semiconductor element 6 can be reduced.

For example, the semiconductor device 6 can be scaled down to wirebond wires 3b in the situation shown in FIG. In the situation shown in FIG. 6, after the wire 3b is bonded to the upper surface of the semiconductor element 6, when the capillary 2 moves in the in-plane direction toward the point 6a rather than the point 6b due to the reverse operation, the in-plane direction The difference 12b in height between the capillary 2 and the wire 3a from the mounting region 810 at the same position with respect to Become. In such a case, since the semiconductor element 6 is inclined with respect to the mounting area 810, contact between the capillary 2 and the wire 3a is avoided. The difference 12b in height from the mounting region 810 between the capillary 2 and the wire 3a at the same position in the in-plane direction corresponds to the difference in height between the tip of the capillary 2 and the wire 3a at the same position in the in-plane direction. It is not limited, and may be the height difference between the side surface of the capillary 2 and the wire 3a at the same position in the in-plane direction. The same applies to the contact between the wire 3b and the wire 3a that are connected in step S5. That is, when wiring the wire 3b, the height difference from the mounting region 810 between the wire 3b and the wire 3a at the same position in the in-plane direction is the mounting region between the portion 6a and the portion 6b on the upper surface of the semiconductor element 6. When the height difference h from 810 is smaller than the height difference h, the semiconductor element 6 is inclined with respect to the mounting area 810, thereby avoiding contact between the wires 3b and 3a. . A dashed line 812 in FIG. 6 is a line parallel to the mounting area 810 .

<A-3. Variation>
The shape of the wire 3a and the wire 3b is not limited to a trapezoidal shape, and may be, for example, a triangular shape. A reverse operation is also performed when forming the wire into a triangular shape. Since the semiconductor element 6 is inclined with respect to the mounting area 810, restrictions on the movable area of the wire bonding apparatus 101 by the wired wires 3a are relaxed. For example, contact between the wire 3a and the capillary 2 is suppressed during the reverse operation.

When the wire 3a is wire-bonded after the wire 3b is wire-bonded, the semiconductor element 6 is attached to the mounting region 810 so that the portion 6a to which the wire 3a is bonded is larger than the portion 6b to which the wire 3b is bonded. With a configuration that is inclined so as to be higher, restrictions on the movable area of the wire bonding apparatus 101 by the wires 3b during wiring of the wires 3a are alleviated.

<B. Embodiment 2>
Here, a method for manufacturing the semiconductor device 40, which is different from the first embodiment, will be described. The semiconductor device manufacturing method of the present embodiment differs from the semiconductor device manufacturing method of the first embodiment in details of step S2. The method for manufacturing the semiconductor device of this embodiment is the same as the method for manufacturing the semiconductor device of the first embodiment in other respects. Below, description is abbreviate|omitted except step S2.

FIG. 26 is a flow chart showing details of step S2 in the method of manufacturing a semiconductor device according to this embodiment.

First, in step S<b>221 , the bonding material 7 for the semiconductor element 6 is placed on the die pad 81 . The bonding material 7 is arranged on the die pad 81 by being applied on the die pad 81, for example. The thickness of the bonding material 7 placed on the die pad 81 is constant, for example, regardless of the in-plane position.

Next, in step S222, the bonding material 7 for the semiconductor element 13 is arranged on the die pad 82. As shown in FIG. The bonding material 7 is arranged on the die pad 82 by being applied on the die pad 82, for example.

Next, in step S223, the pick-up collet 15 is used to arrange the semiconductor element 6 on the bonding material 7 applied on the die pad 81. As shown in FIG. In step S223, as shown in FIG. 7, by tilting the pick-up collet 15, the semiconductor chip 6 is transported in a state in which the semiconductor chip 6 is tilted with respect to the mounting area 810. FIG. The semiconductor element 6 is pressed against the bonding material 7 placed on the die pad 81 while the semiconductor element 6 is tilted with respect to the mounting area 810 . Thereby, as shown in FIG. 8 , the semiconductor element 6 is arranged on the bonding material 7 while being inclined with respect to the mounting area 810 . Also, by pressing the semiconductor element 6 against the bonding material 7 , the bonding material 7 adheres to the mounting region 810 and the semiconductor element 6 inclined with respect to the mounting region 810 .

Next, in step S224, the pickup collet 15 is used to arrange the semiconductor element 13a and the semiconductor element 13b on the bonding material 7 applied on the die pad 82 respectively.

Next, in step S225, the bonding material 7 is cured by heating. As a result, the die pad 81 and the semiconductor element 6 are bonded together, and the die pad 82 and the semiconductor element 13 are bonded together.

Through the above steps, the semiconductor element 6 is mounted on the die pad 81 while being inclined with respect to the mounting area 810 .

Also in this embodiment, since the semiconductor element 6 is inclined with respect to the mounting region 810, the same effect as that described in the first embodiment can be obtained in step S5. For example, the semiconductor element 6 is inclined with respect to the mounting region 810 so that the portion 6b to which the wire 3b is bonded is higher than the portion 6a to which the wire 3a is bonded. Restrictions on the movable area of the wire bonding device by the wires 3a are eased, and the size reduction of the semiconductor device 40 is facilitated.

<C. Embodiment 3>
FIG. 9 is a diagram showing the vicinity of the portion where the die pad 81 and the semiconductor element 6 are bonded in the semiconductor device (hereinafter referred to as a semiconductor device 40c) according to the third embodiment. The semiconductor device 40c is the same as the semiconductor device 40 except that the mounting region 810 has the grooves 16 and the protrusions 17 . For example, in the semiconductor device 40c, the semiconductor element 6 is inclined with respect to the mounting region 810 so that the portion 6b to which the wire 3b is bonded is higher than the portion 6a to which the wire 3a is bonded. there is

In the semiconductor device 40c, a groove 16 is provided on the upper surface of the lead frame 8. As shown in FIG.

The lead frame 8 has protrusions 17 on the edges of the grooves 16 . The protrusion 17 is formed by excluding a portion of the lead frame 8 from the portion of the groove 16 when forming the groove 16 in the lead frame 8. A plurality of grooves 16 may be provided. The number of grooves 16 is adjusted, for example, so that the tilt angle of the semiconductor element 6 in the semiconductor device 40c is preferable. The projection 17 is located on the higher side of the mounting region 810 than the semiconductor element 6 is.

The semiconductor device manufacturing method of the present embodiment differs from the semiconductor device manufacturing method of the first embodiment in details of step S2. The method for manufacturing the semiconductor device of this embodiment is the same as the method for manufacturing the semiconductor device of the first embodiment in other respects.

FIG. 27 is a flow chart showing the details of step S2 in the method of manufacturing a semiconductor device according to this embodiment.

In this embodiment, step S2 includes steps S231 to S236.

At step S231, a groove 16 is formed on the die pad 81 of the lead frame 8. As shown in FIG. A portion of the lead frame 8 excluded from the groove portion by the processing for forming the groove 16 becomes the protrusion 17 on the upper surface of the die pad 81 .

Next, in step S232, the bonding material 7 for the semiconductor element 6 is arranged on the die pad 81. As shown in FIG. The bonding material 7 is arranged on a region including a portion of the upper surface of the die pad 81 where the projections 17 are formed. The bonding material 7 is arranged on the die pad 81 by being applied on the die pad 81, for example.

Next, in step S233, the bonding material 7 for the semiconductor element 13 is arranged on the die pad 82. As shown in FIG. The bonding material 7 is arranged on the die pad 82 by being applied on the die pad 82, for example.

Next, in step S234, the pick-up collet 15 is used to arrange the semiconductor element 6 on the bonding material 7 applied on the die pad 81. As shown in FIG. The semiconductor element 6 is arranged at a position overlapping the protrusion 17 in plan view. The semiconductor element 6 is supported by the projections 17 via the bonding material 7 , so that the semiconductor element 6 is arranged on the bonding material 7 in an inclined state with respect to the mounting area 810 .

Next, in step S235, the pick-up collet 15 is used to place the semiconductor element 13 on the bonding material 7 applied on the die pad 82. As shown in FIG.

Next, in step S236, the bonding material 7 is cured by heating. As a result, the die pad 81 and the semiconductor element 6 and the die pad 82 and the semiconductor element 13 are bonded.

Through the above steps, the semiconductor element 6 is mounted on the die pad 81 while being inclined with respect to the mounting area 810 .

Also in this embodiment, since the semiconductor element 6 is inclined with respect to the mounting region 810, the same effect as that described in the first embodiment can be obtained in step S5. For example, the semiconductor element 6 is inclined with respect to the mounting region 810 so that the portion 6b to which the wire 3b is bonded is higher than the portion 6a to which the wire 3a is bonded. Restrictions on the movable area of the wire bonding device by the wires 3a are eased, facilitating miniaturization of the semiconductor device 40c.

<D. Embodiment 4>
FIG. 10 is a diagram showing the vicinity of the portion where the die pad 81 and the semiconductor element 6 are bonded in the semiconductor device (hereinafter referred to as a semiconductor device 40d) of the fourth embodiment. The semiconductor device 40 d has a protrusion 19 in the mounting area 810 of the die pad 81 and a depression 18 on the back side of the mounting area 810 . Semiconductor device 40d is similar to semiconductor device 40 in other respects. For example, in the semiconductor device 40d, the semiconductor element 6 is inclined with respect to the mounting region 810 so that the portion 6b to which the wire 3b is bonded is higher than the portion 6a to which the wire 3a is bonded. there is

A protrusion 19 is provided on the top surface of the lead frame 8 in the semiconductor device 40d. In the semiconductor device 40 d , a recess 18 is provided on the lower surface of the lead frame 8 at a position facing the protrusion 19 . The projection 19 is located on the higher side of the mounting region 810 than the semiconductor element 6 is.

The semiconductor device manufacturing method of the present embodiment differs from the semiconductor device manufacturing method of the first embodiment in details of step S2. The method for manufacturing the semiconductor device of this embodiment is the same as the method for manufacturing the semiconductor device of the first embodiment in other respects.

FIG. 28 is a flow chart showing the details of step S2 in the method of manufacturing a semiconductor device according to this embodiment.

In this embodiment, step S2 includes steps S241 to S246.

In step S241, the lower surface of the lead frame 8 is pressed to form the depression 18. As shown in FIG. A portion of the lead frame 8 extruded by the press working becomes the protrusion 19 on the upper surface of the die pad 81 .

Next, in step S242, the bonding material 7 for the semiconductor element 6 is arranged on the die pad 81. As shown in FIG. The bonding material 7 is arranged on a region including a portion of the upper surface of the die pad 81 where the projections 19 are formed. The bonding material 7 is arranged on the die pad 81 by being applied on the die pad 81, for example.

Next, in step S243, the bonding material 7 for the semiconductor element 13 is arranged on the die pad 82. As shown in FIG. The bonding material 7 is arranged on the die pad 82 by being applied on the die pad 82, for example.

Next, in step S244, the pick-up collet 15 is used to place the semiconductor element 6 on the bonding material 7 applied on the die pad 81. As shown in FIG. The semiconductor element 6 is arranged at a position overlapping the protrusion 19 in plan view. The semiconductor element 6 is supported by the protrusions 19 via the bonding material 7 , so that the semiconductor element 6 is arranged on the bonding material 7 in an inclined state with respect to the mounting area 810 .

Next, in step S245, the pick-up collet 15 is used to arrange the semiconductor element 13 on the bonding material 7 applied on the die pad 82. As shown in FIG.

Next, in step S246, the bonding material 7 is cured by heating. As a result, the die pad 81 and the semiconductor element 6 and the die pad 82 and the semiconductor element 13 are bonded.

Through the above steps, the semiconductor element 6 is mounted on the die pad 81 while being inclined with respect to the mounting area 810 .

Also in this embodiment, since the semiconductor element 6 is inclined with respect to the mounting region 810, the same effect as that described in the first embodiment can be obtained in step S5. For example, the semiconductor element 6 is inclined with respect to the mounting region 810 so that the portion 6b to which the wire 3b is bonded is higher than the portion 6a to which the wire 3a is bonded. Restrictions on the movable area of the wire bonding device by the wires 3a are eased, facilitating miniaturization of the semiconductor device 40d.

<E. Embodiment 5>
FIG. 12 is a diagram showing the vicinity of the portion where the die pad 81 and the semiconductor element 6 are bonded in the semiconductor device (hereinafter referred to as a semiconductor device 40e) of the fifth embodiment.

In the semiconductor device 40e, the groove 20 is provided on the top surface of the lead frame 8 near the mounting region 810 where the semiconductor element 6 is mounted. Also, part of the bonding material 7 that bonds the die pad 81 and the semiconductor element 6 is contained in the groove 20 . Semiconductor device 40e is similar to semiconductor device 40 in other respects. For example, in the semiconductor device 40e, the semiconductor element 6 is inclined with respect to the mounting region 810 such that the portion 6b to which the wire 3b is bonded is higher than the portion 6a to which the wire 3a is bonded. there is

The groove 20 is located on the side of the semiconductor element 6 that extends from the higher side to the lower side of the semiconductor element 6 in the in-plane direction. A portion of the groove 20 may overlap the semiconductor element 6 in plan view. The groove 20 extends, for example, along a side of the semiconductor element 6 on which the semiconductor element 6 is lowered.

The semiconductor device manufacturing method of the present embodiment differs from the semiconductor device manufacturing method of the first embodiment in details of step S2. The method for manufacturing the semiconductor device of this embodiment is the same as the method for manufacturing the semiconductor device of the first embodiment in other respects. Only step S2 will be described below.

FIG. 29 is a flow chart showing the details of step S2 in the method of manufacturing a semiconductor device according to this embodiment.

In this embodiment, step S2 includes steps S251 to S256.

In step S251, a groove 20 is formed on the upper surface of the die pad 81 near the mounting region 810 for the semiconductor element 6. As shown in FIG.

Step S252 is the same as step S221 of the second embodiment. The state after performing step S252 is shown in FIG.

Step S253 is the same as step S222 of the second embodiment.

Step S254 is the same as step S223 of the second embodiment.

Step S255 is the same as step S224 in the second embodiment.

Step S256 is the same as step S225 of the second embodiment.

That is, in step S2 of the present embodiment, step S251 is performed, and then step S2 of the second embodiment is performed. As a result, the semiconductor element 6 is inclined with respect to the mounting region 810 so that the portion 6a on the upper surface of the semiconductor element 6 where the wires 3a are bonded is lower than the portion 6b where the wires 3b are bonded on the upper surface of the semiconductor element 6. mounted on the die pad 81 in this state.

After step S251, step S2 of the first, third, or fourth embodiment may be performed instead of performing step S2 of the second embodiment. For example, the semiconductor element 6 is inclined with respect to the mounting region 810 so that the portion 6b to which the wire 3b is bonded is higher than the portion 6a to which the wire 3a is bonded. Restrictions on the movable area of the wire bonding device by the wires 3a are eased, and the size reduction of the semiconductor device 40 is facilitated.

Also in this embodiment, since the semiconductor element 6 is inclined with respect to the mounting region 810, the same effect as that described in the first embodiment can be obtained in step S5. For example, the semiconductor element 6 is inclined with respect to the mounting region 810 so that the portion 6b to which the wire 3b is bonded is higher than the portion 6a to which the wire 3a is bonded. Restrictions on the movable area of the wire bonding device by the wires 3a are eased, and the size reduction of the semiconductor device 40 is facilitated.

In any of Embodiments 1 to 4, the bonding material 7 is fluidly deformed by arranging the semiconductor element 6 obliquely. At that time, the bonding material 7 ejected from directly under the semiconductor element 6 may crawl up the side surface of the semiconductor element 6 . Of the side surfaces of the semiconductor element 6, the bonding material 7 tends to crawl up the side surface on which the semiconductor element 6 is lower.

In the present embodiment, the groove 20 can receive the bonding material 7 ejected from directly below the semiconductor element 6 , thereby suppressing the bonding material 7 from crawling up the side surface of the semiconductor element 6 .

The position, depth, length, and width of groove 20 may be adjusted according to the type and amount of bonding material 7 that bonds semiconductor element 6 and die pad 81 . The number of grooves 20 is not limited to one. A plurality of grooves 20 may be provided so as to further suppress the bonding material 7 from crawling up the side surface of the semiconductor element 6 .

In addition, it is possible to combine each embodiment freely, and to modify|transform and abbreviate|omit each embodiment suitably.

1 US horn, 2 capillary, 3, 3a, 3b, 3c wire, 5 spark rod, 6, 13, 13a, 13b semiconductor element, 7 joining material, 8 lead frame, 15 pickup collet, 16, 20 groove, 17, 19 Projection 18 Recess 22 Heatsink 23 Insulating substrate 40, 40c, 40d, 40e, 200 Semiconductor device 80a, 80b, 80c Lead terminal 81, 82 Die pad 101 Wire bonding device 800 Frame 810 Mounting area.

Claims (18)

a lead frame;
a semiconductor element;
with
The semiconductor element is mounted on the lead frame,
the semiconductor element is inclined with respect to a mounting area, which is an area on which the semiconductor element is mounted, on the upper surface of the lead frame;
A first wire is bonded to a first portion of the upper surface of the semiconductor element,
A second wire is bonded to a second portion of the upper surface of the semiconductor element,
the second location is higher from the mounting area than the first location;
semiconductor equipment. The semiconductor device according to claim 1,
The planar shape of the semiconductor element has a width of 3.5 mm or less in at least one direction,
semiconductor device. 3. The semiconductor device according to claim 1 or 2,
The planar shape of the semiconductor element is a shape included in a rectangle having a short side length of 3.5 mm and a long side length of 7 mm,
The semiconductor element has a thickness of 0.5 mm or less.
semiconductor device. The semiconductor device according to any one of claims 1 to 3,
The first wire is bonded to the first location by ball bonding,
the second wire is bonded to the second location by ball bonding;
semiconductor device. The semiconductor device according to any one of claims 1 to 4,
The distance between the first location and the second location is 500 μm or less,
semiconductor device. The semiconductor device according to any one of claims 1 to 5,
The second wire extends from the second location toward the side opposite to the first location with respect to the in-plane direction,
semiconductor device. The semiconductor device according to any one of claims 1 to 6,
The lead frame has lead terminals,
The first wire is joined to the lead terminal,
the tilt of the semiconductor element relative to the mounting area is such that the semiconductor element is lower from the mounting area on a side closer to the lead terminals than on a side farther from the lead terminals;
semiconductor device. The semiconductor device according to any one of claims 1 to 7,
The inclination angle of the semiconductor element with respect to the mounting region is 8 degrees or more and 14 degrees or less.
semiconductor device. The semiconductor device according to any one of claims 1 to 8,
The lead frame has a protrusion on its upper surface,
The semiconductor element is mounted at a position overlapping the protrusion in a plan view,
semiconductor device. The semiconductor device according to claim 9,
a groove is provided on the upper surface of the lead frame, and the protrusion is positioned at the edge of the groove;
The protrusion is formed by removing a part of the lead frame from the groove when forming the groove in the lead frame,
semiconductor device. The semiconductor device according to claim 9,
A recess is provided at a position facing the protrusion on the lower surface of the lead frame,
semiconductor device. The semiconductor device according to any one of claims 1 to 11,
further comprising a bonding material that bonds the semiconductor element and the lead frame;
A groove is provided on the upper surface of the lead frame,
the groove is located on the side of the semiconductor element in the in-plane direction from the higher side to the lower side of the semiconductor element;
part of the bonding material bonding the semiconductor element and the lead frame is in the groove;
semiconductor device. The semiconductor device according to any one of claims 1 to 12,
The semiconductor device is an IC device,
semiconductor device. A semiconductor device manufacturing method for manufacturing the semiconductor device according to any one of claims 1 to 13,
preparing the lead frame and the semiconductor element;
bonding the semiconductor element onto the mounting area of the lead frame so that the semiconductor element is inclined with respect to the mounting area of the lead frame;
After bonding the first wire to the first location on the top surface of the semiconductor device, bonding the second wire to the second location on the top surface of the semiconductor device;
A method of manufacturing a semiconductor device. A method for manufacturing a semiconductor device according to claim 14,
After the bonding of the second wire to the upper surface of the semiconductor element is performed using a capillary at one end of the second wire, the capillary is moved closer to the first point than to the second point in the in-plane direction. move to the side of
A method of manufacturing a semiconductor device. A method for manufacturing a semiconductor device according to claim 14,
After the bonding of the second wire to the upper surface of the semiconductor element is performed using a capillary at one end of the second wire, the capillary is moved closer to the first point than to the second point in the in-plane direction. After that, in the semiconductor device, a portion of the second wire different from the one end is attached to a portion of the semiconductor device on the side opposite to the first portion with respect to the in-plane direction of the second portion. joining the parts with the capillary;
A method of manufacturing a semiconductor device. 17. A method for manufacturing a semiconductor device according to claim 15 or 16,
After the bonding of the one end of the second wire to the upper surface of the semiconductor element, when the capillary is moved in the in-plane direction toward the first location rather than the second location, The difference in height from the mounting region between the capillary or the second wire and the first wire at the same position in the in-plane direction is the difference between the first location and the second location on the upper surface of the semiconductor element. is smaller than the difference in height from the mounting area to the location of
A method of manufacturing a semiconductor device. A method for manufacturing a semiconductor device according to any one of claims 15 to 17,
In the bonding of the second wire to the upper surface of the semiconductor element, the inclination of the capillary with respect to the mounting region is smaller than the inclination of the capillary with respect to the upper surface of the semiconductor element.
A method of manufacturing a semiconductor device.

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