JPH066215A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To provide a frequency synthesizer capable of switching the frequency at a high speed. CONSTITUTION:The pulses are deleted for the time set previously by a pulse deleting gate 15 provided between a voltage control oscillator 14 and a variable divider 16. Then the output of the divider 16 obtained right after the switching of frequency is shifted to a desired phase difference position against the output signal of a reference oscillator 11. Thus, the frequency can be switched at a high speed and the switching time can be extremely shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer capable of performing frequency switching operation at high speed.

[0002]

2. Description of the Related Art FIG. 6 shows, for example, JP-A-3-229517.
FIG. 6 is a block diagram showing a conventional PLL frequency synthesizer disclosed in Japanese Patent Laid-Open Publication No. HEI-2003. In the figure, reference numeral 1 denotes a sample-hold type phase comparator, which is composed of a JK flip-flop 2, an integrator 3, and a sample-hold circuit 4. The comparison frequency fref is input to the J input terminal of the JK flip-flop 2. The output of the sample hold circuit 4 is connected to the K input terminal of the JK flip-flop 2 via the VCO 5, the frequency divider 6, and the switch 7. 8 is a counter (phase difference detection pulse generating means),
9 is a memory.

Next, the operation will be described. The VCO 5 oscillates a frequency corresponding to the output voltage of the sample-and-hold type phase comparator 1, divides the oscillated output by a frequency divider 6 at a frequency division ratio corresponding to a predetermined frequency, and outputs the frequency division output and the comparison frequency. Input fref and the sample-hold type phase comparator 1. Then, a voltage corresponding to the phase difference between the frequency division output and the comparison frequency fref is input to the VCO 5, and the oscillation frequency can be stabilized by the PLL method.

FIG. 7 is a timing chart for explaining the operation of the sample hold type phase comparator 1. When the comparison frequency fref and the output fdiv of the frequency divider 6 are input to the JK flip-flop 2, the JK flip-flop 2 outputs a pulse corresponding to the phase difference to the integrator 3, and the integrator 3 outputs only the time corresponding to the pulse. The sawtooth voltage obtained by charging is input to the sample and hold circuit 4, and the sample and hold circuit 4 holds the input voltage and uses it as the control voltage of the VCO 5.

When switching the output frequency by changing the frequency division ratio of the frequency divider 6, the counter 8 generates a pulse equal to the fdiv pulse position corresponding to each frequency division number stored in the memory 9 in advance. Immediately after switching the output frequency, the output of the counter 8 is selected by the switch 7 as fdiv to be input to the sample-hold type phase comparator 1, and the output of the VCO 5 is rapidly changed to a predetermined frequency. After that, the output of the frequency divider 6 is selected by the switch 7 to enter the steady state.

Next, the operations of the counter 8 and the memory 9 will be described with reference to FIG. The counter 8 is counted up for the time corresponding to the phase difference between the frequency divider output fdiv and the comparison frequency fref for each output frequency, and the value is stored in the memory 9
Remember. At the same time, the counter 8 is counted down by the value stored in the memory 9, and a pulse is output at the timing when the count value becomes zero.

[0007]

The conventional frequency teaching synthesizer is constructed as described above, and it requires complicated components such as a counter and a memory and has a problem of high price.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a frequency synthesizer capable of switching frequencies at high speed and in a short time with a relatively simple structure. And

[0009]

A reference oscillator for generating a reference signal, a voltage controlled oscillator whose frequency is determined according to an applied voltage, and a variable frequency divider for dividing an output signal of the voltage controlled oscillator by N. A sample-and-hold type phase comparator that outputs a voltage value according to the phase difference between the output signal of the variable frequency divider and the output signal of the reference oscillator, and removes the harmonics of the output of the sample-and-hold type phase comparator. A filter circuit that applies the obtained output voltage to the voltage controlled oscillator, a gate that removes a signal pulse sent from the voltage controlled oscillator to the variable frequency divider, and a change in the output voltage of the sample hold type phase comparator A monitoring circuit for monitoring and a control circuit for switching the frequency division ratio of the variable frequency divider, opening and closing the gate, and detecting the output signal of the monitoring circuit are provided. Then, the control circuit sets the frequency division number of the variable frequency divider when switching the frequency, and at the same time, removes the signal pulse sent from the voltage controlled oscillator to the variable frequency divider for a preset time. The gate is controlled as described above, the output signal of the variable frequency divider immediately after switching is moved to the desired phase difference position corresponding to the frequency after switching with respect to the output signal of the reference oscillator, and it is detected by the monitoring circuit. It is configured to correct the gate-off time by a signal based on changes in environment and conditions.

Further, instead of providing a gate for removing a signal pulse sent from the voltage controlled oscillator to the variable frequency divider, at the time of switching, the frequency division number of the variable frequency divider immediately after switching is stored in advance. Value, and the output signal of the variable frequency divider immediately after switching is moved to a desired phase difference position corresponding to the frequency after switching with respect to the output signal of the reference oscillator, and then set to a steady-state value. Thus, the control circuit is configured.

[0011]

In the frequency synthesizer according to the present invention, the gate for pulse removal provided between the voltage controlled oscillator and the variable frequency divider provides a signal pulse sent from the voltage controlled oscillator to the variable frequency divider for a preset time. By simply removing the signal and moving the output signal of the variable frequency divider immediately after switching to the desired phase difference position with respect to the output signal of the reference oscillator, the frequency is switched at high speed, and the switching time at the time of frequency switching is greatly reduced. You can do it.

Further, instead of having a gate for removing the signal pulse sent from the voltage controlled oscillator to the variable frequency divider, the frequency division ratio of the variable frequency divider immediately after switching by the control circuit is set to a preset value at the time of switching. After moving the output signal of the variable frequency divider immediately after switching to the desired phase difference position corresponding to the frequency after switching with respect to the output signal of the reference oscillator,
Set to a value that is constant. In this way, the frequency can be switched at high speed by setting the frequency division ratio of the variable frequency divider in two stages, first to a preset initial value and then to a steady value.

[0013]

EXAMPLES Example 1. FIG. 1 is a block diagram showing an embodiment of a frequency synthesizer according to the present invention. In FIG. 1, reference numeral 11 is a reference oscillator that generates a reference signal having a stable frequency. The sample-hold type phase comparator 12 includes an output signal from the reference oscillator 11 and a variable frequency divider 16 described later.
Outputs a voltage corresponding to the phase difference of the output signal from. The filter circuit 13 removes harmonics of the output signal from the sample-hold type phase comparator 12 and outputs it. The voltage controlled oscillator 14 outputs a frequency corresponding to the output signal from the filter circuit 13. The variable frequency divider 16 frequency-divides the output signal from the voltage controlled oscillator 14 obtained via the gate 15 and outputs the signal to the sample hold type phase comparator 12. The gate 15 is provided with a voltage controlled oscillator 14 which is sent to the variable frequency divider 16 in response to a signal from a control circuit 18 described later.
Remove the required number of output signal pulses from. Reference numeral 17 is a monitoring circuit for monitoring the input signal and the output signal of the sample hold type phase comparator 12, and the control circuit 18 is for the monitoring circuit 1.
The table of the gate-off time is changed according to the detection signal from 7. Further, the control circuit 18 changes the frequency division number N of the variable frequency divider 16 when switching the output frequency.

Next, the operation of this embodiment will be described.
In FIG. 1, the operation of the sample-hold type phase comparator 12 and the operation of the PLL loop in the steady state are the same as those of the conventional example, and therefore the description thereof is omitted, and the operation at the time of switching the output frequency is referred to FIGS. And explain. In the following description, two output frequencies OH and OL (OH> OL
) Is assumed. The output signals fdiv obtained by dividing the output frequencies OH and OL by the variable frequency divider 16 have a certain phase difference with respect to fref like fL and fH shown in FIG. 2, respectively. When the output frequency is switched from OL to OH, the frequency dividing number N to the variable frequency divider 16 by the control circuit 18 is normally set.
By changing the setting from nL to nH, the pulse of the output fdiv gradually changes from the position of fL to the position of fH as shown in fN, and finally stops at the position of fH, and the frequency OH becomes stable. Is output.

On the other hand, the output frequency OL aimed at by the present invention is
The high-speed switching from OH to OH causes the pulse of the output fdiv of the variable frequency divider 16 from the position of fL to f immediately after the frequency division number N is changed.
This can be done by instantly moving to the H position.

When the output frequency is switched from OL to OH, the control circuit 18 changes the setting of the frequency division number N which determines the frequency division ratio of the variable frequency divider 16 from nL to nH, and then the control circuit 18 stores in advance. The gate-off signal G is sent to the gate 15 only for the time corresponding to the change from OL to OH stored in the table.
Send LH. The gate 15 removes the required number of output signal pulses sent from the voltage controlled oscillator 14 to the variable frequency divider 16 by the gate-off signal GLH. By removing the required number of output signal pulses, the count in the variable frequency divider 16 is delayed, and the pulse fLH input to the sample-hold type phase comparator 12 is changed to the position f before switching at the next pulse.
Move from L to position fH after switching.

When the position of the pulse fLH after switching reaches the vicinity of the target pulse position fH, the fluctuation of the input voltage of the voltage controlled oscillator 14 thereafter becomes small and the output frequency converges early, so that the output frequency is high. It is possible to switch. In particular, the fastest switching is to completely match the position of the pulse fLH after switching and the target pulse position. For that purpose, it is necessary to optimize the table of the gate-off time according to the output frequency change of the control circuit 18. There is. Therefore, the table storing the optimum initial value can be changed according to the variation of the device and the change of the environment.

The adaptive modification of the control circuit 18 table is as follows:
The detection result of the monitoring circuit 17 is used. FIG. 5 is a diagram showing the configuration of the monitoring circuit 17, and its operation will be described below. Sample-and-hold type phase comparator 1 changed due to turning off the gate 15 immediately after frequency switching
The output voltage value of 2 is stored in the delay circuit 19 using the output of the reference oscillator 11 as a clock. Next, the output voltage value of the sample-hold type phase comparator 12 in the steady state is compared with the voltage value stored in the delay circuit 19, and the difference value is sent to the control circuit 18. The control circuit 18 changes the contents of the table according to the difference value. For example, the delay circuit 19
If the voltage value stored in is lower, the control circuit 18 corrects the contents of the table so that the gate-off time becomes longer. On the contrary, when the voltage value stored in the delay circuit 19 is higher, the control circuit 18 corrects the contents of the table so that the gate-off time becomes shorter.

Even when the output frequency is switched from OH to OL, the input pulse to the variable frequency divider 16 is removed immediately after switching as shown by GHL and fHL in FIG.
High-speed switching is possible in the same way as when switching from OL to OH.

Example 2. 3 and 4 show a second embodiment of the present invention. In the connection configuration of this embodiment, the gate 15 provided between the voltage controlled oscillator 14 and the variable frequency divider 16 in the first embodiment is removed, and the output of the voltage controlled oscillator 14 is fed to the variable frequency divider 16. It is the same except that it was directly connected.

Immediately after changing the frequency division number NLH, the variable frequency divider 16
By instantaneously moving the pulse of the output fdiv from the position of fL to the position of fH, the output frequency can be switched at high speed.

When switching the output frequency from OL to OH, the control circuit 18 first divides the frequency divider N into the variable frequency divider 16.
The setting of LH is changed from nL to a value nLH corresponding to the change from OL to OH stored in the table of the control circuit 18 in advance. nLH is a value larger than the set value nH in the steady state, and the variable frequency divider 16 needs more input signal pulses according to the value nLH to generate the output signal pulse. As a result, the output signal pulse fLH of the variable frequency divider 16 input to the sample-hold type phase comparator 12 moves from the position fL before switching to the target position fH after switching in the next pulse. Immediately after the output signal pulse fLH of the variable frequency divider 16 reaches the target position fH, the setting of the frequency division number NLH is changed to the steady state value nH and the steady state is entered.

When the position of the pulse fLH after switching reaches the vicinity of the target pulse position fH, the fluctuation of the input voltage of the voltage controlled oscillator 14 thereafter becomes small, the output frequency converges early, and high speed switching is performed. In particular, the fastest switching is to completely match the position of the pulse fLH immediately after switching and the target pulse position fH, and for that purpose,
It is necessary to optimize the table of the frequency division number setting value immediately after switching according to the output frequency change of the control circuit 18. Therefore, the table storing the optimum initial value can be changed according to the variation of the device and the change of the environment.

The adaptive modification of the control circuit 18 table is as follows:
Similar to the first embodiment, the detection result of the monitoring circuit 17 is used. The output voltage value of the sample-hold type phase comparator 12 at constant time is compared with the voltage value stored in the delay circuit 19, and the difference value is sent to the control circuit 18. The point that the control circuit 18 changes the contents of the table according to the difference value is the same as in the first embodiment. However, in the first embodiment, for example, when the voltage value stored in the delay circuit 19 is lower, the control circuit 1
8 corrects the contents of the table in the direction of increasing the gate-off time, and conversely, when the voltage value stored in the delay circuit 19 is higher, the control circuit 18 corrects the contents of the table in the direction of decreasing the gate-off time. On the other hand, in the second embodiment, when the voltage value stored in the delay circuit 19 is lower,
The control circuit 18 corrects the contents of the table so that the frequency division number N of the variable frequency divider 16 immediately after switching is increased. Conversely, when the voltage value stored in the delay circuit 19 is higher, the control circuit 18 The contents of the table are corrected so that the frequency division number N of the variable frequency divider 16 immediately after the switching becomes smaller.

Even when the output frequency is switched from OH to OL, as shown by NHL and fHL in FIG. 4, by setting a number nHL smaller than nL immediately after switching, the same method as when switching from OL to OH is performed. High-speed switching is possible.

[0026]

As described above, according to the present invention, a pulse removing gate is provided between the voltage-controlled oscillator and the variable frequency divider, and the signal pulse sent from the voltage-controlled oscillator to the variable frequency divider is previously set. It is removed only for the set time and the output signal of the variable frequency divider immediately after switching is moved to the desired phase difference position with respect to the output signal of the reference oscillator. The frequency division number is set in two stages, first to a preset initial value and then to a steady value, and the output signal of the variable frequency divider immediately after switching is set to a desired value with respect to the output signal of the reference oscillator. Since the structure is instantly moved to the phase difference position, it is possible to obtain a frequency synthesizer which has a simple structure, low current consumption, and low cost, and which can switch the output frequency at high speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of a frequency synthesizer according to the present invention.

FIG. 2 is a timing diagram showing an operation of the first embodiment of the frequency synthesizer according to the present invention.

FIG. 3 is a configuration diagram showing a second embodiment of the frequency synthesizer according to the present invention.

FIG. 4 is a timing diagram showing the operation of the second embodiment of the frequency synthesizer according to the present invention.

FIG. 5 is a block diagram showing a configuration of a monitoring circuit used in the first and second embodiments of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional frequency synthesizer.

FIG. 7 is a timing chart showing the operation of the sample hold type phase comparator.

FIG. 8 is a timing chart showing the operation of the phase difference detection pulse generating means of the conventional frequency synthesizer.

[Explanation of symbols]

 11 Reference Oscillator 12 Sample Hold Type Phase Comparator 13 Filter Circuit 14 Voltage Controlled Oscillator 15 Gate 16 Variable Frequency Divider 17 Monitoring Circuit 18 Control Circuit 19 Delay Circuit

Claims (2)

[Claims] 1. A reference oscillator that generates a reference signal, a voltage-controlled oscillator whose frequency is determined according to an applied voltage, and a variable frequency divider that divides an output signal of the voltage-controlled oscillator by N.
A sample-and-hold type phase comparator that outputs a voltage corresponding to the phase difference between the output signal of the variable frequency divider and the output signal of the reference oscillator, and a harmonic obtained from the output of the sample-and-hold type phase comparator are removed. A filter circuit for applying an output voltage to the voltage controlled oscillator, a gate for removing a signal pulse sent from the voltage controlled oscillator to the variable frequency divider, and a change in the output voltage of the sample hold type phase comparator. The control circuit includes a monitoring circuit and a control circuit that sets the frequency division number of the variable frequency divider, opens and closes the gate, and detects an output signal of the monitoring circuit. At the same time as setting the frequency division number of the frequency divider, the gate is controlled so as to remove the signal pulse sent from the voltage controlled oscillator to the variable frequency divider for a preset time. , The output signal of the variable frequency divider immediately after switching is moved to a desired phase difference position corresponding to the frequency after switching with respect to the output signal of the reference oscillator, and changes in the environment or conditions detected by the monitoring circuit A frequency synthesizer characterized by modifying the gate-off time by a signal based on it. 2. A reference oscillator for generating a reference signal, a voltage controlled oscillator whose frequency is determined according to an applied voltage, and a variable frequency divider for dividing an output signal of the voltage controlled oscillator by N.
A sample-and-hold type phase comparator that outputs a voltage corresponding to the phase difference between the output signal of the variable frequency divider and the output signal of the reference oscillator, and a harmonic obtained from the output of the sample-and-hold type phase comparator are removed. A filter circuit for applying an output voltage to the voltage controlled oscillator, and a monitoring circuit for monitoring a change in the output voltage of the sample-hold type phase comparator,
A control circuit for setting the frequency division number of the variable frequency divider and detecting the output signal of the monitoring circuit, wherein the control circuit comprises:
The frequency division number of the variable frequency divider immediately after the switching is set to the value at the time of switching stored in advance, and the output signal of the variable frequency divider immediately after the switching is changed to the output signal of the reference oscillator. The frequency synthesizer is characterized in that the value is set to a steady value after being moved to a desired phase difference position corresponding to.