JPH0568134U - PLL frequency synthesizer - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a PLL frequency synthesizer which is capable of reducing lock-up time and which is less likely to be out of lock due to frequency switching. In a PLL frequency synthesizer, a switch 23 provided between a phase comparator 10 and a loop filter 30 and a switch 23 is controlled to be in an off state for a predetermined period with a delay based on an output frequency change width from a time when an output frequency is changed. And a timing signal generating circuit 25 for

Description

[Detailed description of the device]

[0001]

[Industrial application]

 The present invention relates to a PLL frequency synthesizer.

[0002]

[Prior art]

In the conventional PLL frequency synthesizer, for example, when the frequency is switched from the higher side to the lower side at time t ₁ as shown in FIG. 2, the frequency control voltage supplied to the voltage controlled oscillator is as shown by the broken line in FIG. PLL circuit for causing the vibration took time (time t ₁ ~ time t ₇₎ before lock.

Therefore, in order to shorten the lock-up time, as shown in FIG. 10, a narrow band loop filter 32 and a wide band loop filter 31 that receives the output of the narrow band loop filter 32 are connected in cascade. Then, the output of the phase comparator 10 is supplied to the narrow band loop filter 32, the output of the wide band loop filter 31 is applied as a frequency control voltage to the voltage controlled oscillator 40, and the switch 21 driven off by the lock signal is supplied. , The narrow band loop filter 32 is selectively short-circuited, and the switch 21 is controlled to be in the ON state at the time of frequency switching, so that the narrow band loop filter 32 is substantially cut off to shorten the lock-up time and After that, the switch 21 is controlled to the off state, and the narrow band loop filter 32 is inserted to suppress the spurious. I have to.

Further, as shown in FIG. 11, the output of the phase comparator 10 is supplied to a wide band loop filter 31 and a narrow band loop filter 32, and a switch 22 supplies a wide band loop filter 31 and a narrow band loop filter 32. One of the two is selected, and the selected output is applied as a frequency control voltage to the voltage controlled oscillator 40. The output of the wide band loop filter 31 is selected and locked by the switch 22 from the time of frequency switching to the time of locking. After that, the output of the narrow band loop filter 32 is selected by the switch 22 and the selected output is used as the frequency control voltage of the voltage controlled oscillator 40.

[0005]

[Problems to be solved by the device]

 However, when the former PLL frequency synthesizer of the above-mentioned conventional example is used, when the switch 21 is turned from the ON state to the OFF state, the frequency control is performed due to the influence of the voltage due to the electric charge charged in the narrow band loop filter 32. There was a problem that the voltage was changed in steps and the lock was released.

Further, in the case of the latter PLL frequency synthesizer of the above-mentioned conventional example, when the switch 22 switches from the wide band loop filter 31 to the narrow band loop filter 32, the charges stored in both loop filters are charged. If there is a difference in voltage due to the above, there is a problem that the control voltage applied to the voltage controlled oscillator 40 changes in steps and is out of the locked state. Further, even if the voltages due to the electric charges charged in both loop filters are equal, a transient phenomenon occurs when switching is instantaneously performed by the switch 22, and there is a problem in that the voltage generated by this causes lock release. It was

It is an object of the present invention to provide a PLL frequency synthesizer which has a short lock-up time and which is less likely to be out of lock due to frequency switching.

[0008]

[Means for Solving the Problems]

 The PLL frequency synthesizer of the present invention is a PLL frequency synthesizer in which the switch provided between the phase comparator and the loop filter and the switch is turned off for a predetermined period after a period based on the output frequency change width from when the output frequency is changed. And a control means for controlling.

[0009]

[Action]

 According to the PLL frequency synthesizer of the present invention, when the output frequency is changed, the switch is turned off for a predetermined period when the output frequency is changed and a period delayed by the output frequency change width is delayed. Therefore, the frequency control voltage of the voltage controlled oscillator is maintained at a voltage according to the charge charged in the loop filter during switch off, and the switch is turned off when the frequency control voltage corresponding to the changed output frequency is reached. The switch-off period can be set to a period that minimizes overshoot and undershoot, the lockup time is reduced, and lock loss is less likely to occur when the output frequency is changed.

[0010]

【Example】

 Hereinafter, the present invention will be described with reference to examples. FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention.

In the PLL frequency synthesizer of the first embodiment, the phase comparator 10 compares the phase of the input signal of the reference frequency fr with the phase of the output signal of the variable frequency divider 50, and outputs the phase comparison output to the switch 20. To the voltage controlled oscillator 40 as a frequency control voltage, and the output of the voltage controlled oscillator 40 is supplied to the variable frequency divider 50 for frequency division. The output (frequency fv) of the frequency divider 50 is supplied to the phase comparator 10. The switch 20 controls ON / OFF by the output of the timing signal generation circuit 25.

Here, the frequency division ratio is changed by the variable frequency divider 50, and the frequency control voltage reaches the frequency control voltage corresponding to the changed frequency division ratio. The switch 20 is configured to be controlled by the timing signal generating circuit 25 so as to be controlled.

In the PLL frequency synthesizer of the first embodiment configured as described above, the circuit excluding the switch 20 is a normal PLL frequency synthesizer, and the operation during the ON state of the switch 20 is the normal PLL frequency synthesizer. It is similar to the case of the synthesizer. Now, it is assumed that the switch 20 is controlled to be in the ON state when the output signal of the timing signal generating circuit 25 is at the high potential level and to be in the OFF state when the output signal is at the low potential level.

A signal of a high potential level is usually output from the timing signal generating circuit 25, and the switch 20 is controlled to be in an ON state. As shown in FIG. 2, for example, at time t ₁ , if the frequency division ratio control data (D) input to the variable frequency divider 50 is changed to change the output frequency from f _H to f _L (f _H > f _L ). , The frequency control voltage starts to drop. Here, the frequency f _H is the oscillation frequency of the voltage controlled oscillator 40 in the state where the frequency control voltage V _H is applied, and the frequency f _L is the state in which the frequency control voltage V _L (V _H > V _L ) is applied. It is the oscillation frequency of the voltage controlled oscillator 40.

The frequency control voltage becomes the voltage V _L for oscillating the frequency f _L at time t ₄ , but if the switch 20 is in the ON state at this time, an undershoot occurs as shown by the broken line in FIG. Will occur. However, from time t ₄ to t ₅ , as shown in FIG. 3, the signal of low potential level is output from the timing signal generation circuit 25 for a period of, for example, several tens of μsec. Therefore, the switch 20 is controlled to be in the off state only during this period.

By this operation, the frequency control voltage applied to the voltage controlled oscillator 40 from the time t ₄ to the time t ₅ is maintained at the voltage V _L by the charges charged in the loop filter 30. At time t ₅ , the output of the timing signal generating circuit 25 controls the switch 20 to be turned on again, the PLL loop is formed again, and the phase synchronization operation is started.

At this time, between the frequency fv of the output signal output from the variable frequency divider 50 (FIG. 4A) and the frequency fr of the reference signal input to the phase comparator 10 (FIG. 4B). When there is a phase difference between the two, an error voltage is generated as shown in FIG. Due to this error voltage, the frequency control voltage changes away from V _L.

However, as described above, the PLL loop is closed and the phase locked operation is restarted when the frequency control voltage is extremely close to V _L. Therefore, as shown by the solid line in FIG. 2, the amount of change in the frequency control voltage is extremely small, the frequency control voltage becomes stable at time t ₆ , and the lock-up time of the PLL frequency synthesizer in the first embodiment is the time ( It will be shortened to t ₆ −t ₁ ).

Further, although the case where the output frequency is changed from f _H to f _L has been described above, the same operation is performed even when the output frequency is changed from f _L to f _H , and the lockup time can be shortened. Can be achieved.

Further, although the embodiment in which the reference frequency is fixed and the division ratio is variable has been described, when the reference frequency is variable and the division ratio is fixed, the reference frequency and the division ratio are also changed. The same can be applied even when both ratios are variable.

Next, a second embodiment of the present invention will be described. FIG. 5 is a block diagram showing the configuration of the second embodiment of the present invention.

In the PLL frequency synthesizer of the second embodiment, the phase comparator 10 compares the phase of the input signal having the reference frequency fr with the phase of the output signal of the variable frequency divider 50, and outputs the phase comparison output to the switch 23. To the voltage controlled oscillator 40 as the frequency control voltage, and the output of the voltage controlled oscillator 40 is supplied to the variable frequency divider 50 for frequency division. The output (frequency fv) of the frequency divider 50 is supplied to the phase comparator 10. The variable frequency divider 50 and the switch 23 control the frequency division ratio and switch switching timing according to the output of the control circuit 60.

As shown in FIG. 6, the control circuit 60 receives the instruction, generates the frequency division ratio data, and outputs the frequency division ratio data to the variable frequency divider 50. When the frequency division ratio data is changed by receiving the frequency division ratio data from the counter 63, which generates a low potential output upon completion of counting, and the data generation circuit 61, the frequency division ratio data changed and the frequency division ratio data before the change The data comparison circuit 62, which calculates the absolute value of the difference between and, and sets the count value of the counter 63 based on the calculation result. Receiving signals from the clock gate signal generation circuit 66, the clock pulse generator 65, and the clock gate signal generation circuit 66 for output, the gate is opened to generate the clock pulse during the gate opening period. It comprises an edge-triggered monostable multivibrator 67 which is triggered by the signal at the end of counting of the counter 63 and a clock gate 64 which supplies the clock of the counter 65 to the counter 63 and which controls the switch 23 at the output.

In the second embodiment configured as described above, the clock pulse generator 65 generates clock pulses as shown in FIG. 7 (a). When the output frequency is changed, new frequency division ratio data is sent from the data generation circuit 61 to the variable frequency divider 50. Now, the frequency division ratio data when the output frequency f _H D _H, the division ratio data when the output frequency f _L and D _L. When the output frequency is changed from f _H to f _L, in the data comparison circuit 62 | D _H -D _L | operation is performed, the count value of the counter 63 is set in accordance with the operation result.

At the time of frequency switching, a signal is sent from the data generation circuit 61 to the clock gate signal generation circuit 66, and the gate of the clock gate 54 receiving this signal is opened for a predetermined period shown in FIG. The pulse is counted by the counter 63 up to the count value set by the output from the data comparison circuit 62. While the counter 63 is counting, a high potential output is output as shown in FIG. 7C, and a low potential output is output from the end of the count.

Upon receiving the low potential output from the counter 63, the edge trigger monostable multivibrator 67 outputs the off signal shown in FIG. 7D to the switch 23. Therefore, in response to this signal, the switch 23 is controlled to the off state only during the period shown in FIG. 7 (d).

Therefore, as shown in FIG. 2, the output frequency is f_HTo f_LWhen changed to | D _H -D_LTime t according to the calculation result of |_FourThat is, as shown in FIG. 3, the frequency control voltage is V_LTime t reached_FourThe switch 23 is controlled to be turned off at the time t, and after the set period t of the edge trigger monostable multivibrator 67 has elapsed,_FiveIs controlled to ON state. As a result, the frequency control voltage applied to the voltage controlled oscillator 40 for the period t is the voltage V due to the electric charge charged in the loop filter 30._LMaintained at. Therefore, as shown in FIG. 2, the lock-up time of the PLL frequency synthesizer in the second embodiment is also the time (t₆-T₁) Will be shortened to.

Further, as shown in FIG. 8, when the output frequency is changed from f _H to f _M (f _H > f _M > f _L ) at time t ₁ , | D _H −D _M as in the case described above. | time t ₂ corresponding to the calculation result, i.e. Oite switch 23 at time t ₂ when the frequency control voltage reaches V _M as shown in FIG. 9 is controlled to be off, setting the edge trigger monostable multivibrator 67 It is controlled to be in the ON state at time t ₃ when the period t has elapsed. As a result, during the period t, the frequency control voltage applied to the voltage controlled oscillator 40 is maintained at the voltage V _M by the charges charged in the loop filter 30. Therefore, the lock-up time of the PLL frequency synthesizer of the second embodiment as shown in FIG. 8 is a shortened time _{(t 4 '-t 1)} .

Further, although the case where the output frequency is reduced has been illustrated in the second embodiment, the case where the output frequency is increased is similar, and the lockup time can be shortened.

[0030]

[Effect of the device]

 As described above, according to the present invention, when the output frequency is changed, the switch is turned off for a predetermined period when the output frequency is changed and then the period based on the output frequency change width is delayed. The frequency control voltage of the voltage controlled oscillator is maintained at a voltage corresponding to the charge, and the switch is turned off when the frequency control voltage corresponding to the changed output frequency is reached. The off period can be set to a period that minimizes overshoot and undershoot, which has the effects of reducing lockup time and preventing lock loss when changing the output frequency.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a frequency control voltage for explaining the operation of the first and second embodiments of the present invention.

FIG. 3 is a timing diagram for explaining the operation of the first and second embodiments of the present invention.

FIG. 4 is a waveform diagram of an error voltage provided for explaining the operation of the first embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a control circuit according to a second embodiment of the present invention.

FIG. 7 is a timing diagram for explaining the operation of the control circuit according to the second embodiment of the present invention.

FIG. 8 is a schematic diagram showing a frequency control voltage for explaining the operation of the second embodiment of the present invention.

FIG. 9 is a timing diagram for explaining the operation of the second embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional example.

FIG. 11 is a block diagram showing another configuration of the conventional example.

[Explanation of symbols]

 10 phase comparator 20 and 23 switch 25 timing signal generation circuit 30 loop filter 40 voltage controlled oscillator 50 variable frequency divider 60 control circuit

Claims (1)

[Scope of utility model registration request] 1. In a PLL frequency synthesizer, a switch provided between a phase comparator and a loop filter, and control for turning off the switch for a predetermined period with a delay based on the output frequency change width after the output frequency is changed. A PLL frequency synthesizer comprising: