JP2006140852A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit in which a signal disconnecting/connecting means is provided for inputting and disconnecting a phase error detected by a phase comparator to/from a loop filter and the signal disconnecting/connecting means is controlled so as to disconnect the phase error within a range where runaway occurs in a CV line, and thus the runaway of the CV line is cut, and a response delay of an input-output voltage of the loop filter is improved as a result. <P>SOLUTION: The PLL circuit 100 comprises a reference signal generator 1 for generating a reference frequency signal F, the phase comparator 2 for comparing a signal subjected to frequency division by a frequency divider 9 with the reference frequency signal F in phase, the signal inputting/disconnecting means 3 for inputting/disconnecting the phase error ε detected by the phase comparator 2 to/from the loop filter 4, the loop filter 4 for integrating the phase error ε compared by the phase comparator 2, a VCO (voltage controlled oscillator)-A5 and a VCO (voltage controlled oscillator)-B6 the oscillation frequency f of each of which is controlled on the basis of a control voltage v, a CPU (control means) 8 for setting a frequency division ratio in the frequency divider 9 and controlling the signal disconnecting/connecting means 3, and the frequency divider 9 for performing the frequency division of the oscillation signal frequency f oscillated by the VCO A5 and B6 with a prescribed frequency division ratio. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a PLL circuit, and more particularly to a PLL circuit in which a response delay of an input / output voltage of a loop filter generated when moving a free-running frequency of a voltage controlled oscillator is improved.

In a PLL circuit, in general, characteristics after the output frequency of a voltage controlled oscillator (hereinafter referred to as VCO) is in a steady state (steady characteristics) and pull-in characteristics (synchronous characteristics) until phase synchronization with a reference frequency signal is achieved. ) Are in conflict with each other. For example, it is known that when the frequency pull-in range of the synchronization characteristic is widened and the synchronization speed is increased, the noise band of the loop is widened and the characteristic at the steady state is deteriorated. Therefore, it is desirable for the PLL circuit to speed up the lock-up time until the VCO oscillation frequency is pulled into the reference frequency signal and phase-synchronized. Has been.
FIG. 9 is a schematic diagram for explaining the frequency shift of a conventional wireless device. For example, in the case of a circuit configuration in which there are two VCOs as in the PLL circuit 100 of FIG. 1 and the circuit is controlled by the same control voltage line (hereinafter referred to as CV line), the free-running frequency range of each VCO is f1 Suppose that f2 and VCO2-B6 are f3 to f4, and the respective frequencies have a relationship of f1 <f2 <f3 <f4. Then, considering the operation when the VCO-A5 is previously switched from the state in which the VCO-A5 is locked to the phase difference within a certain range at the oscillation frequency f1 to f4, one pattern is as shown in the flowchart of FIG. That is, when the CPU 8 receives an instruction to switch to the frequency f4 by the frequency switch SW7, the CPU 8 switches from the VCO-A5 having the free-running frequency of f1 to the VCO2-B6 having the free-running frequency of f4 (S21). Next, the CPU 8 sets a frequency division ratio based on the frequency of f4 in the frequency divider 9 (S22). As a result, the PLL circuit 100 starts to operate at the frequency of f4 (S23), and as a result, the CV line 14 converges to become the frequency of f4 (S24).
FIG. 11 is a timing chart during frequency shift based on the flowchart of FIG. The operation of the PLL 100, VCO-A and B switching signals, and the movement of the CV line are shown from above. When the CPU 8 outputs a signal for switching from VCO-A5 to VCO-B6, the switching signal for VCO-A5 and VCO-B6 is switched to the VCO-B6 side (operation in S21). However, since the data of f4 has not been received yet, the CV line 14 tries to keep the voltage 1V locked to f1. That is, it is around the position of f3 in FIG. However, since the data remains at f1, the CV line 14 decreases to Vmin in order to become f1 having a frequency lower than f3 (range A). After that, when data of f4 is received (operation of S22), the PLL circuit starts operation from the level of Vmin (operation of S23) trying to reach the frequency of f4, and the CV line 14 attempts to reach the frequency of f4 to 10V. (Range B). The pattern for first switching the VCO is referred to as pattern 1 above.

FIG. 12 is a flowchart in the case of another pattern. That is, when the CPU 8 receives an instruction to switch to the frequency f4 by the frequency switching SW7, the CPU 8 sets a frequency division ratio based on the frequency f4 in the frequency divider 9 (S31). Then, the CPU 8 switches from VCO-A5 having the free-running frequency of f1 to VCO2-B6 having the free-running frequency of f4 (S32). As a result, the PLL circuit 100 starts to operate at the frequency of f4 (S33), and as a result, the CV line 14 converges to become the frequency of f4 (S34).
FIG. 13 is a timing chart at the time of frequency shift based on the flowchart of FIG. The operation of the PLL 100, VCO-A and B switching signals, and the movement of the CV line are shown from above. In this pattern, since the CPU 8 first receives the data of f4 (operation of S31), the CV line moves from the 1V line to around 10V. That is, it is around the position f2 in FIG. However, since it remains VCO-A5, the CV line rises to Vmax to become f4 having a frequency higher than f2 (A range). Next, when the CPU 8 outputs a signal for switching from VCO-A5 to VCO-B6, the switching signal for VCO-A and B is switched to the VCO-B6 side (operation in S32). At that time, since the data of f4 has already been received, the PLL circuit operates to reach the frequency of f4 (operation of S33), and the CV line 14 converges to 10V to reach the frequency of f4 (range B). . The pattern for receiving the frequency data first is referred to as pattern 2 above. In this way, the CV line of the PLL circuit at the time of the conventional frequency shift has a CV ramp in the A range.
In addition, as a conventional technique for increasing the lock-up time, Patent Document 1 discloses that the control voltage of the output of the loop filter that controls the phase fluctuation within a certain range of the oscillation frequency is applied to the VCO of the PLL circuit in order to increase the lock-up time. Separately, a fixed control voltage for determining the free-running frequency of the VCO is stored in advance, and when the free-running frequency of the VCO is changed from one frequency to another frequency, the stored control voltage is switched to change the VCO. The technology of the self-running frequency control voltage supply means of the VCO supplied to the VCO is disclosed.
JP 05-327490 A

However, in the conventional PLL circuit control method described with reference to FIGS. 9 to 13, in any of the patterns 1 and 2, the CV line 14 in the range A is in the range of Vmin and Vmax. Since the operation of converging to the free-running frequency of B6 is started, there is a problem that a longer time is required until the convergence, resulting in a longer lock-up time until phase synchronization.
Further, in Patent Document 1, a D / A converter that converts an analog voltage based on voltage data output from the free-running frequency control voltage supply means of the VCO is provided, and the output of the D / A converter is converted to a VCO. In order to avoid the deterioration of C / N (Carrier to Noise) and S / N of the VCO output signal due to noise actually output from the D / A converter. In addition, an LPF composed of a resistor and a capacitor is inserted between them. However, in this case, although there is a delay in the response of the LPF in spite of the provision of the VCO free-running frequency control voltage supply means for speeding up the lockup, the speedup beyond the delay time of the LPF is not possible. It was impossible.
The present invention has been made in view of such a problem, and includes a signal connection / disconnection means for inputting or blocking a phase error detected by a phase comparator to a loop filter, and the phase error is detected in the loop filter in a range where the CV line is exposed. An object of the present invention is to provide a PLL circuit in which the response delay of the input / output voltage of the loop filter is improved by controlling the signal connecting / disconnecting means so as not to be input to the input signal.

In order to solve such a problem, the present invention provides a voltage controlled oscillator in which an oscillation frequency is controlled based on a control voltage, and a frequency of an oscillation signal oscillated by the voltage controlled oscillator with a predetermined frequency division ratio. A frequency divider, a phase comparator that compares the phase of the output signal of the frequency divider with a phase of a reference frequency signal, and a loop filter that integrates the phase error detected by the phase comparator. In the PLL circuit which applies a control voltage based on the phase error integrated by the loop filter to the voltage controlled oscillator and controls the output frequency of the voltage controlled oscillator to synchronize the phase with the reference frequency signal. A signal connecting / disconnecting means for inputting or interrupting a phase error detected by a detector to the loop filter, a setting of a division ratio to the frequency divider, and a control of the signal connecting / disconnecting means. And when the plurality of voltage controlled oscillators having different oscillation frequencies are controlled by a common control voltage line, the control means moves the oscillation frequency of the voltage controlled oscillator. The phase error input to the loop filter is cut off and switched to a voltage controlled oscillator having a destination oscillation frequency during the cutoff, and the frequency division based on the switched oscillation frequency of the voltage controlled oscillator is performed. After the ratio is set in the frequency divider, the signal connecting / disconnecting means is controlled to input the phase error to the loop filter.
In the case of a circuit configuration in which a plurality of VCOs having different oscillation frequencies are controlled by a common CV line, the PLL circuit of the present invention is connected to a signal in order to prevent the CV line from being disturbed when switching to a VCO having a different frequency. The phase error output from the phase comparator is not input to the loop filter by the means, and after switching the VCO, the data of the free-running frequency of the switching destination VCO is received and the signal connecting / disconnecting means is controlled to perform the phase comparison The phase error output from the detector is input to the loop filter. As a result, the CV line rampage seen immediately after switching the VCO does not occur, so that the lockup time can be shortened accordingly.

According to a second aspect of the present invention, a voltage-controlled oscillator whose oscillation frequency is controlled based on a control voltage, a frequency divider that divides the frequency of an oscillation signal oscillated by the voltage-controlled oscillator by a predetermined frequency division ratio, A phase comparator that compares the phase of the output signal of the frequency divider with the phase of the reference frequency signal, and a loop filter that integrates the phase error detected by the phase comparator, and the phase error integrated by the loop filter A phase error detected by the phase comparator is applied to the loop filter in a PLL circuit which applies a control voltage based on the above to the voltage controlled oscillator and controls the output frequency of the voltage controlled oscillator to synchronize the phase with the reference frequency signal. And a signal connecting / disconnecting means for inputting or interrupting to the frequency divider, and a control means for setting a frequency dividing ratio to the frequency divider and controlling the signal connecting / disconnecting means. When the plurality of voltage controlled oscillators are controlled by a common control voltage line, the control means controls the signal disconnecting means when moving the oscillation frequency of the voltage controlled oscillator to control the loop of the phase error. The input to the filter is cut off, and the frequency division ratio based on the oscillation frequency of the destination voltage controlled oscillator is set in the frequency divider during the cutoff and the voltage controlled oscillator having the destination oscillation frequency is switched. After that, the signal connection / disconnection means is controlled to input the phase error to the loop filter.
In the case of a circuit configuration in which a plurality of VCOs having different oscillation frequencies are controlled by a common CV line, the PLL circuit of the present invention prevents the CV line from being ramped when setting the frequency of the destination VCO. It is the same as in the first aspect until the phase error output from the phase comparator by the signal connecting / disconnecting means is not input to the loop filter, but after receiving the free-running frequency data of the VCO to be switched to, the VCO The place to switch is different. The signal connecting / disconnecting means is controlled to input the phase error output from the phase comparator to the loop filter. As a result, the CV line rampage seen immediately after setting the frequency of the destination VCO does not occur, so that the lockup time can be shortened accordingly.

According to a third aspect of the present invention, the signal connecting / disconnecting means is realized by controlling a charge pump for amplifying a phase error detected by the phase comparator by starting and releasing a power down mode.
The present invention utilizes the function of a charge pump in a PLL circuit as signal connection / disconnection means. In other words, since the charge pump can operate or stop its function in the power down mode, the phase error output from the phase comparator can be easily input to the next-stage loop filter or controlled. be able to.
A fourth aspect of the present invention is the PLL circuit according to the first or second aspect, wherein the signal connection / disconnection means is a junction field effect transistor.
The junction field effect transistor can electrically connect the source electrode and the drain electrode by applying a predetermined level of voltage to the gate terminal. Therefore, by connecting the phase error, which is the output of the phase comparator, to the drain electrode and connecting the loop filter to the source electrode, it is possible to arbitrarily input or block the phase error to the loop filter.

According to the first aspect of the present invention, the phase error output from the phase comparator is not input to the loop filter by the signal connecting / disconnecting means, and after switching the VCO, the data of the free-running frequency of the switching destination VCO is received. In addition, since the phase error output from the phase comparator is input to the loop filter by controlling the signal connecting / disconnecting means, the CV line rampage that occurs immediately after switching the VCO does not occur, and the lock-up time is increased accordingly. Can be fast.
According to the second aspect of the present invention, the phase error output from the phase comparator by the signal connecting / disconnecting means is not input to the loop filter, and after the data of the free-running frequency of the switching destination VCO is received, the VCO is switched and the signal disconnection is performed. Since the phase error output from the phase comparator is input to the loop filter by controlling the contact means, the CV line rampage that occurs immediately after setting the destination VCO frequency does not occur, and the lockup time is increased accordingly. Can be made faster.
Further, in claim 3, since the function of the charge pump in the PLL circuit is used as the signal connection / disconnection means, the phase output from the phase comparator can be easily output by operating or stopping the function in the power down mode. The error can be input to the next-stage loop filter, blocked or controlled, and the same effect as in the first aspect can be achieved.
Further, in the fourth aspect, since the junction field effect transistor is used as the signal connection / disconnection means, the input impedance becomes very large, and the same effect as in the first aspect can be obtained by simpler control.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. .
FIG. 1 is a functional block diagram of a PLL circuit according to an embodiment of the present invention. The PLL circuit 100 includes a reference frequency signal generator 1 that generates a reference frequency signal F, a phase comparator 2 that compares the signal divided by the frequency divider 9 with the phase of the reference frequency signal F, and the phase A signal connection / disconnection means 3 for inputting or blocking the phase error ε detected by the comparator 2 to the loop filter 4, a loop filter 4 for integrating the phase error ε compared by the phase comparator 2, and a control voltage VCO (Voltage Controlled Oscillator) -A5, VCO (Voltage Controlled Oscillator) -B6 in which the oscillation frequency f is controlled based on v, setting of the frequency division ratio to the frequency divider 9 and control of the signal connection / disconnection means 3 And a frequency divider 9 that divides the frequency f of the oscillation signal oscillated by the VCOAs 5 and B6 by a predetermined frequency division ratio.
In this embodiment, the frequency switching SW 7 for switching the oscillation frequency from the outside is connected to the CPU 8, and the VCO switching SW 15 is controlled by the signal line 13 from the output port to select one of the VCOAs 5 and B6. ing. The CV line 14 of the loop filter 4 is commonly connected to the input terminals of the VCOAs 5 and B6 and is controlled by the same control voltage v.

  Next, the operation of the PLL circuit 100 of this embodiment will be described. FIG. 2 is a schematic diagram for explaining the frequency shift of the wireless device of the present invention. For example, there are two VCOs as in the PLL circuit 100 of FIG. The free-running frequency ranges of each VCO are f1 to f2 for VCO-A5, f3 to f4 for VCO2-B6, and each frequency is f1 <f2 <f3 <f4. Then, consider the operation when the VCO-A5 is switched from the state in which the VCO-A5 is locked to the phase difference within a certain range at the oscillation frequency f1 in advance to f4. The pattern 1 is as shown in the flowchart of FIG. That is, when the CPU 8 receives an instruction to switch to the frequency f4 by the frequency switching SW 7, the CPU 8 outputs a signal disconnection a to the signal connection / disconnection means 3 via the signal line 10. Thereby, the signal connecting / disconnecting means 3 prevents the phase error ε of the phase comparator 2 from being input to the loop filter 4 (S1). Next, in this state, a signal b for switching from VCO-A5 having a free-running frequency of f1 to VCO2-B6 having a free-running frequency of f4 is output (S2). Next, the CPU 8 sets a frequency division ratio based on the frequency of f4 in the frequency divider 9 (S3). Next, the CPU 8 outputs a signal contact d to the signal connection / disconnection means 3. Thereby, the signal connection / disconnection means 3 inputs the phase error ε of the phase comparator 2 to the loop filter 4 (S4). As a result, the PLL circuit 100 starts to operate at the frequency of f4 (S5), and as a result, the CV line 14 converges to attain the frequency of f4 (S6).

FIG. 4 is a timing chart at the time of frequency shift based on the flowchart of FIG. The operation of the PLL 100, VCO-A and B switching signals, the movement of the CV line, and the operation of the signal connection / disconnection means 3 are shown from above. First, when a frequency shift instruction is received, a signal disconnection a is output to the signal connecting / disconnecting means 3. Thereby, the signal connection / disconnection means 3 prevents the output of the phase comparator 2 from being input to the loop filter 4 (operation of S1). Next, when the CPU 8 outputs a signal for switching from VCO-A5 to VCO-B6, the switching signal for VCO-A5 and VCO-B6 is switched to the VCO-B6 side (operation of S2). However, since the data of f4 has not been received yet, the CV line 14 tries to keep the voltage 1V locked to f1. That is, it is around the position of f3 in FIG. However, since the data is still f1, the CV line 14 tries to become f1 having a frequency lower than f3, but the signal connection / disconnection means 3 prevents the output of the phase comparator 2 from being input to the loop filter 4. It does not drop to Vmin and is stable at 1v. Thereafter, the data of f4 is received (operation of S3), and immediately after that, the signal connection / disconnection means 3 inputs the output of the phase comparator 2 to the loop filter 4 (operation of S4). As a result, the PLL circuit operates to achieve the frequency of f4 (operation of S5), and the CV line 14 converges to 10V to achieve the frequency of f4 (operation of S6).
As described above, the PLL circuit 100 according to this embodiment has a CV generated when switching to a VCO having a different frequency in the case of a circuit configuration in which a plurality of VCO-A5 and VCO-B6 having different oscillation frequencies are controlled by the common CV line 14. In order to prevent the fluctuation of the line 14, the phase error ε output from the phase comparator 2 by the signal connection / disconnection means 3 is not input to the loop filter 4, and the switching is performed after switching from VCO-A 5 to VCO-B 6. The free-running frequency data of the previous VCO-B 6 is received, the signal connection / disconnection means 3 is controlled, and the phase error ε output from the phase comparator 2 is input to the loop filter 4. As a result, the CV line rampage seen immediately after switching the VCO does not occur, so that the lockup time can be shortened accordingly.

  FIG. 5 is a flowchart for pattern 2. That is, when the CPU 8 receives an instruction to switch to the frequency f4 by the frequency switching SW 7, the CPU 8 outputs a signal disconnection a to the signal connection / disconnection means 3. As a result, the signal connecting / disconnecting means 3 does not input the phase error ε of the phase comparator 2 to the loop filter 4 (S11). Next, the CPU 8 sets a frequency division ratio based on the frequency of f4 in the frequency divider 9 (S12). Next, a signal c for switching from VCO-A5 having a free-running frequency of f1 to VCO2-B6 having a free-running frequency of f4 is output (S13). Next, the CPU 8 outputs a signal contact d to the signal connection / disconnection means 3. Thereby, the signal connection / disconnection means 3 inputs the phase error ε of the phase comparator 2 to the loop filter 4 (S14). As a result, the PLL circuit 100 starts to operate at the frequency of f4 (S15), and as a result, the CV line 14 converges to attain the frequency of f4 (S16).

FIG. 6 is a timing chart at the time of frequency shift based on the flowchart of FIG. The operation of the PLL 100, VCO-A and B switching signals, the movement of the CV line, and the operation of the signal connection / disconnection means 3 are shown from above. First, upon receiving a frequency shift instruction, a signal disconnection a is output to the signal connecting / disconnecting means 3. Thereby, the signal connection / disconnection means 3 prevents the output of the phase comparator 2 from being input to the loop filter 4 (operation of S11). In this pattern, since the PLL 100 first receives the data of f4 (operation of S12), the CV line tries to move to around 10V (that is, tries to reach the position of f2 in FIG. 2). 3 prevents the output of the phase comparator 2 from being input to the loop filter 4, so that it does not rise to Vmax and is stable at 1v. Next, when the CPU 8 outputs a signal for switching from VCO-A5 to VCO-B6, the switching signal for VCO-A, B is switched to the VCO-B6 side (operation in S13). Immediately after that, the signal connection / disconnection means 3 inputs the output of the phase comparator 2 to the loop filter 4 (operation of S14). At that time, since the data of f4 has already been received, the PLL circuit operates so as to reach the frequency of f4 (operation of S15), and the CV line 14 converges to 10V while attempting to reach the frequency of f4 (operation of S16). ).
As described above, the PLL circuit 100 of the present embodiment sets the frequency of the destination VCO-B6 in the case of a circuit configuration in which a plurality of VCO-A5 and VCO-B6 having different oscillation frequencies are controlled by the common CV line 14. In order to prevent the CV line from being disturbed at this time, the signal connection / disconnection means 3 is the same as the pattern 1 until the phase error ε output from the phase comparator 2 is not input to the loop filter 4. After the data of the free-running frequency of the switching destination VCO-B6 is received, the switching from VCO-A5 to VCO-B6 is different. Then, the signal connection / disconnection means 3 is controlled, and the phase error ε output from the phase comparator 2 is input to the loop filter 4. As a result, the CV line rampage that occurs immediately after setting the frequency of the destination VCO-B6 does not occur, and the lockup time can be shortened accordingly.

  FIG. 7 is a diagram for comparing the difference between the movement of the CV line according to the conventional method and the movement of the CV line according to the present invention. Reference numeral 20 indicates the movement of the CV line in the case of pattern 2 when the frequency is moved from f1 to f4, reference numeral 21 is the movement of the CV line of the present invention, and reference numeral 22 indicates the case where the frequency is moved from f1 to f4. This is the movement of the CV line in the case of pattern 1. As is apparent from this figure, between the time t2 (Q point) until the conventional codes 20 and 22 converge to 10V and the time t1 (P point) at which the code 21 of the present invention converges, t1 < There is a relationship of t2, and it can be seen that in the method of the present invention, the CV line is not disturbed and the time for convergence to 10 V is short. As a result, the response delay of the input / output voltage of the loop filter can be improved. Here, t0 is the time when each waveform starts to converge to 10V.

FIG. 8 is a diagram showing an embodiment of the signal connection / disconnection means 3 of the present invention. FIG. 8A is realized by controlling the charge pump 26 that amplifies the current of the phase error ε detected by the phase comparator 25 as signal connecting / disconnecting means by starting and canceling the power down mode signal 27. In this circuit, the phase error ε detected by the phase comparator 25 is input to the charge pump 26 at the start of the power down mode signal 27 to amplify the current and output it to a loop filter (not shown). Further, by canceling the power-down mode signal 27, the phase error ε detected by the phase comparator 25 is blocked by the charge pump 26 so that it is not output to a loop filter (not shown).
As described above, the present embodiment uses the function of the charge pump in the PLL circuit as the signal connection / disconnection means. That is, since the charge pump 26 can operate or stop its function in the power down mode, the phase error ε output from the phase comparator 2 can be easily input to the next loop filter 4 or shut off. Can be controlled.
FIG. 8B is realized by controlling the signal connection / disconnection means 3 by a junction field effect transistor (J-FET). In this signal connection / disconnection means, the drain electrode (D) and the source electrode (S) of the J-FET 31 are connected between the phase comparator 2 and the loop filter 4. A resistor R is connected between the drain electrode (D) and the gate electrode (G), and the gate electrode (G) and the control signal 30 are connected via the diode D. Although the J-FET 31 is used in FIG. 8B, the phase comparator 2 and the loop filter 4 may be connected by a mechanical contact such as a relay. That is, the J-FET 31 is merely an example, and even if it is realized by other electronic means, it does not depart from the present invention.
In this way, the J-FET 31 can electrically connect the source electrode and the drain electrode by applying a predetermined level of voltage to the gate terminal. Therefore, the phase error ε, which is the output of the phase comparator 2, is connected to the drain electrode, and the loop filter 4 is connected to the source electrode, so that the phase error ε can be arbitrarily input to or blocked from the loop filter 4. Can do.
In the above description, the case where there are two VCOs has been described, but a larger number may be used.

It is a functional block diagram of a PLL circuit according to an embodiment of the present invention. It is a schematic diagram explaining the frequency shift of the radio | wireless machine of this invention. It is an operation | movement flowchart of the pattern 1 of this invention. It is a timing chart at the time of the frequency shift based on the flowchart of FIG. It is an operation | movement flowchart of the pattern 2 of this invention. It is a timing chart at the time of the frequency shift based on the flowchart of FIG. It is a figure which compares the motion of the CV line by a conventional system, and the motion of the CV line by this invention. It is a figure which shows the Example of the signal connection / disconnection means 3 of this invention. It is a schematic diagram explaining the frequency shift of the conventional radio | wireless machine. It is an operation | movement flowchart of the conventional pattern 1. FIG. It is a timing chart at the time of the frequency movement based on the flowchart of FIG. It is an operation | movement flowchart of the conventional pattern 2. FIG. It is a timing chart at the time of the frequency movement based on the flowchart of FIG.

Explanation of symbols

  1 reference frequency signal generator, 2 phase comparator, 3 signal connection / disconnection means, 4 loop filter, 5 VCO-A, 6 VCO-B, 7 frequency switching SW, 8 CPU, 9 frequency divider, 100 PLL circuit, v Control voltage, f frequency of oscillation signal, F reference frequency signal, ε phase error

Claims (4)

A voltage-controlled oscillator whose oscillation frequency is controlled based on a control voltage; a frequency divider that divides the frequency of an oscillation signal oscillated by the voltage-controlled oscillator by a predetermined frequency division ratio; and an output signal of the frequency divider A phase comparator that compares the phase of the reference frequency signal with the phase of the reference frequency signal, and a loop filter that integrates the phase error detected by the phase comparator, and a control voltage based on the phase error integrated by the loop filter is provided. In a PLL circuit that is applied to the voltage controlled oscillator and controls the output frequency of the voltage controlled oscillator to be phase-synchronized with the reference frequency signal.
A signal connecting / disconnecting means for inputting or blocking the phase error detected by the phase comparator to the loop filter; a control means for setting a frequency division ratio to the frequency divider and controlling the signal connecting / disconnecting means; With
When controlling a plurality of voltage controlled oscillators having different oscillation frequencies by a common control voltage line,
The control means, when moving the oscillation frequency of the voltage controlled oscillator, controls the signal connection / disconnection means to cut off the input of the phase error to the loop filter, and sets the oscillation frequency of the movement destination during the interruption. Switch to the voltage controlled oscillator provided, and after setting the frequency dividing ratio based on the oscillation frequency of the switched voltage controlled oscillator in the frequency divider, control the signal connecting / disconnecting means and input the phase error to the loop filter A PLL circuit characterized by: A voltage-controlled oscillator whose oscillation frequency is controlled based on a control voltage; a frequency divider that divides the frequency of an oscillation signal oscillated by the voltage-controlled oscillator by a predetermined frequency division ratio; and an output signal of the frequency divider A phase comparator that compares the phase of the reference frequency signal with the phase of the reference frequency signal, and a loop filter that integrates the phase error detected by the phase comparator, and a control voltage based on the phase error integrated by the loop filter is provided. In a PLL circuit that is applied to the voltage controlled oscillator and controls the output frequency of the voltage controlled oscillator to be phase-synchronized with the reference frequency signal.
A signal connecting / disconnecting means for inputting or blocking the phase error detected by the phase comparator to the loop filter; a control means for setting a frequency division ratio to the frequency divider and controlling the signal connecting / disconnecting means; With
When controlling a plurality of voltage controlled oscillators having different oscillation frequencies by a common control voltage line,
When the control means moves the oscillation frequency of the voltage controlled oscillator, the control means controls the signal connecting / disconnecting means to cut off the input of the phase error to the loop filter, and the destination voltage controlled oscillator during the cut-off A frequency division ratio based on the oscillation frequency of the first frequency is set in the frequency divider, and after switching to a voltage controlled oscillator having a destination oscillation frequency, the signal disconnection means is controlled to control the phase error to the loop. A PLL circuit characterized by being input to a filter.   3. The signal connecting / disconnecting means is realized by controlling a charge pump that amplifies a phase error detected by the phase comparator by starting and releasing a power-down mode. PLL circuit.   3. The PLL circuit according to claim 1, wherein the signal connecting / disconnecting means is a junction field effect transistor.

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