JP2007013898A - Pll frequency synthesizer, integrated circuit and communication apparatus using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve miniaturization of a PLL frequency synthesizer. <P>SOLUTION: A PLL frequency synthesizer of the present invention comprises a voltage controlled oscillator, a frequency divider, a phase comparator, and a low-pass filter. In such a PLL frequency synthesizer, a lock detector is further provided, a reference voltage selector circuit outputs a lock detecting signal, a control voltage, a reference voltage, and a switching signal, and the voltage controlled oscillator determines upper and lower limit values of a variable range of an outputted oscillation frequency, and a central frequency that is a central value of the oscillation frequency variable range, based on the reference voltage, the switching signal and the control voltage from the low-pass filter. Thus, a wide variable range and a narrow variable range of the oscillation frequency are switched by sharing the same circuit, and since the central frequency of the oscillation frequency variable range is changed by voltage control, an installation area is reduced in comparison with a case where a plurality of circuits of the same type are configured. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a PLL frequency synthesizer configured to control a voltage controlled oscillator, an integrated circuit using the same, and a communication apparatus.

  Conventionally, a PLL (phase locked loop) frequency synthesizer has been widely used as a local oscillation source in wireless communication devices such as cellular mobile wireless telephones, cordless telephones, wireless data terminals, and tuners such as satellite broadcast tuners and cable TV tuners. It is used. The PLL frequency synthesizer is a circuit that oscillates an accurate frequency and generates signals of a plurality of frequencies having different frequencies by equal intervals.

  FIG. 5 shows a general PLL frequency synthesizer, which is cited from FIG.

  As a general component constituting the PLL frequency synthesizer, as shown in FIG. 5, a reference signal oscillator 11 that outputs a reference signal, and a phase comparison that compares the phases of the reference signal and the output signal from the frequency divider 15 12, a loop filter (low-pass filter) 13 that smoothes the output signal from the phase comparator 12 and outputs a control voltage to the voltage-controlled oscillator 14, a voltage-controlled oscillator 14 whose oscillation frequency changes according to the input voltage, and a voltage-controlled oscillator The frequency divider 15 that divides the output signal from 14 to an arbitrary frequency division ratio based on an external control signal, whether the PLL frequency synthesizer is in a locked state, whether the phase of the phase comparator 12 is aligned A lock detection circuit 16 that determines whether or not, a conversion gain switching signal 17 that is output to the voltage controlled oscillator 14, a CPU 18 that sets division ratio data, and the like.

  The phase comparator 12 includes a charge pump circuit (not shown) for outputting the phase difference from the input signal through the loop filter 13 in the form of voltage.

  FIG. 6 shows an oscillation circuit of a voltage-controlled oscillator of a general PLL frequency synthesizer, and FIG. 18 of Patent Document 2 is cited.

  As shown in FIG. 6, the oscillation circuit of the voltage controlled oscillator has an oscillation frequency determined by a resonance circuit mainly composed of inductors La and Lb and variable capacitance elements VCa1 to VCa3 and VCb1 to VCb3. By changing the capacitance value of the variable capacitance element, the oscillation frequency of the resonance circuit can be changed.

  The voltage controlled oscillator is an important circuit that determines the oscillation frequency, but its phase noise greatly affects the accuracy of the PLL frequency synthesizer and further affects the modulation accuracy of the transmission / reception system. The phase noise shows a better value when the sensitivity of the voltage controlled oscillator is lower. This is because if the sensitivity of the voltage controlled oscillator is high, phase noise increases due to disturbance entering the control voltage line. The sensitivity of the voltage controlled oscillator is the change rate of the oscillation frequency with respect to the change of the control voltage.

  When a voltage controlled oscillator with a wide frequency variable range is required, a variable capacitance element having a large capacitance change may be used. Alternatively, a plurality of variable capacitance elements may be used in parallel connection. However, if the frequency variable range is widened, the sensitivity of the voltage controlled oscillator is also increased, which contributes to the deterioration of the phase noise characteristics.

In order to reduce phase noise, a technique is known in which a plurality of voltage-controlled oscillators having a narrow frequency variable range are made to cover a desired frequency variable range with low phase noise (for example, Patent Document 2).
Japanese Patent Laid-Open No. 9-326693 (released on December 16, 1997) JP 2003-110425 A (published on April 11, 2003) JP 2003-198364 A (published July 11, 2003)

However, the conventional configuration requires a plurality of voltage controlled oscillators in accordance with the necessary frequency variable range, which causes a problem that the area occupied by the voltage controlled oscillator on the circuit increases.
Specifically, it is necessary to prepare a plurality of voltage controlled oscillators that satisfy a desired frequency variable range and are within practical phase noise to satisfy a necessary frequency variable range. For this reason, when using a voltage controlled oscillator having a narrow frequency variable range with good phase noise characteristics, a large number of voltage controlled oscillators are required to satisfy the desired frequency variable range.
The present invention has been made in view of the above problems, and an object of the present invention is to provide a PLL frequency synthesizer capable of reducing the circuit scale of a voltage controlled oscillator while suppressing phase noise, an integrated circuit including the PLL frequency synthesizer, and It is to realize a communication device.

  The PLL frequency synthesizer of the present invention includes a voltage controlled oscillator whose oscillation frequency changes according to a control voltage, a frequency divider that divides an output signal from the voltage controlled oscillator into an arbitrary frequency dividing ratio based on an external control signal, A phase comparator for comparing the phase of a reference signal having a reference frequency with an output signal from the frequency divider, and a low-pass filter for smoothing the output signal from the phase comparator and outputting the control voltage to the voltage controlled oscillator The PLL frequency synthesizer further includes a lock detector and a reference voltage selection circuit, and the lock detector detects that the PLL frequency synthesizer is locked based on a comparison result of the phase comparator. The reference voltage selection circuit outputs the lock signal and the low-pass filter output from the lock detector. A switching signal for switching a connection state of an oscillation circuit that oscillates at an oscillation frequency according to the applied control voltage of the voltage-controlled oscillator based on the control voltage output from the data, and a variable oscillation frequency In order to determine a reference point, a reference voltage applied to a predetermined point of the oscillation circuit is generated and output to the voltage controlled oscillator, and the voltage controlled oscillator switches between the reference voltage from the reference voltage selection circuit and the switching The oscillation frequency variable range of the oscillation circuit is determined based on the signal.

  According to the above configuration, by switching between a wide variable range of the oscillation frequency and a narrow variable range based on the switching signal and the reference voltage, a single voltage-controlled oscillator can be used to lock the wide oscillation frequency variable range. Thus, it is possible to realize oscillation with less phase noise in a narrow oscillation frequency variable range. Since the above-mentioned characteristics can be provided by a single voltage controlled oscillator, it is possible to realize a PLL frequency synthesizer with a small installation area compared to the case where a plurality of the same type of circuits are configured while suppressing phase noise. .

  In the PLL frequency synthesizer of the present invention, when the lock detector detects that the PLL frequency synthesizer is unlocked, it outputs an unlock signal, and the reference voltage selection circuit oscillates a voltage controlled oscillator. In an initial state of starting, the initial reference voltage is output as the reference voltage and the initial switching signal is output as the switching signal based on the unlock signal, and the voltage-controlled oscillator outputs the initial reference voltage and the initial switching signal. It is preferable that the oscillation frequency variable range is an initial oscillation frequency variable range which is a maximum variable range based on a signal.

  According to the above configuration, since the oscillation frequency variable range is the maximum, it is possible to oscillate in a wide variable range, and it is possible to shorten the time required for locking rather than performing oscillation in a narrow variable range. There is a further effect.

In the PLL frequency synthesizer of the present invention, the reference voltage selection circuit may further change the oscillation frequency variable range narrower than the initial oscillation frequency variable range when the lock signal is input from the lock detector. It is preferable to output the reference voltage and the switching signal for setting the range of the variable frequency at the time of lock.
According to the above configuration, it is possible to perform oscillation with less phase noise by switching to a circuit connection state having a narrower frequency variable range including a target frequency based on detection of a locked state. There is a further effect.

In the PLL frequency synthesizer of the present invention, it is preferable that the initial oscillation frequency variable range includes all the frequency ranges that can be taken by each of the lockable frequency variable ranges.
According to the above configuration, since the initial oscillation frequency variable range includes all of the lockable frequency variable ranges, it is possible to reliably obtain all of the target frequencies within the lockable frequency variable range. Play.

  In the PLL frequency synthesizer of the present invention, when the unlock signal is output from the lock detector when the reference voltage selection circuit is not in a state of outputting the initial reference voltage, the initial reference voltage and Preferably, the initial switching signal is output, and the voltage-controlled oscillator sets the oscillation frequency variable range to the initial oscillation frequency variable range based on the initial reference voltage and the initial switching signal.

  According to the above configuration, when the target frequency changes due to the change of the frequency division ratio, there is an additional effect that the frequency can be changed to another narrow frequency variable range including the target frequency.

  Further, by configuring the PLL frequency synthesizer with an integrated circuit, it is possible to reduce the size of the integrated circuit. Further, the communication device is configured using the integrated circuit, so that the communication device can be downsized.

  Since the PLL frequency synthesizer of the present invention further includes a lock detector and a reference voltage selection circuit, the PLL frequency synthesizer can be switched between a wide variable range of the oscillation frequency and a narrow variable range based on the switching signal and the reference voltage. Using one voltage-controlled oscillator, it is possible to reduce the time required for locking in a wide oscillation frequency variable range, and to realize oscillation with less phase noise in a narrow oscillation frequency variable range. Since the above characteristics can be provided by a single voltage controlled oscillator, a PLL frequency synthesizer with a smaller installation area can be realized as compared with the case where a plurality of circuits of the same type are configured.

One embodiment of the present invention will be described below with reference to FIGS.
FIG. 1 shows an embodiment of the present invention, and is a block diagram showing a main configuration of a PLL frequency synthesizer of the present invention.

  As shown in FIG. 1, a PLL frequency synthesizer 10 of the present invention includes a reference signal oscillator 11, a phase comparator 12, a low-pass filter 13, a voltage control oscillator 14, a frequency divider 15, a lock detector 16, a CPU 18, and a reference voltage. A selection circuit 19 is included.

  The reference signal oscillator 11 outputs a reference signal 23 having a reference frequency to the phase comparator 12.

The phase comparator 12 compares the phases of the reference signal 22 and the signal output from the frequency divider 15 to detect a phase difference and outputs the phase difference to the low-pass filter 13 as a voltage.
The low-pass filter 13 is for averaging the DC signal including the ripple from the phase comparator 12 and converting it to a clean DC signal with few AC components. The voltage-controlled oscillator 11, the phase comparator 12, the low-pass filter 13, and the frequency divider 15 are for determining transfer characteristics for stably performing PLL loop control.
The voltage controlled oscillator 14 is a variable frequency oscillator whose oscillation frequency can be controlled by the control voltage 21.

  The frequency divider 15 divides the output signal from the voltage controlled oscillator 14 to an arbitrary frequency division ratio based on the external control signal 24.

  The lock detector 16 detects whether the PLL frequency synthesizer 10 is locked or unlocked based on the comparison result of the phase comparator 12, and includes a lock signal and an unlock signal. This is for outputting the detection signal 22. If it is locked, the lock detection signal 22 becomes a lock signal, and if it is unlocked, the lock detection signal becomes an unlock signal.

  The CPU 18 is for giving an external control signal 24 to the frequency divider 15 to determine the frequency division ratio.

  The reference voltage selection circuit 19 is for outputting the switching signal 17 and the reference voltage 20 based on the control voltage 21 from the low-pass filter 13 and the lock detection signal 22 from the lock detection circuit 16.

  Next, the operation of the PLL frequency synthesizer 10 in this embodiment will be described.

  The reference signal 23 generated by the reference signal oscillator 11 is input to the phase comparator 12. The phase comparator 12 compares the phase difference between the signal input from the frequency divider 15 and the reference signal 23 and outputs a phase difference signal to the low-pass filter 13. The low-pass filter 23 smoothes the signal output from the phase comparator 12 and outputs the smoothed signal to the voltage controlled oscillator 14 as the control voltage 21.

  The voltage controlled oscillator 14 oscillates based on the input control voltage 21 and outputs it to the frequency divider 15 and the output terminal. The frequency divider 15 determines the frequency division ratio based on the external control signal 24 output by the CPU 18. The frequency divider 15 divides the output from the voltage controlled oscillator 14 at an arbitrary frequency dividing ratio and feeds it back to the phase comparator 12.

A new signal having an oscillation frequency synchronized with the reference signal 23 is generated by the above loop.
In the above flow, the lock detector 16 measures the transition of the comparison result of the phase comparator 12, detects the lock state of the oscillation frequency, and outputs the lock detection signal 22 to the reference voltage selection circuit 19. The reference voltage selection circuit 19 receives the control voltage 21 and the lock detection signal 22, and outputs the switching signal 17 and the reference voltage 20 based on the detection timing of the lock state and the lock state and the control voltage 21. Here, there are two lock states: a locked state and an unlocked state.

Next, the relationship between the control signal 21 and the switching signal 17 and the reference voltage 20 output from the reference voltage selection circuit 19 in this embodiment will be described with reference to FIGS.
FIG. 2 shows an embodiment of the present invention and is a graph showing the relationship between the control voltage 21 and the oscillation frequency f at each reference voltage 20 of the voltage controlled oscillator 14 of the present invention.
A graph 26 is a graph showing the relationship between the control voltage 21 of the voltage controlled oscillator 14 and the oscillation frequency f.

A curve 27 shows a wide range of the initial oscillation frequency variable range fb0 determined by the switching signal 17 and the value V _sel of the reference voltage 20.

  A curve 28 shows the narrow lock frequency variable range fb1 used when the locked state is detected.

  A curve 29 shows a narrow oscillation frequency variable range fb2 at the time of lock used when a locked state is detected.

  The curve 27 has the maximum frequency variable range among all the curves. The lockable oscillation frequency variable range fb1 is a range having a higher center frequency than the lockable oscillation frequency variable range fb2. The locked oscillation frequency variable range fb1 preferably overlaps with the locked oscillation frequency variable range fb2 to some extent.

  FIG. 3 shows an embodiment of the present invention and is a circuit diagram showing an oscillation circuit 30 which is a main configuration of the voltage controlled oscillator 14 of the present invention.

  The oscillation circuit 30 includes a passive part 31 and an active part 32.

Passive unit 31 includes an inductor L1 · L2, a variable capacitance element Cv11 · Cv12 · Cv21 · Cv22 · Cv31 · Cv32, switch SW _1, a control voltage input terminal 33, the switching signal input terminal 34, and includes a reference voltage input terminal 35 Yes.

  The inductor L1 is connected between the power supply Vcc and one connection point d to the active part 32 of the passive part 31.

  The inductor L2 is connected between the power source Vcc and the other connection point e to the active part of the passive part 31.

  One end of the variable capacitance element Cv11 is connected to one end of the inductor L1 on the connection point d side.

  One end of the variable capacitance element Cv12 is connected to one end of the inductor L2 on the connection point e side.

  The other end of the variable capacitance element Cv11 and the other end of the variable capacitance element Cv12 are connected to each other, and this point is defined as a connection point a. Here, the variable capacitance elements Cv11 and Cv12 are variable capacitance diodes, and the connection point a side is a cathode.

  One end of the variable capacitance element Cv21 is connected to one end of the inductor L1 on the connection point d side.

  One end of the variable capacitance element Cv22 is connected to one end of the inductor L2 on the connection point e side.

  The other end of the variable capacitor Cv21 and the other end of the variable capacitor Cv22 are connected to each other, and this point is defined as a connection point b. Here, the variable capacitance elements Cv21 and Cv22 are variable capacitance diodes, and the connection point b side is a cathode.

  One end of the variable capacitance element Cv31 is connected to one end of the inductor L1 on the connection point d side.

  One end of the variable capacitance element Cv32 is connected to one end of the inductor L2 on the connection point e side.

  The other end of the variable capacitance element Cv31 and the other end of the variable capacitance element Cv32 are connected to each other, and this point is defined as a connection point c. Here, the variable capacitance elements Cv31 and Cv32 are variable capacitance diodes, and the connection point c side is a cathode.

  A connection point a between the variable capacitance element Cv11 and the variable capacitance element Cv12 and a connection point b between the variable capacitance element Cv21 and the variable capacitance element Cv22 are connected via the switch SW1.

The control voltage input terminal 33 is connected between the connection point a and the switch SW1 and receives the control voltage V _con .

The switching signal input terminal 34 is a terminal for controlling ON / OFF switching of the switch SW1, and the switching signal 17 is input thereto. By switching the ON / OFF of the switch SW _1, it switches the connection state of the oscillation circuit 30.

  The reference voltage input terminal 35 is connected to a connection point c between the variable capacitance element Cv31 and the variable capacitance element Cv32, and receives the reference voltage 20.

  The active part 32 includes fixed capacitance elements C11, C12, C21, and C22, resistors RB1 and RB2, transistors Q1 and Q2, and a direct current source I1. The active part 32 serves as a negative resistance circuit to supply power to the passive part 31 and maintain oscillation.

The transistors Q1 and Q2 are NPN type.
The fixed capacitance element C11 is connected between the base of the transistor Q1 and the connection point e to the collector of the transistor Q2 and the passive unit 31.

  The fixed capacitance element C12 is connected between the base of the transistor Q2 and the connection point d to the collector of the transistor Q1 and the passive part 31.

  The fixed capacitor C21 is connected between the base of the transistor Q1 and GND.

  The fixed capacitor C22 is connected between the base of the transistor Q2 and GND.

  The resistor RB1 is connected between the power supply Vo and the base of the transistor Q1.

  The resistor RB2 is connected between the power supply Vo and the base of the transistor Q2.

  The direct current source I1 is connected between the emitter of the transistor Q1 and the emitter of the transistor Q2 and GND.

As shown in FIG. 2, the voltage controlled oscillator 14 constitutes a circuit having a wide oscillation frequency variable range fb0 in the initial state of the PLL frequency synthesizer 10. Reference voltage selection circuit 19 outputs the signal S1 to instruct so as to turn ON the switch SW ₁ as the switching signal 17, and outputs an initial reference voltage _{V sel0} as the reference voltage _{V sel} as a reference voltage 20, a wide oscillation frequency An instruction is issued to configure a resonance circuit having a variable range fb0.

In the initial state, values given to the voltage controlled oscillator 14 are V _sel = V _sel0 , SW ₁ = ON, and V _con = V _con0 .

As shown in FIG. 3, a switching signal 17 for turning on the switch SW ₁ is input to the switching signal input terminal 34 in the initial state of the PLL frequency synthesizer 10. The initial reference voltage _Vsel0 is input to the reference voltage input terminal 35 in the initial state. With these inputs, a resonance circuit having an oscillation frequency / control voltage characteristic and a wide oscillation frequency variable range fb0 shown by the curve 27 in FIG. The initial reference voltage V _sel0 is a voltage that determines a variable reference point of the oscillation frequency in the oscillation frequency variable range fb0, and the oscillation frequency moves in the oscillation frequency variable range fb0 when the value V _con of the control voltage 21 changes.

When the locked state is detected by the lock detector 16 at the oscillation frequency f1, the reference voltage selection circuit 19 includes the resonance circuit of the oscillation circuit 30 and the voltage-controlled oscillator 14 includes the oscillation frequency f1 at the time of the lock. An instruction to switch to a circuit configuration having a narrow oscillation frequency variable range fb1 is given. That is, a switching signal for turning off the switch SW1 is input to the switching signal input terminal 34, and a value V that is a reference voltage 20 that sets the frequency variable range to the reference oscillation voltage variable range fb1 at the reference voltage input terminal 35. _sel1 is input.

fb1 is an oscillation frequency variable range that is narrower than the initial oscillation frequency variable range having the oscillation frequency f1 within the variable range and has excellent noise characteristics. The value V _sel1 of the reference voltage 20 is a voltage that determines the variable reference point of the oscillation frequency in the oscillation frequency variable range fb1, and the oscillation frequency moves in the oscillation frequency variable range fb1 by changing the value V _con of the control voltage 21. .

At this time, the oscillation frequency / control voltage characteristic is a curve 28. By changing the circuit configuration and the reference voltage 20, the oscillation frequency variable range fb is changed from the wide oscillation frequency variable range fb0 to the narrow oscillation frequency variable range fb1. Thus, the convergence value of the control voltage 21 corresponding to the oscillation frequency f1 is changed from _{V con1} to _V'con1. At this time, the locked state is maintained.

Circuitry by the switch SW ₁ is turned OFF is changed, the reference voltage 20 by which is changed, the oscillation frequency variable range fb is changed to a narrow oscillation frequency variable range fb1 of a wide oscillation frequency variable range fb0. As a result, a resonant circuit with good noise characteristics can be realized by a PLL frequency synthesizer having a narrow oscillation frequency variable range.

Next, when the lock is released when the frequency division ratio of the frequency divider 15 is changed by the external control signal 24, the lock detector 16 detects that the PLL frequency synthesizer 10 is unlocked, and the unlock signal is Is output. Thereby, the reference voltage selection circuit 19 gives an instruction to switch the resonance circuit of the oscillation circuit 30 to a circuit configuration having a wide oscillation frequency variable range fb0 to the voltage controlled oscillator. That is, the switching signal 17 for turning the switch SW1 from OFF to ON is input to the switching signal input terminal 34, and the initial value _Vsel0 is input to the reference voltage input terminal 35 as the reference voltage 20. The oscillation frequency / control voltage characteristic returns to the curve 27.

  When the switch SW1 is turned on to change the circuit configuration and the reference voltage 20 is changed, the oscillation frequency variable range fb is returned from the narrow oscillation frequency variable range fb1 to the wide oscillation frequency variable range fb0. This allows locking to different frequencies. At this time, a resonance circuit having a good lock time performance by a PLL frequency synthesizer having a wide oscillation frequency variable range is constructed again.

After that, when the lock detector 16 detects again the locked state at the frequency f2, the switching signal 17 is changed to the content of switching the switch from ON to OFF, and the reference voltage 20 is changed from the initial value _Vsel0. V _sel2 is changed. A switching signal 17 for turning the switch SW ₁ from ON to OFF is input to the switching signal input terminal 34. Similarly, a predetermined value V _sel2 is input to the reference voltage input terminal 35 as the reference voltage 20. The value V _sel2 of the reference voltage 20 is a voltage that determines the variable reference point of the oscillation frequency in the oscillation frequency variable range fb2, and the oscillation frequency moves in the oscillation frequency variable range fb2 by changing the value V _con of the control voltage 21. .

The oscillation frequency / control voltage characteristic at this time is a curve 29. By changing the circuit configuration and the reference voltage 20, the oscillation frequency variable range fb is changed from the wide oscillation frequency variable range fb0 to the narrow oscillation frequency variable range fb2. Thus, the convergence value of the control voltage 21 corresponding to the oscillation frequency f2 changes from _{V con2} to _V'con2. At this time, the locked state is maintained.

Circuitry by the switch SW ₁ is turned OFF is changed, the reference voltage 20 by which is changed, the oscillation frequency variable range fb is changed narrow oscillation frequency variable range fb2 from a wide oscillation frequency variable range fb0. As a result, a resonant circuit with good noise characteristics can be realized by a PLL frequency synthesizer having a narrow oscillation frequency variable range.

  fb2 is an oscillation frequency variable range having an oscillation frequency variable range different from fb1, which is narrower than the initial oscillation frequency variable range having the oscillation frequency f2 within the upper and lower limits of the variable range, and has excellent noise characteristics.

  As described above, by first changing the switching signal 17 and the reference voltage 20 based on the detection of the locked state and the unlocked state and the output reference voltage, a resonance circuit having the maximum frequency variable range is configured first. Then, by forming a resonance circuit having a narrower frequency variable range including the lock frequency and continuing the oscillation, it is possible to oscillate with small phase noise. Since the resonance circuit having the maximum frequency variable range is used first, the time required to lock to the target frequency is short. Since a single voltage-controlled oscillator can be used to provide the above characteristics, a PLL frequency synthesizer with good phase noise characteristics can be obtained with a small area on an integrated circuit.

  FIG. 4 shows an embodiment of the present invention, and is a block diagram showing a main part configuration of a communication apparatus using the PLL frequency synthesizer 10 of the present invention.

  The communication device 40 includes a switch 42, a reception amplifier 43, a mixer 44, a band pass filter 45, a demodulator 46, a voltage controlled oscillator 47, a PLL circuit 48, a mixer 49, a band pass filter 50, a modulator 51, and a power amplifier 52. It is out.

  The reception amplifier 43, the mixer 44, the band pass filter 45, the demodulator 46, the voltage controlled oscillator 47, the PLL circuit 48, the mixer 49, the band pass filter 50, and the modulator 51 are generally configured as one semiconductor chip as the integrated circuit 41. Formed on top.

  The switch 42 is connected between the antenna and the reception amplifier 43 and the power amplifier 52.

  A low noise amplifier (LNA) 43, a mixer 44, a band pass filter (BPF) 45, and a demodulator 46 are arranged in this order in the subsequent stage of the switch 42 to perform signal processing and constitute a receiving unit.

The power amplifier (PA) 43, the mixer 49, the band pass filter 50, and the modulator 51 are arranged in this order in the subsequent stage of the switch 42 to perform signal processing and constitute a transmission unit.
The PLL circuit 48 is connected to the voltage controlled oscillator 47 and outputs signals to the mixer 44 and the mixer 49.

  Next, the operation of the communication device 40 will be described.

  At the time of reception, a signal input from the antenna is amplified by the low noise amplifier 43, down-converted by the mixer 44, an unnecessary frequency is cut by the band pass filter 45, and sent to the demodulator 46.

  At the time of transmission, an unnecessary frequency is cut by the band-pass filter 50 after the transmission signal modulated by the modulator 51 is up-converted by the mixer 49, amplified by the power amplifier 52, and then output from the antenna.

  The voltage controlled oscillator 47 outputs local signals of the mixer 44 and the mixer 49. If the phase noise of the local signal output from the voltage controlled oscillator 47 is low, the transmission / reception characteristics of the high frequency transmitter / receiver are improved.

  By using the PLL frequency synthesizer of the present invention in the integrated circuit of the communication device, a single voltage controlled oscillator shortens the time required for locking in a wide oscillation frequency variable range, and oscillation with less phase noise in a narrow oscillation frequency variable range. Can be realized. Since the above characteristics can be provided by a single voltage-controlled oscillator, a PLL frequency synthesizer with good phase noise characteristics can be configured with a small area on the integrated circuit, and the integrated circuit and the communication device can be miniaturized. can do.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  The PLL frequency synthesizer of the present invention can switch between a wide variable range of the oscillation frequency and a narrow variable range by sharing the same circuit, and by changing the center frequency of the variable range of the oscillation frequency by voltage control, Since the installation area is smaller than in the case where a plurality of circuits are configured, the present invention can be suitably applied to applications such as communication devices such as mobile phones and integrated circuits used in tuners.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an embodiment of the present invention and is a block diagram illustrating a main configuration of a PLL frequency synthesizer according to the present invention. 4 is a graph showing an embodiment of the present invention and showing a relationship between a control voltage and an oscillation frequency at each reference voltage of the voltage controlled oscillator of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1, showing an embodiment of the present invention, is a circuit diagram illustrating a main configuration of a voltage controlled oscillator according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an embodiment of the present invention and is a block diagram illustrating a configuration of a main part of a communication device using a PLL frequency synthesizer of the present invention. It is a block diagram which shows a prior art and shows the principal part structure of a PLL frequency synthesizer. It is a circuit diagram which shows a prior art and shows the principal part structure of a voltage controlled oscillator.

Explanation of symbols

10 PLL frequency synthesizer (PLL frequency synthesizer)
11 Reference Signal Oscillator 12 Phase Comparator (Phase Comparator)
13 Low-pass filter (low-pass filter)
14 Voltage controlled oscillator (Voltage controlled oscillator)
15 divider (divider)
16 Lock detector (Lock detector)
17 Switching signal (switching signal)
18 CPU
19 Reference voltage selection circuit (reference voltage selection circuit)
20 Reference voltage (reference voltage)
21 Control voltage (control voltage)
22 Lock detection signal (Lock detection signal)
23 Reference signal (reference signal)
24 External control signal (external control signal)
26 Control Voltage / Oscillation Frequency Variable Range Corresponding Graph 27 Curve Showing Initial Oscillation Frequency Variable Range 28 Curve Showing Locking Oscillation Frequency Variable Range 1 29 Curve Showing Locking Oscillation Frequency Variable Range 2 30 Oscillation Circuit (Voltage Control Oscillator)
31 Passive part 32 Active part 33 Control voltage input terminal 34 Switching signal input terminal 35 Reference voltage input terminal 40 Communication device (communication device)
41 Integrated circuits (integrated circuits)
42 switch 43 low noise amplifier 44 mixer 45 band pass filter 46 demodulator 47 voltage controlled oscillator 48 PLL circuit 49 mixer 50 band pass filter 51 modulator 52 power amplifier

Claims (7)

A voltage-controlled oscillator whose oscillation frequency changes according to a control voltage; a frequency divider that divides an output signal from the voltage-controlled oscillator into an arbitrary division ratio based on an external control signal; a reference signal having a reference frequency; In a PLL frequency synthesizer comprising: a phase comparator that compares the phase of an output signal from a frequency divider; and a low-pass filter that smoothes the output signal from the phase comparator and outputs the control voltage to the voltage controlled oscillator.
A lock detector and a reference voltage selection circuit;
The lock detector detects that the PLL frequency synthesizer is locked from the comparison result of the phase comparator and outputs a lock signal,
The reference voltage selection circuit oscillates the voltage controlled oscillator according to the applied control voltage based on the lock signal output from the lock detector and the control voltage output from the low pass filter. A switching signal for switching a connection state of an oscillation circuit that oscillates at a frequency, and a reference voltage applied to a predetermined point of the oscillation circuit to determine a variable reference point of the oscillation frequency, and output to the voltage controlled oscillator And
The PLL frequency synthesizer, wherein the voltage controlled oscillator determines an oscillation frequency variable range of the oscillation circuit based on the reference voltage and the switching signal from the reference voltage selection circuit. When the lock detector detects that the PLL frequency synthesizer is unlocked, it outputs an unlock signal,
In the initial state, the reference voltage selection circuit outputs an initial reference voltage as the reference voltage and an initial switching signal as the switching signal based on the unlock signal, and the voltage controlled oscillator 2. The PLL frequency synthesizer according to claim 1, wherein the oscillation frequency variable range is set to an initial oscillation frequency variable range which is a maximum variable range based on the voltage and the initial switching signal.   The reference voltage selection circuit further sets the oscillation frequency variable range to a lock frequency variable range that is a variable range narrower than the initial oscillation frequency variable range when the lock signal is input from the lock detector. 3. The PLL frequency synthesizer according to claim 2, wherein the reference voltage and the switching signal for outputting are output.   4. The PLL frequency synthesizer according to claim 3, wherein the initial oscillation frequency variable range includes all of the frequency ranges that can be taken by each of the lockable frequency variable ranges.   The reference voltage selection circuit outputs the initial reference voltage and the initial switching signal when the unlock signal is output from the lock detector when the initial reference voltage is not being output. 5. The PLL according to claim 2, wherein the controlled oscillator sets the oscillation frequency variable range as the initial oscillation frequency variable range based on the initial reference voltage and the initial switching signal. Frequency synthesizer.   An integrated circuit comprising the PLL frequency synthesizer according to claim 1.   A communication apparatus using the integrated circuit according to claim 6.

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