JPH0661841A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

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Publication number
JPH0661841A
JPH0661841A JP4232836A JP23283692A JPH0661841A JP H0661841 A JPH0661841 A JP H0661841A JP 4232836 A JP4232836 A JP 4232836A JP 23283692 A JP23283692 A JP 23283692A JP H0661841 A JPH0661841 A JP H0661841A
Authority
JP
Japan
Prior art keywords
circuit
integrated circuit
power supply
supply voltage
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4232836A
Other languages
Japanese (ja)
Inventor
Kazuo Aoki
青木  一夫
Original Assignee
Mitsubishi Electric Corp
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp, 三菱電機株式会社 filed Critical Mitsubishi Electric Corp
Priority to JP4232836A priority Critical patent/JPH0661841A/en
Publication of JPH0661841A publication Critical patent/JPH0661841A/en
Pending legal-status Critical Current

Links

Abstract

(57) [Abstract] [Purpose] To realize a semiconductor integrated circuit in which the characteristics hardly change even when the power supply voltage is changed. [Structure] In order to specify and control the operation of these circuits, a second output circuit 12 that compensates for changes in the characteristics of the first output circuit 11 due to changes in the power supply voltage is created in advance in the circuit. The control signal input terminal 15 is provided, and the control signal input terminal 1 is provided in accordance with the power supply voltage using the integrated circuit.
By changing the logic level given to 5, the operation of the second output circuit 12 is controlled. [Effect] The integrated circuit maker does not need to develop the integrated circuit for each power supply voltage, and the user of the integrated circuit can easily design the system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit corresponding to a system capable of changing a power supply voltage such as 5V and 3V.

[0002]

2. Description of the Related Art FIG. 12 is a diagram showing an output portion of a very general CMOS semiconductor integrated circuit.
Is a package, 2 is an output terminal of the integrated circuit (external lead of the package), 3 and 4 are P-channel M constituting the output circuit
The OS output transistor and the N-channel MOS output transistor 5 are inputs to the output circuit. FIG. 13 shows FIG.
Output voltage (Vo) showing the electrical characteristics of the output circuit 1 of FIG.
It is a figure which shows an example of the output current (Io) characteristic.
Is the output current characteristic of the output transistor when the power supply voltage is high, and 102 is the output current characteristic when the power supply voltage is low.

FIG. 14 is a diagram showing a generally well-known delay circuit, 202 is an inverter circuit that constitutes the delay circuit, and 201 is a circuit configuration in which n inverter circuits are connected in series. It is a delay circuit.

In FIG. 12, a P-channel MOS transistor 3 and an N-channel MOS transistor 4 forming an output circuit are connected to an output terminal 2 to which a load circuit is connected,
Although the VDD level and the GND level are output respectively, the driving capability required for these output transistors 3 and 4 is normally calculated in the development stage of the integrated circuit 1 based on the actual use conditions of the integrated circuit, and the capability thereof is calculated. To determine the transistor size. That is, the output voltage and the output current that should flow at that time are measured with respect to the power supply voltage, the operating temperature, the load, etc. of the integrated circuit, and the size of the transistor that can realize this is calculated and built in the integrated circuit. Here, the built-in output transistors 3 and 4 have DC characteristics as shown in FIG. 13 with respect to the power supply voltage. In FIG. 13, 101 indicates a characteristic when the power supply voltage is relatively high (VDD1), for example, 5V, and 102 indicates a characteristic when the power supply voltage is relatively low (VDD2), for example, 3V. There is. That is, when the size of the output transistor forming the output circuit is determined only under one use condition, for example, when the power supply voltage is 5V, the current that can flow through the transistor is naturally small when the power supply voltage is low, for example, 3V.

On the other hand, conventionally, the power supply voltage of the logic IC has been mainly 5V, but in recent years, with the higher performance and larger scale of the system, it has become necessary to reduce the power consumption of the system.
In addition, the system power supply voltage has been reduced due to the demand for battery drive of the system.

Therefore, there is an increasing demand for low-voltage operation even in the semiconductor integrated circuit used in the system.
However, in general, if the power supply voltage is lowered, the logic operation can be secured in the logic IC, but as described above, the characteristics of the transistors forming the integrated circuit deteriorate,
For example, when the power supply voltage is reduced from 5V to 3V, each AC and DC characteristic of the integrated circuit has a capacity of about 1/2.

[0007] Here, even if the power supply voltage is lowered, AC, DC
If the characteristics are not desired to be changed, it is necessary to redesign the transistor size to be large when the power supply voltage is 3V, for example, and it is necessary to redevelop the integrated circuit itself having the same function for 3V from the beginning.

The output circuit of the integrated circuit has been described above, but the same applies to the circuit operation inside the integrated circuit. For example, the delay integrated circuit 201 shown in FIG.
Is well known, this circuit also uses the inverter 202 as a delay element, and the MO
Since the characteristics of the S-transistor change depending on the power supply voltage, if the power supply voltage is changed, the delay amount will change greatly. Therefore, it is necessary to separately develop the semiconductor integrated circuits for 5V and 3V.

[0009]

As described above, in the conventional semiconductor integrated circuit, the function of the system is kept the same even when the power supply voltage of the system is lowered (3V).
Power supply voltage is high (5V) to keep the same characteristics.
It is impossible to use the integrated circuit used in such a case as it is, and it is necessary to redevelop an integrated circuit having the same function and characteristic at a low power supply voltage. This has been a problem for manufacturers as well, which puts a heavy burden on development.

The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to provide a semiconductor integrated circuit capable of maintaining the same function and the same characteristic even when the power supply voltage is changed. There is.

[0011]

In the semiconductor integrated circuit according to the present invention, a circuit having the same function and characteristics is used in advance at the development stage for each power supply voltage used by the integrated circuit. It is provided with means for designating and controlling those circuit operations in accordance with the power supply voltage.

The semiconductor integrated circuit according to the present invention is
The circuit operation designating control means is provided with a terminal for designating an operation circuit provided in an integrated circuit, a storage element for a signal for designating an operation, a mask layout in any one step of a wafer process, or a power supply voltage supplied. Means for outputting a logic level corresponding to the power supply voltage by comparison with the voltage of, or an operation designating fuse.

[0013]

In the present invention, the circuits that function for each power supply voltage are created in advance, and those circuits are specified and operated according to the power supply voltage to be used. Can obtain the same operating characteristics of the circuit.

Further, the logic level of the operation circuit designating terminal is changed, the logic level is stored in the operation designating signal storage element, or the mask layout of one step of the wafer process is changed in accordance with the power supply voltage to be used. ,
Alternatively, the power supply voltage is automatically detected and the operation designating signal is generated accordingly, or the fuse for operation designating is cut off.
A functioning circuit can be operated for each power supply voltage.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. Example 1. FIG. 1 shows an output circuit in a semiconductor integrated circuit according to an embodiment of the present invention and a circuit for designating and controlling its operation. In the figure, 1 is a package, 2 is an output terminal (package external lead) of the integrated circuit, and 11 is an output. Terminal 2
Connected to the first output circuit, 3, 4 are P-channel transistors forming the first output circuit 11, and N-channel transistors, and 12 is a second output circuit connected to the output terminal 2.
Output circuit, 6 and 8 are first P-channel transistors that form the second output circuit 12, and first N-channel transistors, and 7 is between the power supply voltage (VDD) and the first P-channel transistor 6. A second P-channel transistor connected in series, 9 is a second N-channel transistor connected in series between GND and the first N-channel transistor 8, and 10 is a second N-channel transistor in the second output circuit 12. An inverter connected between the gate of the P-channel transistor 7 and the gate of the second N-channel transistor 9 is a control signal 13 which is also input to the gate of the second N-channel transistor 9 and the inverter 10.
Further, 5 is an input signal of the output circuits 11 and 12, and 14
Is a buffer circuit for outputting the control signal 13, 15 is a control signal input terminal to which the input of the buffer circuit 14 is connected, and 16 is a control signal input terminal 15 outside the package.
Is connected to GND.

Next, the operation of this embodiment shown in FIG. 1 will be described. The output circuit of the integrated circuit is usually composed of only the first output circuit 11 as shown in FIG. 12, but as described above,
If the sizes of the P-channel and N-channel transistors 3 and 4 forming the output circuit are determined when the power supply voltage is 5V, when the power supply voltage is lowered to, for example, 3V, the characteristics of the transistors deteriorate and the characteristics of the integrated circuit. Also becomes lower than when the power supply voltage is 5V.

Therefore, at the development stage of the integrated circuit, the second output circuit 12 is provided beforehand in consideration of use at this low power supply voltage. That is, at the time of low voltage operation in which the transistor characteristic is deteriorated, the deteriorated transistor characteristic is compensated by operating the first output circuit 11 and the second output circuit 12 in parallel. On the other hand, when the power supply voltage is high, the operation of the second output circuit 12 is turned off, and the output load is driven only by the first output circuit 111.

A control signal input terminal 15 is provided in the package of the integrated circuit 1 to specify and control these output operations.

Then, the user of the integrated circuit sets the input terminal 15 provided outside the package 1 to the logic "H" or logic "L" level according to the power supply voltage to be used. For example, when the power supply voltage is 3V, it is necessary to turn on the second output circuit 12.
When the control signal 13 in the integrated circuit 1 is set to logic “H”, the second N-channel transistor 9 in the second output circuit 12
, The gate potential of the second P-channel transistor 7 becomes "L" by the inverter 10 to which the control signal 13 is input, and the second output circuit 12 is turned on. Therefore, the user of the integrated circuit can connect the control signal input terminal 15 of the integrated circuit 1 to the power supply (V
DD).

When the power supply voltage is 5V, the control signal input terminal 15 is connected to GND by the external wiring 16 in order to turn off the second output circuit 12. At this time, the gate potential of the N-channel transistor 9 of the second output circuit 12 becomes "L", the gate potential of the P-channel transistor 7 becomes "H", and the output circuit 12 is turned off.
To do.

According to the first embodiment as described above, the first output circuit 11 whose characteristic changes depending on whether the power supply voltage is 5 V or 3 V is previously compensated for the change in the characteristic due to the power supply voltage in the integrated circuit. Since the second output circuit 12 for controlling the operation of this circuit 12 is designed and controlled from the external control terminal 15, the same integrated circuit can be used regardless of the power supply voltage of the system. You can
Also, the operating characteristics at different power supply voltages can be made the same. Therefore, since the same integrated circuit can be used by a user of the integrated circuit regardless of the power supply voltage of the system, advantages such as easy system design can be obtained.

Example 2. In the first embodiment of FIG. 1, the means for designating and controlling the operation of the circuit for each power supply voltage is the control signal input terminal 15 provided outside the package 1, and the user of the integrated circuit uses the control signal input terminal 15 Is connected to a power supply (VDD) or GND to control the operation of the output circuit 12. As the circuit operation designation control means, as shown in FIG. 3, a control signal input terminal 15 is provided in the integrated circuit. A resistor element 34 is previously provided between the power source in the integrated circuit and the power source.
If you make sure that
Depending on whether the control signal input terminal 15 is connected to GND or not, it is possible to selectively use the power supply voltage of 5V and 3V, and the system board design becomes easy.

Example 3. Similarly, as the circuit operation designation control means, as shown in FIG.
Between the resistor and the GND in the integrated circuit in advance.
If the control input terminal 15 is a power source (VD
Depending on whether or not it is connected to D), it is possible to selectively use the power supply voltage of 5V and 3V.

Example 4. These resistance elements 34 and 35 in the second and third embodiments may be realized by a specific process that can be treated as a resistance in semiconductor manufacturing, for example, by impurity diffusion. As described above, it can be realized by utilizing the ON resistance of the MOS transistor 36.

Example 5. In the above embodiments, the circuit for compensating for the change in the characteristics of the output circuit of the integrated circuit is described. However, as described in the description of the conventional example, the present invention is
It is also effective in compensating the characteristics of various circuits in the integrated circuit.

The fifth embodiment provides a circuit capable of compensating for the case where the delay value of the delay circuit in the conventional example as shown in FIG. 14 varies with the power supply voltage. In such a case, At the development stage of the integrated circuit, as shown in FIG. 2, for example, when the power supply voltage is 5V, a delay circuit 21 having a desired delay time and when the power supply voltage is 3V, the delay circuit 21 has a delay when the power supply voltage is 5V. Time and
A delay circuit 22 having the same delay time is provided, both outputs are switched by the control signal 13 and the selector circuit 23, and the delay time from the input 5 to the output 24 of the delay circuit is the same when the power supply voltage is 5V and 3V. Can be controlled to.

The control method is the same as that of the embodiment shown in FIGS. 1 and 3 to 5, and the control signal terminal 15 is provided in the integrated circuit terminal so that the user of the integrated circuit can control the voltage at which the integrated circuit is used. Accordingly, the potential of the control signal input terminal 15 is set to "H" or "L" level.

For example, when the power supply voltage is 5V, it is necessary to use the delay time of the delay circuit 21. Therefore, the control signal 13 is set to the logic "L" level, and the output 24 of the selector circuit 23 has the delay circuit. 21 signal should appear. For that purpose, the control signal input terminal 15 of the integrated circuit package may be connected to GND by the external wiring 16.

In order to use the power supply voltage of 3V, the control signal input terminal 15 is connected to the power supply (VDD) by the external wiring 16 in order to select the signal of the delay circuit 22.
Then, the control signal 13 in the integrated circuit 1 becomes the logic "H" level, and the signal of the delay circuit 22 appears at the output 24 of the selector 23.

Example 6. In the embodiments of FIGS. 1 and 2, the control signal 13 for designating and controlling the operation of various circuits by the power supply voltage is input to the external terminal of the integrated circuit so that the user of the integrated circuit can set the control signal 13. Although the terminal 15 is provided, this circuit operation designation control means is provided on the integrated circuit maker side at the time of package assembly in order to reduce the number of external terminals, as shown in FIG.
The control signal input terminal (pad) 41 in the package may be connected to VDD or GND by 42.

In this way, the integrated circuit maker does not need to design a circuit for the power supply voltage of 5 V and a circuit for the power supply voltage of 3 V, and the effect of reducing the development load of the integrated circuit can be obtained.

Example 7. As the circuit operation designation control means, as shown in FIG. 7, for example, VDD and pad 41
If a resistance element 35 is formed between the pad 41 and the pad, the integrated circuit maker can put the pad 41 into the GN at the time of package assembly.
The control signal 13 can be set only by connecting or not connecting to D, and in this case, the manufacturing process becomes easier.

Example 8. Further, as the circuit operation designation control means, as shown in FIG. 8, a register (latch) 53 for storing a control signal for designating and controlling the operation of the circuit for each power supply voltage is provided in the integrated circuit to turn on the system. At the time (at the time of initial reset), the logic level of “H” or “L” corresponding to the voltage used may be stored in the register 53.

The control signal data can be written in the register 53 by using the data input terminal 52, the internal data bus 54, and the clock input terminal 51 and the internal clock signal 55 which are used for writing other data. .

Example 9. Further, in the embodiments of FIGS. 1 and 3 to 7, the control signal input terminal is connected to the power supply (VDD) or the GN when the integrated circuit package is assembled or mounted.
Although the operation mode is set by connecting to D, as the circuit operation designation control means, as shown in FIG. 9, the wiring in the integrated circuit is used in the mask layout of any one step during the wafer process. , Photoengraving mask 6
The pattern data of 1 may be changed by changing the pattern data of 61a and 61b, and the control signal 13 may be directly given the logical "H" level or "L" level. In this case, there is an advantage that the external terminal need not be used for inputting the control signal.

Example 10. As the circuit operation designation control means, as shown in FIG. 10, a power supply voltage detection circuit for automatically detecting the power supply voltage and setting the control signal 13 at a predetermined logic level may be provided in the integrated circuit. Good. Also in this case, the control signal input external terminal becomes unnecessary.

In FIG. 10, the power supply voltage is the voltage dividing circuit 7
The voltage is divided by 2 and the + input 7 of the comparator circuit 71 is input.
3 is output. The comparator 71 has this input 73,
The reference voltage Vref connected to the other-input 74 is compared. By appropriately setting the reference voltage (Vref) and the divided potential 73, the output of the comparator 71 outputs a logical “H” level when the power supply voltage is 5V, and an “L” level when the power supply voltage is 3V. Thereby, the operation designation control signal 13 can be obtained.

Example 11. Further, as in the case of FIG. 9, the circuit operation designation control means sets the logic level of the control signal 13 to the fuse 81 provided between the control signal 13 and the power source, and the control signal 13 as shown in FIG. It can also be set by cutting one of the fuses 82 provided between the GND and the GND.

Here, as a method of cutting the fuses 81 and 82, there is a method of cutting with a laser or the like during a wafer test of the integrated circuit, or a method of electrically blowing an overcurrent into the fuses to blow them.

[0040]

As described above, according to the semiconductor integrated circuit of the present invention, for a circuit whose characteristics change according to the power supply voltage, a circuit for compensating for the characteristics change due to the power supply voltage is provided in advance in the integrated circuit. Since it is built in and the operation of this circuit is specified and controlled by the circuit operation specification control means such as the external control terminal, the same integrated circuit is used and the characteristics are the same regardless of the power supply voltage of the system. can do. As a result, it is possible for the manufacturer of the integrated circuit to reduce the development load of the integrated circuit, and also for the user of the integrated circuit, since the same integrated circuit can be used, the system design becomes easy.

[Brief description of drawings]

FIG. 1 is a diagram showing an output circuit in a semiconductor integrated circuit according to a first embodiment of the present invention and a circuit for designating and controlling its operation.

FIG. 2 is a diagram showing a delay circuit according to a fifth embodiment of the present invention.

FIG. 3 is a diagram showing a circuit operation designation control means according to a second embodiment of the present invention.

FIG. 4 is a diagram showing circuit operation designation control means according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a circuit operation designation control means according to a fourth embodiment of the present invention.

FIG. 6 is a diagram showing a circuit operation designation control means according to a sixth embodiment of the present invention.

FIG. 7 is a diagram showing a circuit operation designation control means according to a seventh embodiment of the present invention.

FIG. 8 is a diagram showing a circuit operation designation control means according to an eighth embodiment of the present invention.

FIG. 9 is a diagram showing a circuit operation designation control means according to a ninth embodiment of the present invention.

FIG. 10 is a diagram showing a circuit operation designation control means according to a tenth embodiment of the present invention.

FIG. 11 is a diagram showing a circuit operation designation control means according to an eleventh embodiment of the present invention.

FIG. 12 is a diagram showing an output circuit in a conventional semiconductor integrated circuit.

FIG. 13 is a diagram showing a delay circuit in a conventional semiconductor integrated circuit.

FIG. 14 is a diagram showing a conventional delay circuit.

[Description of Reference Signs] 1 semiconductor integrated circuit package 2 output terminal 11 first output circuit 12 second output circuit 13 control signal 15 control signal input terminal 16 external wiring 21,22 delay circuit 23 selector 24 selector output 34, 35 resistance Element 36 MOS transistor 41 Control signal input terminal 42, 43 Internal wiring 35 Resistive element 51 Clock input terminal 52 Data input terminal 53 Register (latch) 54 Internal data bus 55 Internal clock signal

Claims (8)

[Claims]
1. An operable standard power supply voltage can be set to at least two values or more, and at least one is supplied for each power supply voltage value supplied so that the operating characteristics of the circuit are the same for different power supply voltages used. The section is a semiconductor integrated circuit in which different circuits are made to function, and is provided with means for designating and controlling the operation of the circuit for each power supply voltage.
2. The semiconductor integrated circuit according to claim 1, wherein as the circuit operation designation control means, at least one signal electrode terminal is provided, and a package external terminal connected to the signal electrode terminal is used in actual use. A semiconductor integrated circuit characterized by being set to a logical "H" level or "L" level in accordance with a power supply voltage.
3. The semiconductor integrated circuit according to claim 2, wherein a pull-up or a pull-down is provided between the signal electrode terminal for controlling the circuit operation and the power supply, or between the signal electrode terminal and the ground. A semiconductor integrated circuit having a built-in resistance element.
4. The semiconductor integrated circuit according to claim 2, wherein the signal electrode terminals for the circuit operation designation control are not connected to the external terminals of the package, but are directly connected to the logic “H” level during package assembly. , A semiconductor integrated circuit characterized by being connected to the "L" level.
5. The semiconductor integrated circuit according to claim 1, wherein the circuit operation specifying control means is provided in the integrated circuit, and specifies an operation state specifying signal for specifying and controlling the operation of the circuit for each of the power supply voltages. And a logic "H" level or "L" level corresponding to a power supply voltage used for this memory circuit when the power is turned on.
6. The semiconductor integrated circuit according to claim 1, wherein the circuit operation designation control means sets a mask layout of an arbitrary step during a wafer process, and changes the mask layout to control the operation of the circuit. The semiconductor integrated circuit is characterized in that the level of a signal in the circuit is fixed to a logical "H" level or "L" level.
7. The semiconductor integrated circuit according to claim 1, wherein the circuit operation designation control means detects a power supply voltage to be supplied, compares the power supply voltage with a predetermined voltage, and outputs a logic corresponding to the power supply voltage. A semiconductor integrated circuit characterized in that it is means for outputting a level as a signal for designating and controlling the operation of the circuit for each of these power supply voltages.
8. The semiconductor integrated circuit according to claim 1, wherein the circuit operation designation control means is configured to, after the wafer process is completed,
A fuse that can blow a part of the circuit by laser or electrical means at the time of inspection or mounting is used, and the signal level for designating and controlling the operation of the circuit for each power supply voltage by the blow of the fuse is "H" or "L" level. A semiconductor integrated circuit, characterized in that it is fixed to.
JP4232836A 1992-08-06 1992-08-06 Semiconductor integrated circuit Pending JPH0661841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4232836A JPH0661841A (en) 1992-08-06 1992-08-06 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4232836A JPH0661841A (en) 1992-08-06 1992-08-06 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH0661841A true JPH0661841A (en) 1994-03-04

Family

ID=16945558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4232836A Pending JPH0661841A (en) 1992-08-06 1992-08-06 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0661841A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7164299B2 (en) 2003-01-17 2007-01-16 Nec Corporation Output buffer circuit having pre-emphasis function

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7164299B2 (en) 2003-01-17 2007-01-16 Nec Corporation Output buffer circuit having pre-emphasis function

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