JPH10336013A - Input level variable buffer and its adjusting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adjust an input level without remaking even in the case of the deterioration of an input level caused by noise, etc., by changing a threshold value from one selected information among information from a storing information and information of a control information. SOLUTION: In manufacturing a semiconductor integrated circuit with an input buffer circuit, a storing content (the controlling content of an MOS transistor) is already determined and a two-input selector 118 selects the set value of a storing block 120 to use and only when a set value is used to a control block 119, selects the other. MOS transistor control information of the block 119 or 120 is transmitted to an input buffer circuit 121 by selection by the selector 118. Then, the threshold of an inverter circuit is changed by one information selected by the circuit 118 form among information from the block 120 and information of the block 119.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly, to a device having an input buffer circuit used for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art When a circuit having a CMOS structure is used as an input buffer circuit for taking in an input signal of a semiconductor device inside, an inverter circuit having a CMOS structure is often used. Therefore, a logically inverted value of the input value appears as the output value of the input buffer circuit.

[0005] The input buffer circuit has an input signal level defined, and has various levels such as TTL and CMOS corresponding to the elements connected to the outside at the preceding stage.

In the input buffer circuit, in particular, the input high level (referred to as "VIH") and the input low level ("VI
L ”) is required. This means that an input level equal to or higher than VIH is set to a high level (logical value: High), VIL
The following input level is defined as a low level (logic value: Low) and is taken into the integrated circuit. Ideally, the lower the VIH and the higher the VIL, the easier this input buffer circuit is to use.

However, the input buffer circuit has VIH and V
Because both IL must satisfy the TTL level specification, and it is impossible to avoid variations in various design parameters at the time of semiconductor manufacturing, ultimately, both VIH and VIL exceed the specification. Design the input buffer circuit so that the margin is as large as possible.

FIG. 5 shows an example of a circuit configuration of a conventional input buffer circuit. Referring to FIG. 5, in this inverter circuit, a P-channel MOS transistor 501 is provided.
And the drain terminal of an N-channel MOS transistor 502 are connected, the source terminal of the P-channel MOS transistor 501 is the high-potential power supply VDD 403, and the source terminal of the N-channel transistor 502 is the low-potential power supply VS
S404 is respectively connected, the input terminal is connected to the gate terminals of the MOS transistors 501 and 502, and the output terminal is connected to the drain terminals of the MOS transistors 501 and 502.

The input level is determined by where the threshold values of the N-channel transistor 502 and the P-channel transistor 501 are.

Although there are many configuration parameters of a MOS transistor, an easy method for adjusting the threshold value of the MOS transistor is to use a channel length (L) of the MOS transistor.
And a method of changing the value of the channel width (W). Therefore, in order to change VIH and VIL of the input buffer circuit, it is common to change the channel length and channel width. Furthermore, since the value of the channel length W is very large with respect to the channel length L, it is general to make the channel length L constant and change the channel length W to minimize the influence of variations during semiconductor manufacturing. It is a target.

However, when VDD and VSS fluctuate due to factors such as the circuit configuration and the rate, and it becomes impossible to maintain the potential difference as designed, or when the level of the input signal fluctuates for some reason, the design is made. The input buffer circuit does not operate at the threshold value of the inverter circuit thus set, which causes a malfunction.

[0010] When the input buffer circuit is redesigned, rework from the base is further required, and the development period is extended.

For example, Japanese Unexamined Patent Publication No. Hei 5-152930 discloses that, among a plurality of inverter circuits of a CMOS structure (each having a different threshold value) connected in parallel, a drive circuit is appropriately turned on / off to provide an input buffer. There has been proposed a variable threshold voltage buffer circuit that can easily change the threshold value of the circuit.

[0012]

However, the above-mentioned Japanese Patent Application Laid-Open
In the variable threshold voltage buffer circuit proposed in Japanese Patent Application Laid-Open No. 152930, the input level can be easily changed.
There is a problem that mass production is impossible. In other words, the input level remains unchanged before the change after a few clocks after the power is turned on or after the reset. Therefore, the value of the input level before the change is defined as the input level of the terminal. .

Therefore, in order to manufacture / mass-produce, it is necessary that the conducting / cut-off transistor be specified at the time of manufacturing.

Further, even if a conduction / shutoff transistor can be specified at the time of manufacture using a fuse, the manufacturing conditions are different from those of the already specified sample. Therefore, since the manufacturing conditions vary depending on the manufacturing lot, it is necessary to determine the conduction / shutoff transistor in a state close to the time of actual use, and reflect it in the product under the manufacturing conditions.

Further, it is difficult to find the cause of a malfunction due to noise in the buffer circuit, and it is very difficult to design the circuit in consideration of the noise. For this reason,
It is most accurate to determine the conducting / non-conducting transistor in a situation close to the time of actual use.

In the buffer circuit proposed in the above-mentioned Japanese Patent Application Laid-Open No. 5-152930, a control line of a transistor to be turned on / off or a fuse to be processed (fuse), for example, when added to all input terminals in a semiconductor integrated circuit. ) Is increased.

The smaller the number of these control lines and fuses, the more the layout problem and the like can be avoided. Therefore, the chip size is reduced and the cost can be reduced.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor integrated circuit having an inverter circuit having a CMOS structure as an input buffer circuit, in which an input level caused by noise or the like is reduced. It is an object of the present invention to provide an input level variable buffer capable of easily adjusting the input level without rework even when the deterioration occurs, and a method of adjusting the input level variable buffer.

[0019]

In order to achieve the above object, the present invention relates to a semiconductor integrated circuit having an inverter circuit as an input buffer circuit having a CMOS structure. Control means having a register which can be controlled by a control circuit, and at least one or more inverter circuits connected in parallel which can change a threshold value by appropriately changing the number of transistors which can be driven. The method is characterized in that the threshold value is changed from one of the pieces of information of the means.

The input level adjusting method of the present invention uses a CMOS
At least one or more inverter circuits whose threshold values can be changed by appropriately changing the number of operation transistors constituting the inverter circuit having the structure according to conduction / non-conduction of a switch transistor inserted between the drive transistors. A method of adjusting an input level of a semiconductor integrated circuit further comprising an input buffer circuit including a nonvolatile memory means, wherein a first conductive or non-conductive transistor is set for the input buffer circuit by software. A step, a second step of controlling a set value to be input to the input buffer circuit, a third step of measuring an input level with an IC tester, and determining a conductive or non-conductive transistor from the measurement result. In the fourth step, an error is made so that the determined information can be reflected at the time of mass production. A fifth step of storing the nonvolatile storage unit, the storage information and having a sixth step of controlling so as to input to the input buffer circuit.

[Operation] Further, according to the input buffer circuit of the present invention, the number of control signal lines for adjustment can be reduced, so that layout problems and the like can be avoided. Therefore, the chip size is reduced and the cost is reduced. Reduction is possible.

According to the adjusting method of the present invention, even when the characteristics of the input level do not reach the design purpose, the rework from the base is not required. In addition, since the input level of the input buffer circuit can be adjusted in a state close to the time of actual use, a highly accurate characteristic improvement measure can be taken, and the development period can be greatly reduced.

[0023]

Embodiments of the present invention will be described below. In a preferred embodiment, the input buffer circuit according to the present invention comprises a plurality of inverter circuits, which are composed of a P-channel MOS transistor and an N-channel MOS transistor inserted between a high-potential power supply VDD and a low-potential power supply VSS and are connected in parallel to each other. In one or a plurality of inverters, a switching transistor (106, 107, 110, 111, 11 in FIG. 1) is connected in series to a P-channel MOS transistor and an N-channel MOS transistor.
4, 115), the number of operating inverters is changed by turning on / off the switching transistor, and the threshold value can be set variably, and information for setting the selection of the inverter can be stored in a nonvolatile manner. A storage means (120 in FIG. 1) and a control means (119 in FIG. 1) having a register which can be controlled by software are provided, and information from the storage means (120 in FIG. 1) and the control means (1 in FIG. 1) are provided.
The threshold value of the inverter circuit is changed according to one of the information items (19) selected by the selector (118 in FIG. 1).

In order to describe the above-mentioned embodiment of the present invention in more detail, an embodiment of the present invention will be described below with reference to the drawings.

[Embodiment 1] FIG. 1 is a diagram showing a circuit configuration of an embodiment of the present invention. An input buffer circuit and an input level adjusting method according to an embodiment of the present invention will be described below.

Referring to FIG. 1, the input buffer circuit 12
1, a plurality of CMOS inverter structures are connected in parallel. N channel MOS transistors 103, 10
5, 109 and 113 are connected to the low potential side power source VS
Connected to S. N channel MOS transistor 1
06, 110 and 114 are output terminals 102
, And the source terminal is connected to the drain terminals of the N-channel MOS transistors 105, 109, and 113. The drain terminal of the N-channel MOS transistor 103 is also connected to the output terminal 102.

P channel MOS transistors 104, 1
The high-potential-side power supply VDD is connected to each of the source terminals 08, 112, and 116. The drain terminals of P-channel MOS transistors 107, 111, and 115 are output terminal 1
02, and the source terminal is connected to the drain terminals of the P-channel MOS transistors 108, 112 and 116. P-channel MOS transistor 104
Are also connected to the output terminal 102.

The input terminal 101 is connected to N-channel MOS transistors 104, 108, 112 and 116 and P-channel MOS transistors 103, 105, 109 and 113.
Are commonly connected to the gate terminals of

Encoder circuit 117
Consists of a well-known logic block that encodes a 3-bit decoded signal into 8-bit,
Is a two-input selector. The control block 119 uses C
It has a register that can be controlled by software via a data bus such as a PU (not shown). By controlling the selection of the selector 118, the inverter circuit 12 can be easily controlled.
MOS transistors 107, 111, 11 constituting
5, 106, 110 and 114 can be controlled. The gate terminals of the P-channel MOS transistors 107, 111, 115 and the N-channel MOS transistors 106, 110, 114 are connected to the output of the encoder 117,
ON / OFF of these MOS transistors is controlled by the output of the encoder 117.

The storage block 120 is composed of a nonvolatile memory that can be set from the outside and the CPU.

By the selection in the two-input selector circuit 118, the MOS transistor control information of the control block 119 or the storage block 120 is transferred to the input buffer circuit 12
1 is transmitted.

When the semiconductor integrated circuit having the input buffer circuit shown in FIG. 1 is manufactured, the storage contents (the control contents of the MOS transistors) are already determined, and the two-input selector 118 uses the set value of the storage block 120. The other is selected only when the set value in the control block 119 is used.

In the input buffer circuit 121, N-channel MOS transistors 106, 110, 114 and P
Channel MOS transistors 107, 111, 115
Are switches for controlling the operation of the MOS transistors connected to the respective source terminals.

On the other hand, N-channel MOS transistor 10
3, 105, 109 and 113 and P-channel MOS transistors 104, 108, 112 and 116 are transistors for adjusting and determining the input level, and the input level is determined by the transistor size ratio between the N-channel and the P-channel.

When the input level deteriorates due to an unpredictable factor such as noise at the time of design, the following input level adjustment method is effective to eliminate rework.

At the beginning of manufacture, setting the size ratio between the N-channel MOS transistor and the P-channel transistor according to the design target is the same as in the conventional method. If the design goals are met, there is nothing more to do.

However, if it is worse than the design target due to noise or the like, the following steps are taken. FIG. 2 is a flowchart for explaining this processing flow.

[Evaluation Stage] In the control block 119, the conduction transistor is set by software (step S1).

2. The selector 118 is selected so that the set value of the control block 119 can be transmitted to the input buffer circuit 121 (step S2).

3. The input level of the measurement terminal is measured using a test pattern that can be measured by an LSI tester (IC tester) or the like (step S3).

4. Step 1 above. And step 2. Is repeated to find a combination of conducting / non-conducting transistors (step S4).

5. Step 3 above. Is performed under various manufacturing conditions in order to consider a manufacturing margin (because of manufacturing variations) (step S5).

6. Step 4 above. Based on the measurement results under the above manufacturing conditions, a combination of conducting / non-conducting transistors is determined for the purpose of improving the input level (step S6).

In each of the above steps, the measurement itself is in principle exactly the same as the conventional measurement method.

[Manufacturing stage] The set value is written into a non-volatile memory (flash memory or the like) accessible from the outside, reflecting the result of the above step (step S7).

At the time of manufacture, the MOS
Since the transistor control information is selected so as to be transmitted to the input buffer circuit, rework is not required, and the input level is improved.

Further, it is more effective to adopt an input buffer circuit as shown in FIG. 3 as an embodiment of the present invention.

FIG. 3 is exactly the same as the connection relationship with the input buffer circuit 121 shown in FIG.
The size of each transistor that constitutes the inverter circuit
The points to note are different.

The channel length L of each MOS transistor constituting the inverter circuit is fixed, and only the channel width W is changed at a fixed ratio.

In the example shown in FIG. 3, if the channel width of N channel MOS transistor 303 is 4W ', the channel width of N channel MOS 305/309/313 is 3
If the channel width of W '/ 2W' / 1W 'and P-channel MOS transistor 304 is 4 W, the P-channel MOS
The channel width of the transistors 308/312/316 is 3W / 2W / 1W.

In this combination, all integers can be combined within a certain range (in this example, the unit size × 1 to ×
15), and the size ratio between the N-channel MOS transistor side and the P-channel MOS transistor side can be finely adjusted with a minimum number of control lines.

Furthermore, since the number of control lines can be reduced, the effects of reducing the chip size and cost can be expected.

As shown in the present embodiment, fine adjustment can be made for each input terminal. However, if cost is severe in terms of chip size or the like, input terminals for each functional block or input terminals for each side of the chip may be used. There is also a method of creating a group and adjusting a plurality of input terminals collectively for each group. Further, if the number of inverter circuits connected in parallel is increased, finer fine adjustment can be performed.

FIG. 4 shows the configuration of an input buffer circuit according to a second embodiment of the present invention. 4, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description of the same components will be appropriately omitted to avoid duplication.

FIG. 4 shows a state in which the nonvolatile storage means is not used.
In this method, a signal line is broken by a fuse.

By inserting a fuse 122 between the driving transistor and the output terminal 102, fine adjustment of the input level threshold can be performed in the same manner as in the first embodiment.

In order to reflect this adjustment result at the time of mass production, the fuse (fuse) corresponding to the non-conductive MOS transistor based on the evaluation result may be disconnected.

Therefore, according to this embodiment, the first embodiment is used.
Instead of the storing step of the non-volatile storage means, a step of disconnecting the corresponding fuse is required.

[0059]

As described above, according to the present invention,
This makes it possible to perform highly accurate correction of a cause such as noise that is difficult to consider at the time of design, thereby eliminating the need for rework.

The reason is that in the present invention, when the input level does not reach the design target value, the size ratio between the N-channel transistor and the P-channel transistor of the inverter circuit of the input buffer circuit can be selected and changed by the control line. Means for changing a control line to a set value by a control block at the time of evaluation, and means for externally setting conductive / non-conductive transistor settings so as to reflect the evaluation result at the time of manufacture It has a storage means of the characteristics, and this set value is selected at the time of manufacture.

Further, according to the present invention, by arranging the input buffer circuits with different sizes, there is an effect that finer fine adjustment can be performed with a smaller number of control lines. This contributes to a reduction in chip size in layout, and has an effect of cost reduction.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating an input level adjustment method according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating an example of a configuration of an input buffer circuit according to one embodiment of the present invention;

FIG. 4 is a diagram showing the configuration of a second embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional input buffer circuit.

[Explanation of symbols]

101 Input terminal of input buffer circuit 102 Output terminal of input buffer circuit 103 N-channel MOS transistor 104 P-channel MOS transistor 105 N-channel MOS transistor 106 N-channel MOS transistor 107 P-channel MOS transistor 108 P-channel MOS transistor 109 N-channel MOS transistor 110 N-channel MOS transistor 111 P-channel MOS transistor 112 P-channel MOS transistor 113 N-channel MOS transistor 114 N-channel MOS transistor 115 P-channel MOS transistor 116 P-channel MOS transistor 117 3 to 8 encoder 118 2-input selector 119 control block 120 storage block 121 input buffer Road 122 fuse 301 output terminal 303 N-channel MOS transistor of the input terminal 302 an input buffer circuit of the input buffer circuit (L = constant, W
= 4W ') 304 P-channel MOS transistor (L = constant, W
= 4W) 305 N-channel MOS transistor (L = constant, W
= 3W ′) 306 N-channel MOS transistor 307 P-channel MOS transistor 308 P-channel MOS transistor (L = constant, W
= 3W) 309 N-channel MOS transistor (L = constant, W
= 2W ′) 310 N-channel MOS transistor 311 P-channel MOS transistor 312 P-channel MOS transistor (L = constant, W
= 2W) 313 N-channel MOS transistor (L = constant, W
= 1W ′) 314 N-channel MOS transistor 315 P-channel MOS transistor 316 P-channel MOS transistor (L = constant, W
= 1 MOS transistor 317 Control terminal 318 MOS transistor 311 control terminal 319 MOS transistor 315 control terminal 320 MOS transistor 306 control terminal 321 MOS transistor 310 control terminal 322 MOS transistor 314 control terminal 323 Input buffer circuit 501 P-channel MOS transistor 502 N Channel MOS transistor 503 High-potential-side power supply (VDD) 504 Low-potential-side power supply (VSS) 505 Input terminal 506 Output terminal

Claims (7)

[Claims] 1. A semiconductor integrated circuit having an inverter circuit as an input buffer circuit having a CMOS structure, comprising: storage means capable of storing information in a nonvolatile manner during mass production; control means having a register controllable by software; At least one or more inverter circuits connected in parallel, the threshold value of which can be changed by appropriately changing the number of transistors that can be driven, wherein any one of information from the storage means and information from the control means is selected. An input buffer circuit characterized in that a threshold value of the inverter circuit is changed according to one of the information. 2. A P inserted between a higher power supply and a lower power supply.
A switch is inserted in series with the P-channel MOS transistor and the N-channel MOS transistor in one or a plurality of inverters among a plurality of inverter circuits composed of a channel MOS transistor and an N-channel MOS transistor and connected in parallel with each other; An inverter circuit in which the number of operation inverters is changed and the threshold value can be variably set by turning on / off the power supply; storage means capable of storing information for setting the selection of the operation inverter in a nonvolatile manner; And a control means having a register, wherein the threshold value of the inverter circuit is changed by one of information selected from the information from the storage means and the information from the control means. Input buffer circuit. 3. The threshold value can be changed at least by appropriately changing the number of operation transistors constituting an inverter circuit having a CMOS structure according to conduction / non-conduction of a switch transistor inserted between the drive transistors. A method for adjusting an input level of a semiconductor integrated circuit having an input buffer circuit including one or more inverter circuits and further having a non-volatile memory means, comprising: A first step of setting an input level to the input buffer circuit; a third step of measuring an input level with an IC tester; A fourth step of determining a non-conducting transistor; and mass-producing the determined information. Input level adjustment, comprising: a fifth step of storing the information in the nonvolatile storage unit, and a sixth step of controlling the storage information to be input to the input buffer circuit so that the input information can be reflected in the input buffer circuit. Method. 4. The input buffer circuit according to claim 1, wherein the storage means capable of storing the data during mass production comprises a fuse. 5. The input level adjusting method according to claim 3, wherein the step of storing the operating transistor determination information in the nonvolatile storage unit is a step of disconnecting a fuse. 6. An input buffer circuit in which a plurality of CMOS-structured inverter circuits are connected in parallel and a threshold value is changed by changing an operation transistor, wherein the transistors constituting the inverter circuits connected in parallel have different dimension sizes. An input buffer circuit characterized in that: 7. An input buffer circuit in which a plurality of CMOS-structured inverter circuits are connected in parallel and a threshold value is changed by changing an operation transistor, wherein transistors constituting the inverter circuits connected in parallel have different dimension sizes. 2 ⁿ (n
(Where n is a natural number).