JPH0661440A - Integrated circuit device as well as method and apparatus for data processing of integrated circuit device - Google Patents
Integrated circuit device as well as method and apparatus for data processing of integrated circuit deviceInfo
- Publication number
- JPH0661440A JPH0661440A JP4212478A JP21247892A JPH0661440A JP H0661440 A JPH0661440 A JP H0661440A JP 4212478 A JP4212478 A JP 4212478A JP 21247892 A JP21247892 A JP 21247892A JP H0661440 A JPH0661440 A JP H0661440A
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- Japan
- Prior art keywords
- metal wiring
- integrated circuit
- cell
- circuit device
- information
- Prior art date
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、集積回路装置、集積回
路装置のデータ処理方法、および集積回路装置のデータ
処理装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, a data processing method for the integrated circuit device, and a data processing device for the integrated circuit device.
【０００２】[0002]
【従来の技術】従来より、集積回路装置製造工程におけ
る層間絶縁膜堆積工程において、所定の長さ以上の長さ
を有する金属配線が、前記層間絶縁膜堆積工程で用いら
れる電磁波を受信してしまうと言った、いわゆるアンテ
ナ効果現象の影響で、前記金属配線につながっているゲ
ート酸化膜にダメージを与えるという障害が問題となっ
ている。これに対して従来は回路設計あるいはマスクレ
イアウト設計時に、アンテナ効果に対する回路的な対策
はとられておらず、もっぱらアンテナ効果による損傷が
小さくなるように製造するという、製造上の対策しかと
られていなかった。2. Description of the Related Art Conventionally, in an interlayer insulating film depositing process in an integrated circuit device manufacturing process, a metal wiring having a predetermined length or more receives an electromagnetic wave used in the interlayer insulating film depositing process. There is a problem that the gate oxide film connected to the metal wiring is damaged due to the so-called antenna effect phenomenon. On the other hand, conventionally, no circuit-like measures have been taken against the antenna effect at the time of circuit design or mask layout design, and only manufacturing measures have been taken to manufacture so that damage due to the antenna effect is reduced exclusively. There wasn't.
【０００３】[0003]
【発明が解決しようとする課題】上記のように、アンテ
ナ効果による損傷に対する対策が、集積回路装置データ
作成時には全く考慮されていなかったという問題点があ
った。As described above, there has been a problem that measures against damage due to the antenna effect have not been taken into consideration at the time of creating integrated circuit device data.
【０００４】本発明は係る問題点を解決するためになさ
れたものであって、集積回路装置データ作成段階におい
て、アンテナ効果に対する対策を施すことにより、前記
ゲート酸化膜の損傷を小さくすることを目的としてい
る。The present invention has been made to solve the above problems, and it is an object of the present invention to reduce the damage to the gate oxide film by taking measures against the antenna effect at the stage of creating integrated circuit device data. I am trying.
【０００５】[0005]
【課題を解決するための手段】本発明に係る集積回路装
置は、ゲート電極と、このゲート電極と接続された第１
の金属配線と、この第１の金属配線と接続された所定の
長さ以上の長さを有する第２の金属配線とを有し、前記
第１の金属配線と前記ゲート電極の近傍にＰ型およびＮ
型の拡散領域を設けてダイオードとなし、前記ダイオー
ドと前記第１の金属配線が接続されていることを特徴と
する。An integrated circuit device according to the present invention includes a gate electrode and a first electrode connected to the gate electrode.
And a second metal wiring connected to the first metal wiring and having a length equal to or longer than a predetermined length, the P-type metal wiring being provided near the first metal wiring and the gate electrode. And N
A mold diffusion region is provided to form a diode, and the diode is connected to the first metal wiring.
【０００６】本発明に係る集積回路装置のデータ処理方
法は、集積回路のマスクレイアウトデータ作成時におい
て、セルの入力ピンのみに接続され、所定の長さ以上の
長さを有すると判断または予測された金属配線を検出す
る工程と、前記金属配線が接続されたセルの近傍に保護
ダイオードを含むセルを配置する工程と、前記金属配線
と前記保護ダイオードを含むセルとを接続するために、
前記金属配線と前記保護ダイオードを含むセルとを、集
積回路装置製造工程において前記金属配線が形成される
工程と同じまたはこれ以前の工程で形成される金属配線
で接続する工程とを備えたことを特徴とする。In the data processing method of the integrated circuit device according to the present invention, when the mask layout data of the integrated circuit is created, it is determined or predicted that the data is connected only to the input pin of the cell and has a length longer than a predetermined length. A step of detecting a metal wiring, a step of disposing a cell including a protection diode in the vicinity of the cell to which the metal wiring is connected, and for connecting the metal wiring and a cell including the protection diode,
A step of connecting the metal wiring and the cell including the protection diode with a metal wiring formed in the same step as or before the step of forming the metal wiring in the integrated circuit device manufacturing process. Characterize.
【０００７】本発明に係る集積回路装置のデータ処理装
置は、集積回路の接続情報と、前記集積回路を構成する
論理素子に対応したセルの情報と、前記セルの配置情報
と、前記接続情報に従って前記セルの端子を接続した配
線情報とを、記憶するデータ記憶手段と、前記データ記
憶手段から情報を取りだし、加工して前記データ記憶手
段へ格納する処理手段と、前記処理手段が行なう処理の
手順を記憶したプログラム記憶手段とを備え、前記プロ
グラム記憶手段に記憶した処理の手順がセルの入力ピン
のみに接続され、所定の長さ以上の長さを有すると判断
または予測された金属配線を検出し、前記金属配線が接
続されたセルの近傍に保護ダイオードを含むセルを配置
し、前記金属配線と前記保護ダイオードを含むセルと
を、集積回路装置製造工程において前記金属配線が形成
される工程と同じまたはこれ以前の工程で形成される金
属配線で接続する手順を含むことを特徴とする。A data processing device of an integrated circuit device according to the present invention, in accordance with connection information of the integrated circuit, information of a cell corresponding to a logic element forming the integrated circuit, arrangement information of the cell, and the connection information. Data storage means for storing wiring information connecting terminals of the cells, processing means for extracting information from the data storage means, processing it, and storing it in the data storage means, and procedure of processing performed by the processing means A program storage means for storing the metal wiring, the procedure of the processing stored in the program storage means is connected only to the input pin of the cell, and the metal wiring judged or predicted to have a length equal to or longer than a predetermined length is detected. Then, a cell including a protection diode is arranged in the vicinity of the cell to which the metal wiring is connected, and the cell including the metal wiring and the protection diode is manufactured by an integrated circuit device. Characterized in that it comprises the steps of connecting the same or which metal wiring formed in the previous step and the step of the metal wiring is formed in the process.
【０００８】[0008]
【作用】本発明の集積回路装置においては、上述した構
成によって、第１の金属配線と接続された所定の長さ以
上の長さを有する第２の金属配線が存在する場合、ゲー
ト電極に接続された第１の金属配線の近傍にダイオード
を形成し、このダイオードを第１の金属配線と接続する
ことにより、前記ダイオードがアンテナ効果に対する保
護回路となり、電磁波の影響を防ぐことができ、これに
よりゲート酸化膜の損傷を小さくすることができる。In the integrated circuit device according to the present invention, when the second metal wiring having a length equal to or longer than the predetermined length connected to the first metal wiring is present, it is connected to the gate electrode by the above-described structure. By forming a diode in the vicinity of the formed first metal wiring and connecting this diode to the first metal wiring, the diode serves as a protection circuit against the antenna effect and can prevent the influence of electromagnetic waves. Damage to the gate oxide film can be reduced.
【０００９】本発明の集積回路装置のデータ作成方法お
よび本発明の集積回路装置データ作成装置においては、
集積回路装置のマスクレイアウトデータ作成時におい
て、セルの入力ピンのみに接続され、所定の長さ以上の
長さを有すると判断または予測された金属配線が検出さ
れ、前記金属配線が接続されたセルの近傍に保護ダイオ
ードを含むセルが配置され、前記金属配線と前記保護ダ
イオードを含むセルとが、集積回路装置製造工程におい
て前記金属配線が形成される工程と同じまたはこれ以前
の工程で形成される金属配線で接続されることにより、
前記保護ダイオードが集積回路製造工程において問題と
なるアンテナ効果に対する保護回路となり、電磁波の影
響を防ぐことができ、これによりゲート酸化膜の損傷を
小さくすることができる。In the integrated circuit device data creating method and the integrated circuit device data creating device of the present invention,
When the mask layout data of the integrated circuit device is created, the metal wiring connected to only the input pin of the cell and judged or predicted to have a length equal to or longer than a predetermined length is detected, and the cell to which the metal wiring is connected is detected. A cell including a protection diode is disposed in the vicinity of, and the metal wiring and the cell including the protection diode are formed in the same step as or before the step of forming the metal wiring in the integrated circuit device manufacturing process. By connecting with metal wiring,
The protection diode serves as a protection circuit against the antenna effect which is a problem in the integrated circuit manufacturing process, and can prevent the influence of electromagnetic waves, thereby reducing damage to the gate oxide film.
【００１０】[0010]
【実施例】以下、本発明をその実施例を示す図面に基づ
き詳述する。図１は、本発明に係る集積回路装置の実施
例を示した回路図である。The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. FIG. 1 is a circuit diagram showing an embodiment of an integrated circuit device according to the present invention.
【００１１】図１において、１１はＰチャネルトランジ
スタ、１２はＮチャネルトランジスタである。またＶｄ
ｄは電源端子、Ｖｓｓはグランド端子である。ここで、
Ｐチャネルトランジスタ１１のゲート１１ｇおよびＮチ
ャネルトランジスタ１２のゲート１２ｇは金属配線１１
ｉ（第１の金属配線）により接続され、またそれぞれの
ドレイン１１ｄおよび１２ｄも接続されてインバータセ
ルを構成している。In FIG. 1, 11 is a P-channel transistor and 12 is an N-channel transistor. Also Vd
d is a power supply terminal and Vss is a ground terminal. here,
The gate 11g of the P-channel transistor 11 and the gate 12g of the N-channel transistor 12 are the metal wiring 11
i (first metal wiring), and the respective drains 11d and 12d are also connected to form an inverter cell.
【００１２】またダイオード１４および１５は保護回路
セルを構成しており、この保護回路セルは金属配線１１
ｉ近傍に形成され、金属配線１３（第２の金属配線）を
介してインバータセルの金属配線１１ｉと接続されてい
る。保護回路セルは直接、金属配線１１ｉと接続される
方が望ましい。尚、金属配線１１ｉは第１層金属配線で
形成しており、金属配線１３は第２層金属配線で形成し
ている。The diodes 14 and 15 constitute a protection circuit cell, and the protection circuit cell is a metal wiring 11.
It is formed in the vicinity of i and is connected to the metal wiring 11i of the inverter cell via the metal wiring 13 (second metal wiring). It is desirable that the protection circuit cell be directly connected to the metal wiring 11i. The metal wiring 11i is formed of the first-layer metal wiring, and the metal wiring 13 is formed of the second-layer metal wiring.
【００１３】ここで、金属配線１３が例えば１ｍｍ以上
と言うような長い配線であり、かつこれが形成される時
点で金属配線１１ｉ以外に接続されていない場合を考え
る。この場合、金属配線１３形成後、さらに層間絶縁膜
を形成するとき、電磁波を金属配線１３が受け、この影
響で、Ｐチャネルトランジスタのゲート１１ｇあるいは
Ｎチャネルトランジスタのゲート１２ｇが破壊される場
合がある。Here, consider a case where the metal wiring 13 is a long wiring of, for example, 1 mm or more, and is not connected to anything other than the metal wiring 11i at the time of forming the metal wiring. In this case, when the interlayer insulating film is further formed after the metal wiring 13 is formed, the metal wiring 13 receives an electromagnetic wave, which may damage the gate 11g of the P-channel transistor or the gate 12g of the N-channel transistor. .
【００１４】次に、アンテナ効果により、ゲート１１ｄ
とゲート１２ｄを接続する金属配線１１ｉに接続された
所定の長さ以上の金属配線１３に過剰電圧がかかった時
の保護回路の動作を説明する。金属配線１３に電源端子
Ｖｄｄよりも大きい電圧がかかった場合、ダイオード１
４を電流が順方向に流れることにより定常状態では、金
属配線１３の電圧は電源電圧と等しくなる。また、金属
配線１３にグランド端子Ｖｓｓよりも低い電圧がかかっ
た場合は、ダイオード１５を電流が順方向に流れること
により、定常状態では金属配線１３の電圧はグランド電
圧と等しくなる。このように、保護回路はゲートにかか
る過剰電圧を低減する役割を果たす。Next, due to the antenna effect, the gate 11d
The operation of the protection circuit when an excessive voltage is applied to the metal wiring 13 having a predetermined length or more and connected to the metal wiring 11i connecting the gate 12d and the gate 12d will be described. When a voltage higher than the power supply terminal Vdd is applied to the metal wiring 13, the diode 1
In the steady state, the voltage of the metal wiring 13 becomes equal to the power supply voltage because the current flows in the forward direction. Further, when a voltage lower than the ground terminal Vss is applied to the metal wiring 13, a current flows through the diode 15 in the forward direction, so that the voltage of the metal wiring 13 becomes equal to the ground voltage in a steady state. In this way, the protection circuit serves to reduce the excess voltage on the gate.
【００１５】なお、本実施例においては保護回路を２つ
のダイオードを用いて構成したが、１つまたは２つより
多くのダイオードを用いて構成してもよい。なお、集積
回路製造中はＬＳＩの基板は接地されていることが望ま
しい。In this embodiment, the protection circuit is composed of two diodes, but it may be composed of one or more than two diodes. It is desirable that the substrate of the LSI is grounded during manufacturing of the integrated circuit.
【００１６】図２は、本発明に係る集積回路装置のデー
タ処理方法の実施例を示した流れ図である。集積回路装
置のマスクレイアウトデータ作成時において、金属配線
検出工程２１では、セルの入力ピンのみに接続され、所
定の長さ以上の長さを有すると判断または予測された金
属配線を検出する。保護ダイオードセル配置工程２２で
は、金属配線検出工程２１で検出された金属配線が接続
されたセルの近傍に保護ダイオードを含むセルを配置す
る。金属配線、保護ダイオードセル間接続工程２３で
は、前記金属配線と前記保護ダイオードを含むセルと
を、集積回路装置製造工程において前記金属配線が形成
される工程と同じまたはこれ以前の工程で形成される金
属配線で接続する処理を行なう。FIG. 2 is a flow chart showing an embodiment of the data processing method of the integrated circuit device according to the present invention. At the time of creating mask layout data of the integrated circuit device, in the metal wiring detecting step 21, the metal wiring connected to only the input pin of the cell and judged or predicted to have a length equal to or longer than a predetermined length is detected. In the protection diode cell placement step 22, a cell including a protection diode is placed near the cell to which the metal wire detected in the metal wire detection step 21 is connected. In the metal wiring / protection diode cell connection step 23, the metal wiring and the cell including the protection diode are formed in the same step as or before the step of forming the metal wiring in the integrated circuit device manufacturing step. Perform the process of connecting with metal wiring.
【００１７】図３(a),(b)は各々、図２に示した本発明
に係る集積回路装置のデータ処理方法によって作成され
たマスクレイアウト図、およびこれに対応する回路を示
した回路図である。３２はインバータのセルを示し、３
１は保護ダイオードを含むセル、３３は金属配線のレイ
アウト図を示す。いま、金属配線検出工程２１でインバ
ータセル３２における金属配線が検出されたとすると、
保護ダイオードセル配置工程２２において保護ダイオー
ドを含むセル３１がインバータのセル３２のすぐ隣に配
置され、金属配線、保護ダイオードセル間接続工程２３
において、金属配線３３によりインバータのセル３２と
接続される。FIGS. 3A and 3B are respectively a mask layout diagram created by the data processing method of the integrated circuit device according to the present invention shown in FIG. 2 and a circuit diagram showing a circuit corresponding thereto. Is. Reference numeral 32 denotes an inverter cell and 3
Reference numeral 1 is a cell including a protection diode, and 33 is a layout diagram of metal wiring. Now, assuming that the metal wiring in the inverter cell 32 is detected in the metal wiring detecting step 21,
In the protection diode cell arranging step 22, the cell 31 including the protection diode is arranged immediately adjacent to the cell 32 of the inverter, and the metal wiring and the protection diode cell connecting step 23 are performed.
At, the metal wiring 33 connects to the inverter cell 32.
【００１８】また保護ダイオードを含むセル３１のマス
クレイアウト図に対応する回路図が３４、インバータの
セル３２のマスクレイアウト図に対応する回路図が３
５、金属配線３３のマスクレイアウト図に対応する回路
図が３６である。The circuit diagram corresponding to the mask layout diagram of the cell 31 including the protection diode is 34, and the circuit diagram corresponding to the mask layout diagram of the cell 32 of the inverter is 3.
5, 36 is a circuit diagram corresponding to the mask layout diagram of the metal wiring 33.
【００１９】図４は、本発明に係る集積回路装置のデー
タ処理装置の実施例を示したブロック図である。データ
記憶手段４３は集積回路の接続情報４３ｎと、前記集積
回路を構成する論理素子に対応したセルの情報４３ｃ
と、前記セルの配置情報４３ｐと、前記接続情報に従っ
て前記セルの端子を接続した配線情報４３ｗを記憶す
る。FIG. 4 is a block diagram showing an embodiment of the data processing device of the integrated circuit device according to the present invention. The data storage means 43 includes connection information 43n on the integrated circuit and cell information 43c corresponding to the logic elements forming the integrated circuit.
Then, the cell placement information 43p and the wiring information 43w connecting the terminals of the cell according to the connection information are stored.
【００２０】処理手段４２はデータ記憶手段４３から情
報を取り出し、加工してデータ記憶手段４３へ格納す
る。プログラム記憶手段４１は処理手段４２が行なう処
理の手順を記憶している。処理手段４２が行なう処理の
内容は、図２にて実施例を示した本発明に係る集積回路
装置のデータ処理方法と同じである。尚、プログラム記
憶手段４１とデータ記憶手段４３は、図４に示すよう
に、異なる記憶手段を用いてそれぞれの情報を記憶して
もよく、また、同一の記憶手段を用いてそれぞれの情報
を格納し、適宜情報を選択して用いても良い。The processing means 42 retrieves information from the data storage means 43, processes it, and stores it in the data storage means 43. The program storage means 41 stores the procedure of processing performed by the processing means 42. The contents of the processing performed by the processing means 42 are the same as the data processing method of the integrated circuit device according to the present invention shown in the embodiment in FIG. The program storage means 41 and the data storage means 43 may store respective information by using different storage means, as shown in FIG. 4, or store the respective information by using the same storage means. However, the information may be appropriately selected and used.
【００２１】[0021]
【発明の効果】以上のように本発明は第１の金属配線と
接続された所定の長さ以上の長さを有する第２の金属配
線が存在する場合、ゲート電極に接続された第１の金属
配線の近傍にダイオードを形成し、このダイオードを第
１の金属配線と接続することにより、前記ダイオードが
集積回路装置製造工程で問題となるアンテナ効果に対す
る保護回路となり、電磁波の影響を防ぐことができ、こ
れによりゲート酸化膜の損傷を小さくすることができ
る。As described above, according to the present invention, when the second metal wiring having a predetermined length or more connected to the first metal wiring is present, the first metal wiring connected to the gate electrode is used. By forming a diode in the vicinity of the metal wiring and connecting the diode to the first metal wiring, the diode serves as a protection circuit against the antenna effect which is a problem in the integrated circuit device manufacturing process, and the influence of electromagnetic waves can be prevented. Therefore, damage to the gate oxide film can be reduced.
【００２２】さらに第２の集積回路装置のデータ作成方
法においてはマスクレイアウト作成時にアンテナ効果に
対する対策がとれると言う効果をもたらす。Further, the second method for creating data of the integrated circuit device brings about an effect that a countermeasure against the antenna effect can be taken at the time of creating the mask layout.
【００２３】さらに第３の集積回路装置データ作成装置
においてもマスクレイアウト作成時にアンテナ効果に対
する対策がとれると言う効果をもたらす。Furthermore, the third integrated circuit device data creation apparatus also has the effect that measures can be taken against the antenna effect when creating a mask layout.
【図１】本発明の一実施例に係る集積回路装置の回路図FIG. 1 is a circuit diagram of an integrated circuit device according to an embodiment of the present invention.
【図２】同実施例に係る集積回路装置のデータ処理方法
を示した流れ図FIG. 2 is a flowchart showing a data processing method of the integrated circuit device according to the embodiment.
【図３】(a)は図２に示したデータ処理方法によって作
成されたマスクレイアウト図 (b)は同マスクレイアウト図に対応した回路図3A is a mask layout diagram created by the data processing method shown in FIG. 2, and FIG. 3B is a circuit diagram corresponding to the mask layout diagram.
【図４】同実施例に係る集積回路装置のデータ処理装置
のブロック図FIG. 4 is a block diagram of a data processing device of the integrated circuit device according to the embodiment.
１１ Ｐチャネルトランジスタ １１ｉ 金属配線 １２ Ｎチャネルトランジスタ １３ 金属配線 １４,１５ ダイオード ２１ 金属配線検出工程 ２２ 保護ダイオードセル配置工程 ２３ 金属配線、保護ダイオードセル間接続工程 ４１ プログラム記憶手段 ４２ 処理手段 ４３ データ記憶手段 ４３ｎ 集積回路の接続情報 ４３ｃ 論理素子に対応したセルの情報 ４３ｐ セルの配置情報 ４３ｗ 配線情報 11 P-Channel Transistor 11i Metal Wiring 12 N-Channel Transistor 13 Metal Wiring 14, 15 Diode 21 Metal Wiring Detection Process 22 Protective Diode Cell Arranging Process 23 Metal Wiring, Protection Diode Cell Connecting Process 41 Program Storage Means 42 Processing Means 43 Data Storage Means 43n Integrated circuit connection information 43c Cell information corresponding to logic element 43p Cell placement information 43w Wiring information
フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/088 9170−4Ｍ Ｈ０１Ｌ 27/08 １０２ Ｆ Continuation of front page (51) Int.Cl. 5 Identification number Office reference number FI technical display location H01L 27/088 9170-4M H01L 27/08 102 F
Claims (3)
た第１の金属配線と、この第１の金属配線と接続された
所定の長さ以上の長さを有する第２の金属配線とを有
し、前記第１の金属配線と前記ゲート電極の近傍にＰ型
およびＮ型の拡散領域を設けてダイオードとなし、前記
ダイオードと前記第１の金属配線が接続されていること
を特徴とする集積回路装置。1. A gate electrode, a first metal wiring connected to the gate electrode, and a second metal wiring connected to the first metal wiring and having a predetermined length or more. A P-type diffusion region and an N-type diffusion region are provided near the first metal wiring and the gate electrode to form a diode, and the diode and the first metal wiring are connected to each other. Integrated circuit device.
成時において、セルの入力ピンのみに接続され、所定の
長さ以上の長さを有すると判断または予測された金属配
線を検出する工程と、前記金属配線が接続されたセルの
近傍に保護ダイオードを含むセルを配置する工程と、前
記金属配線と前記保護ダイオードを含むセルとを、集積
回路装置製造工程において前記金属配線が形成される工
程と同じまたはこれ以前の工程で形成される金属配線で
接続する工程とを備えたことを特徴とする集積回路装置
のデータ処理方法。2. A step of detecting a metal wiring that is connected to only an input pin of a cell and is determined or predicted to have a length equal to or longer than a predetermined length when creating mask layout data of an integrated circuit device, The step of disposing a cell including a protection diode in the vicinity of the cell to which the metal wiring is connected and the step of forming the metal wiring in the integrated circuit device manufacturing step are the same as the step of forming the metal wiring and the cell including the protection diode. Or a step of connecting with a metal wiring formed in a step before this, a data processing method for an integrated circuit device.
成する論理素子に対応したセルの情報と、前記セルの配
置情報と、前記接続情報に従って前記セルの端子を接続
した配線情報とを記憶するデータ記憶手段と、前記デー
タ記憶手段から情報を取りだし、加工して前記データ記
憶手段へ格納する処理手段と、前記処理手段が行なう処
理の手順を記憶したプログラム記憶手段とを備え、 前記プログラム記憶手段に記憶した処理の手順がセルの
入力ピンのみに接続され、所定の長さ以上の長さを有す
ると判断または予測された金属配線を検出し、前記金属
配線が接続されたセルの近傍に保護ダイオードを含むセ
ルを配置し、前記金属配線と前記保護ダイオードを含む
セルとを、集積回路装置製造工程において前記金属配線
が形成される工程と同じまたはこれ以前の工程で形成さ
れる金属配線で接続する手順を含むことを特徴とした集
積回路装置のデータ処理装置。3. Information of connection of an integrated circuit, information of a cell corresponding to a logic element forming the integrated circuit, arrangement information of the cell, and wiring information connecting terminals of the cell according to the connection information. The program storing means includes a data storing means for storing the information, a processing means for taking out information from the data storing means, processing it and storing it in the data storing means, and a program storing means for storing a procedure of processing performed by the processing means. The procedure of the process stored in the storage means is connected only to the input pin of the cell, detects the metal wiring that is determined or predicted to have a predetermined length or more, and detects the vicinity of the cell to which the metal wiring is connected. A cell including a protection diode is arranged in the same manner, and the metal wiring and the cell including the protection diode are formed in the same step as the step of forming the metal wiring in the integrated circuit device manufacturing process. A data processing device for an integrated circuit device, which includes a step of connecting with metal wiring formed in the same step or a step before this.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4212478A JPH0661440A (en) | 1992-08-10 | 1992-08-10 | Integrated circuit device as well as method and apparatus for data processing of integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4212478A JPH0661440A (en) | 1992-08-10 | 1992-08-10 | Integrated circuit device as well as method and apparatus for data processing of integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0661440A true JPH0661440A (en) | 1994-03-04 |
Family
ID=16623314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4212478A Pending JPH0661440A (en) | 1992-08-10 | 1992-08-10 | Integrated circuit device as well as method and apparatus for data processing of integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0661440A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0840377A1 (en) * | 1996-11-01 | 1998-05-06 | Motorola, Inc. | Semiconductor device using diode place-holders and method of manufacture thereof |
| EP0993046A2 (en) * | 1998-09-28 | 2000-04-12 | Siemens Aktiengesellschaft | Method of integrating protective elements into masterslice integrated circuits |
| KR100323452B1 (en) * | 1999-12-30 | 2002-02-06 | 박종섭 | Eletromagnetic Interference prevention circuit |
| US6393603B1 (en) | 1998-12-10 | 2002-05-21 | Nec Corporation | Circuit design method calculating antenna size of conductive member connected to gate oxide film of transistor with approximate expression |
| US6421816B1 (en) | 1998-04-07 | 2002-07-16 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system |
| US6713817B2 (en) | 2000-10-31 | 2004-03-30 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit system |
| JP2007293822A (en) * | 2006-03-31 | 2007-11-08 | Nec Corp | Lsi design system, antenna damage prevention method and prevention control program used in same |
| US9142556B2 (en) | 2012-03-23 | 2015-09-22 | Rohm Co., Ltd. | Dummy gate cell, cell-based IC, and portable device |
-
1992
- 1992-08-10 JP JP4212478A patent/JPH0661440A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6308308B1 (en) | 1996-11-01 | 2001-10-23 | Motorola Inc. | Semiconductor device using diode place-holders and method of manufacture thereof |
| US5966517A (en) * | 1996-11-01 | 1999-10-12 | Motorola, Inc. | Semiconductor device using diode place-holders and method of manufacture thereof |
| EP0840377A1 (en) * | 1996-11-01 | 1998-05-06 | Motorola, Inc. | Semiconductor device using diode place-holders and method of manufacture thereof |
| US7114140B2 (en) | 1998-04-07 | 2006-09-26 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system |
| US6421816B1 (en) | 1998-04-07 | 2002-07-16 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system |
| US6502225B2 (en) | 1998-04-07 | 2002-12-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system |
| US6502226B2 (en) | 1998-04-07 | 2002-12-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system |
| US6611950B2 (en) | 1998-04-07 | 2003-08-26 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device, semiconductor device design method, semiconductor device design method recording medium, and semiconductor device design support system |
| CN100359688C (en) * | 1998-04-07 | 2008-01-02 | 松下电器产业株式会社 | Semiconductor device and design method and the recording medium and support system for said method |
| EP0993046A3 (en) * | 1998-09-28 | 2005-06-08 | Infineon Technologies AG | Method of integrating protective elements into masterslice integrated circuits |
| EP0993046A2 (en) * | 1998-09-28 | 2000-04-12 | Siemens Aktiengesellschaft | Method of integrating protective elements into masterslice integrated circuits |
| US6393603B1 (en) | 1998-12-10 | 2002-05-21 | Nec Corporation | Circuit design method calculating antenna size of conductive member connected to gate oxide film of transistor with approximate expression |
| KR100323452B1 (en) * | 1999-12-30 | 2002-02-06 | 박종섭 | Eletromagnetic Interference prevention circuit |
| US6713817B2 (en) | 2000-10-31 | 2004-03-30 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit system |
| JP2007293822A (en) * | 2006-03-31 | 2007-11-08 | Nec Corp | Lsi design system, antenna damage prevention method and prevention control program used in same |
| US9142556B2 (en) | 2012-03-23 | 2015-09-22 | Rohm Co., Ltd. | Dummy gate cell, cell-based IC, and portable device |
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