JP2003209172A - Design method of semiconductor device and design device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout design technique of a semiconductor device which can obtain reduction in chip size and man-hour of layout design by arranging a cell capable of avoiding charge-ups. <P>SOLUTION: The layout design is applied to a semiconductor device which is manufactured with a plurality of gate level cells and a high-functional block level macro-cell mixed. The layout design of the semiconductor device is carried out according to steps S1 to S8. The arrangement design of a cell is carried out by inputting a maximum area value, which does not cause a charge-up defect, in an arrangement step of cell (S3), dividing an allocated area for cells automatically based on the maximum area value (S4) and arranging cells in the divided allocated area (S5). <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device design technique, and is particularly effective when applied to a semiconductor device design method and a design device which are suitable as a measure against charge-up leading to gate breakdown of a MOS transistor in cell arrangement. Related technology.

[0002]

2. Description of the Related Art According to a study made by the present inventor, regarding a design technique of a semiconductor device, for example, Japanese Patent Laid-Open No. 2000-2000
The technology described in Japanese Patent Laid-Open No. 150607 is cited. This publication discloses a mask pattern design device that determines a damage rule based on a gate exposed area, an antenna ratio, and the like, and changes the layout by checking the rule.

[0003]

By the way, as a result of the present inventor's examination of the design technique of the semiconductor device as described above, the following facts have become clear.

For example, the above-mentioned Japanese Patent Laid-Open No. 2000-15060.
The technique disclosed in Japanese Patent Publication No. 7 is a method of inputting damage information and a circuit diagram created by a process simulator and performing a damage rule check after layout. That is, this technique is a phenomenon in which the gate oxide film is damaged by the charges charged in the metal wiring layer during the ion implantation in the manufacturing process, and the MOS transistor is destroyed or reliability is deteriorated. Technology.

The following techniques can be considered as the design technique of the semiconductor device examined by the present inventor.

For example, in the design of a semiconductor device, when a common power supply circuit is used, cells used in an integrated circuit are arranged so that they are connected to each other in order to reduce the chip area, that is, they are spread without leaving a cell interval. We are arranging. When the result of the layout of these spreads is large, the area of resist applied on the cells in the chip manufacturing process also becomes large. Along with this, the amount of charge that is charged up by ion implantation also increases, so it is conceivable that destruction of the gate oxide film and deterioration of device characteristics will occur.

Further, generally, in order to reduce the amount of charge charged up in the resist, measures such as process technology and equipment are taken. For example, in the diffusion process, as the miniaturization progresses, the gate oxide film becomes thinner, and even if the same amount of electric charge is generated, it is easy to destroy the gate oxide film.

Therefore, at the layout designing stage, it is attempted to reduce the amount of charges charged up by appropriately dividing the cells by changing the area such as spacing between the spread cell rows. The division of 1 causes a wasteful area due to manual work and an increase in design man-hours due to re-design.

That is, according to the technique examined by the present inventor as a premise of the present invention, a case where the macro 2 and the cell 3 are arranged on the chip 1 as shown in an example in FIGS. To read the input data (step S4
1), allocation of cell layout area (step S42,
(B)), manually dividing the cell layout area (step S
43, (c)), cell placement (step S44,
(D)), wiring between cells (step S45), area violation check (step S46, (e)) are performed in order, and as a result of the check (step S47), if there is an area violation, manual cell placement in step S43. The process from the division of the area is repeated, and the process ends when there is no violation of the area.
48).

For example, in the area violation check, the charge-up violation area is set to 100 and the area is checked. As a result, area A = 50, area B = 40, area C = 45, area D = 45, area E = 105, area F = 110, area G = 75, area H = 15, area E and area F are area violations (NG), and the cell arrangement area is again divided manually.

In this method, since the cell rows are manually opened so as not to cause the charge-up failure, the width is too wide and a wasteful area is apt to occur. In addition, since it is detected whether or not there is an area violation at the DRC verification stage, the number of man-hours to go back is required when there is a violation, which is a factor of design delay.

Therefore, in order to reduce the chip size and the layout design man-hour, the present inventor considers a predetermined upper limit area value at the cell placement stage of the layout design and considers a cell that does not cause a charge-up failure. I came up with the idea of automatically calculating the area and placing it.

An object of the present invention is to provide a semiconductor device design technique capable of realizing a layout design capable of reducing a chip size and layout man-hours by arranging cells in consideration of charge-up measures. It is in.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the method of designing a semiconductor device according to the present invention has a step of arranging a plurality of cells based on circuit information. In this step, an upper limit area value is input and the input upper limit area value is set. It includes each step of automatically dividing the arrangement area of a plurality of cells based on the above, and arranging the plurality of cells in the divided arrangement area.

Further, in the method of designing a semiconductor device, the step of inputting the upper limit area value includes the X direction and the Y direction.
It includes the step of inputting the width of the direction. Further, the step of automatically dividing the arrangement area of the plurality of cells, obtains the arrangement area of the plurality of cells, determines the division area based on the obtained arrangement area, and the upper limit area value, and this is determined. Based on the number of divisions, the layout area of multiple cells is divided so as to satisfy the circuit and logic constraints, and it is determined whether or not the divided layout area is a charge-up violation. , If it is a charge-up violation, repeat the process from the input of the upper limit area value,
It includes each step. Further, there is a step of outputting layout data after the step of arranging the plurality of cells is completed, and this layout data is applied to mask data in the gate forming step and the source / drain region forming step of the MOS transistor. . Further, the upper limit area value is set based on the area of the resist applied on the cells in the manufacturing process of the semiconductor device.

Further, the semiconductor device designing apparatus according to the present invention has means for arranging a plurality of cells based on circuit information, and this means reads the input upper limit area value and reads the upper limit area value. It includes means for automatically dividing the arrangement area of the plurality of cells based on the value and arranging the plurality of cells in the divided arrangement area.

Further, in the semiconductor device designing apparatus, the means for reading the upper limit area value is capable of reading the input vacant widths in the X and Y directions. The means for automatically dividing the arrangement area of the plurality of cells determines the arrangement area of the plurality of cells, determines the number of divisions based on the obtained arrangement area, and the upper limit area value, and determines this. Based on the number of divisions, the layout area of multiple cells is divided so as to satisfy the circuit and logic constraints, and it is determined whether or not the divided layout area is a charge-up violation. In the case of a charge-up violation, it is possible to repeat the processing from the input of the upper limit area value. Also, it is possible to output layout data after the arrangement of the plurality of cells is completed, and the layout data is
It is applied to the mask data of the gate forming process and the source / drain region forming process of the S transistor. The upper limit area value can be set based on the area of the resist applied on the cell in the manufacturing process of the semiconductor device.

Therefore, according to the semiconductor device designing method and the designing device, the upper limit area value which does not cause the charge-up failure is considered in the cell layout stage of the layout design, and the charge-up failure is automatically performed based on the upper limit area value. By arranging the cells by dividing them into cell areas that do not
It is possible to prevent charge-up that may occur in the manufacturing process of a semiconductor device when forming a mask for a MOS transistor. In addition, since the cells are arranged in consideration of charge damage, it is possible to realize a highly accurate layout design without backtracking.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

First, with reference to FIG. 1, an example of a procedure of a layout design process in a semiconductor device designing method according to an embodiment of the present invention will be described. FIG. 1 is a flow chart showing a layout design process of a semiconductor device, (a) shows a flow of a design procedure, and (b) to (e) show a layout on a chip in each design procedure.

The semiconductor device of the present embodiment is applied to, for example, a semiconductor device in which a plurality of gate-level cells and highly functionalized block-level macrocells are mixed and manufactured. The design of this semiconductor device is, for example, CAD or D.
Using a design tool built on a workstation using computer software called A, each process of system design, logic circuit design, and layout design is performed in order based on design specifications. In particular, the layout design of the semiconductor device is performed by the following procedure using the design tool as described above and the circuit information created by the system design and the logic circuit design.

(1) Read input data (step S
1) In step S1, wiring connection information (netlist), cell layout information, technology information (design constraints), etc. are input.

(2) Allocation of Cell Arrangement Area (Step S2) In this step S2, a region in which cells are arranged is input. For example, taking a semiconductor memory as an example, a macro 2 of a predetermined block such as a memory cell array on a chip 1,
Considering the case of arranging a plurality of cells 3 such as peripheral circuits around this memory cell array, in the state of (b), a charge-up failure occurs due to a violation of the area of resist coating. Therefore, the following area division is necessary.

(3) Input of upper limit area value (step S3) In this step S3, an upper limit area value which does not cause damage to the gate oxide film due to charge-up failure is input. For example, (c) shows an example of tool menu specifications, and Ad
d To Area item has upper limit area value (μm), Vi
Width of the space in the X direction (μm) in the Horizontal Space Width item, Horizontal Space
Input the width (μm) in the Y direction in the Width item. The mechanism leading to gate destruction is shown in Fig. 3.
Will be described later.

(4) Dividing Cell Arrangement Area Considering Upper Limit Area Value (Step S4) In this step S4, the arrangement area of the cells 3 allocated in step S2 in consideration of the upper limit area value input in step S3 is taken into consideration. Split automatically. For example, (d)
In this state, based on the input of the upper limit area value, the empty area 4 is automatically arranged in the X direction and the Y direction of the column of the cells 3 so as not to cause a charge violation. A specific dividing method will be described later with reference to FIG.

(5) Arrangement of Cells (Step S5) In this step S5, the cells 3 are arranged in the arrangement area divided in the step S4. For example, in the state of (e), the cell area 5 can be arranged without violating the charge-up area by the charge-up countermeasure at the time of area division. When checking each area with the charge-up violation area = 100, area A (+ D) = 99, area B (+ C)
= 99, area E = 95, area F = 99, area G =
Unlike 99, there is no extra area and a small area is not created.

(6) Mask Data for MOS Transistor Creation (Step S6) In this step S6, mask data for MOS transistor creation considering the upper limit area value is output. In addition, M
An example of mask data for creating the OS transistor is shown in FIG.
Will be described later.

(7) Wiring Between Cells (Step S7) In this step S7, wiring is carried out between the cells 3 arranged in step S5.

(8) Wiring mask data (step S
8) In this step S8, mask data at the chip or block level of the wiring connecting between the cells 3 is output.

Then, a mask for forming MOS transistors in cells is created using the MOS transistor creation mask data, and a mask for connecting the cells by wires is created using the wiring mask data. These masks are used in the semiconductor device manufacturing process.

Next, an example of the procedure of the semiconductor device manufacturing process will be described with reference to FIG. FIG. 2 is a flowchart showing the manufacturing process of the semiconductor device.

(1) Wafer Process (Step S11) In this step S11, although not particularly limited, surface treatment, oxidation, photolithography (resist coating, Exposure, development, etching, resist removal), ion implantation / diffusion, film formation, etc.
A transistor and a wiring are formed. In particular, the mask formed as described above is used as a photomask for forming a gate of a MOS transistor and forming source / drain regions in an exposure step of photolithography.

(2) Assembly (Step S12) In this step S12, after the wafer having undergone the wafer process is cut into individual chips, for example, die bonding, wire bonding, A semiconductor device having a package structure is completed through processes such as molding, lead cutting, and marking.

(3) Inspection (Step S13) In this step S13, a final inspection of the completed semiconductor device is performed, and a good semiconductor device whose reliability is confirmed by an electrical characteristic test may be shipped as a product. it can.

Next, referring to FIG. 3, an example of a mechanism of gate breakdown due to charge-up failure will be described as a technique studied by the present inventor. 3A and 3B are explanatory views showing the mechanism of gate breakdown due to charge-up failure, where FIG. 3A shows the flow of charges at the time of ion implantation, and FIG. 3B shows the flow of conduction current of the MOS transistor.

In the diffusion process of the manufacturing process of the semiconductor device, the gate oxide film becomes thinner as the miniaturization progresses, and even if the amount of charge is the same, the gate oxide film is likely to be destroyed. This phenomenon is due to the fact that when the layout result in which the cells are laid out with no space between them is large, the area of resist applied on the cells is also large, and the amount of charges charged up by ion implantation is also large. It is considered to be further promoted.

For example, when there is a gate electrode or a resist having a large area on the gate oxide film at the time of ion implantation as shown in (a), this portion functions to collect electric charges to amplify the damage of the gate oxide film. . In such cases,
An excessive voltage is applied between (A) and (B), and the gate oxide film is broken, so that conduction occurs. Therefore, as shown in (b), a defective MOS transistor is formed due to the current flowing across the thin gate oxide film of the transistor.

Therefore, the present inventor has found that it is possible to take measures against charge-up by considering the area of one unit of cells arranged in a line. Here, the reason why the electric field strength applied to the oxide film which destroys the gate, which the present inventor has found out, is proportional to the area value S of the resist applied.

Q is the charge amount charged in the resist,
When the gate oxide film is regarded as a capacitor and the capacitance value is C, the voltage value V is Q = C × V (1)

When the thickness of the gate oxide film is Tox and the electric field strength applied to the gate oxide film is E, E = V / Tox = Q / (C × Tox) (2)

As preconditions, (1) it is considered that the charge amount Q is proportional to the area value S of the resist.

Q∝S∴Q = A × S A: Proportional constant (area) (2) The film thickness Tox of the gate oxide film of all the MOS transistors in the cell coated with resist cannot be uniformly coated. First, it is considered that the film thickness Tox varies in a certain range. The thinnest film thickness is Toxmin.

(3) The charged electric charge (total: Q) is mostly charged (α × Q) in the thinnest portion. α is a proportional constant (charge amount). I think the destruction always happens from here. The capacitance value of the thinnest gate oxide film is Cg.

From these preconditions (1) to (3), considering the electric field strength (Emin) applied to the thinnest gate oxide film in the equation (2), Emin = (α × Q) / (Cg × Toxmin) ) = [Α × (A × S)] / (Cg × Toxmin) = [(A × α) / (Cg × Toxmin)] × S (3) where Emin is the area value of S. Proportional to S
If is small, the electric field strength is low and gate breakdown does not occur. In addition, [(A × α) / (Cg × Toxmin)]
The part of is a coefficient determined by the process.

Therefore, the electric field strength at which the gate breakdown of a MOS transistor having a thin gate oxide film occurs is Eth (Eth)
Is determined by the process). If Eth ≦ Emin, no destruction occurs. If Eth> Emin, the above relationship is established.

Next, an example of the procedure of the dividing method of the cell arrangement area will be described with reference to FIG. FIG. 4 is a flow chart showing a method for dividing the cell layout area. FIG.
(B) shows the layout on the chip. In addition,
In FIG. 4, N: total area value in which cells are arranged, S: upper limit area value that does not cause charge-up violation, Dn: number of divided N (D1, D2, ..., D5), Wx: in X direction A space value between cell areas and a space value between cell areas in the Wy: Y direction are shown.

(1) Input processing on the tool (step S
20) In the input processing on this tool, in step S21, the upper limit area value (S) is input, and further, the value of the vacant width (vacant area) in the X (Wx) or Y (Wy) direction is input.

(2) Internal processing of the tool (step S3)
0) In the internal processing of this tool, first, in step S31, the arrangement area value (N) of the cell 3 is obtained. Succeedingly, in a step S32, the division number (Dn) is determined. The number of divisions is the number of divisions (Dn) = cell arrangement area value (N) / upper limit area value (S). Then, in step S33,
The arrangement area value (N) of the cells 3 is divided according to the division number (Dn) so as to satisfy the circuit constraint (speed, power) and the logical constraint. Finally, in step S34, an area violation check is performed, and if there is an area violation, the processing from step S21 is repeated, and the process ends when there is no area violation.

As a result of dividing the arrangement area of the cells 3,
As shown in (b), in the layout of the cells 3 on the chip 1, the layout area values of the cells 3 are D1, D2, D3, D.
4, it can be divided into sizes such as D5 that do not cause a charge-up violation.

Next, an example of mask data for creating a MOS transistor will be described with reference to FIG. FIG. 5 is an explanatory diagram showing mask data for creating a MOS transistor,
(A) shows one cell on the chip, (b) shows the resist before coating, (c) shows the resist-free portion after the resist coating, and (d) shows the resist-coated portion after the resist coating. Show. This mask data is MOS
It is used to form the gate and source / drain regions of a transistor.

In the cell 3, for example, as shown in (b), the PMOS transistor PMOS is arranged on the upper side and the NMOS transistor NMOS is arranged on the lower side, and these are arranged so that they are connected via the metal wiring M on the center side. Has become. In each of the transistors PMOS and NMOS, a diffusion layer of a source S and a drain D is formed on the surface of the wafer,
An electrode of the gate G is formed on the surface of the gate oxide film. Further, the source S and the drain D are arbitrarily connected to the metal wiring M formed on the surface of the wafer through the conductive contact C.

In the diffusion process of the manufacturing process of the semiconductor device including the cell 3 as described above, for example, as shown in (c),
The portions of the diffusion layers of the source S and the drain D of the PMOS transistor PMOS and the NMOS transistor NMOS are portions not coated with resist, and the other portions are portions coated with resist as shown in (d).
In the present invention, the area of the part to which this resist is applied is
As described above, consideration is given so as not to exceed the predetermined area value.

Therefore, according to the present embodiment, in the layout design, the upper limit area value which does not cause the charge-up failure is input at the placement stage of the cells 3 and the placement area of the cells 3 is automatically divided, thereby eliminating waste. It does not generate a large area. Moreover, since the arrangement of the cells 3 can be changed without performing any manual work, the error potential can be eliminated. Further, since the layout area of the cells 3 that does not cause the charge-up failure is automatically calculated and arranged, the backtracking of the area violation is reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, although the semiconductor device of the semiconductor memory has been described as an example in the above embodiments, the present invention is not limited to this, and is applicable to all integrated circuits including a MOS transistor as a circuit element, and particularly, Since the chip size is reduced, it can be favorably applied to a semiconductor device that employs a technique of laying out cells.

[0058]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1) In the layout design, by considering the upper limit area value which does not cause the charge-up failure at the cell placement stage, it is possible to prevent the charge-up that may occur in the manufacturing process of the semiconductor device.

(2) In the layout design, by arranging the cells by dividing them into cell areas which do not cause a charge-up failure automatically based on the upper limit area value at the cell arranging stage, the layout is highly accurate and has no backtracking. It is possible to realize the design.

(3) According to the above (1) and (2), by taking measures against charge-up at the layout design stage, it is possible to detect the broken portion of the gate oxide film before manufacturing, so that the yield of products is improved. It is possible to prevent the occurrence of mask defects.

[Brief description of drawings]

1A to 1E are flow charts showing a layout design process of a semiconductor device in a method of designing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

3A and 3B are explanatory views showing a mechanism of gate breakdown due to charge-up failure in the embodiment of the present invention.

4A and 4B are flow charts showing a method of dividing a cell layout area in an embodiment of the present invention.

5A to 5D are explanatory diagrams showing mask data for forming a MOS transistor in the embodiment of the present invention.

6A to 6E are flowcharts showing a layout design process of a semiconductor device in a method of designing a semiconductor device studied as a premise of the present invention.

[Explanation of symbols]

1 chip 2 macro 3 cells 4 vacant areas 5 cell area

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kenji Nakata             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Hidenori Kitajima             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group F-term (reference) 5B046 AA08 BA04 JA01                 5F048 AA02 AB02 AC01 BB05 CC11                       CC15 CC18                 5F064 BB12 BB35 CC09 DD02 DD13                       DD22 GG01 HH06 HH09 HH10                       HH18

Claims (10)

[Claims] 1. A step of arranging a plurality of cells based on circuit information, wherein the step of arranging the plurality of cells includes a step of inputting an upper limit area value and a step of inputting an upper limit area value based on the input upper limit area value. A method of designing a semiconductor device, comprising: automatically dividing an arrangement area of the plurality of cells; and arranging each of the plurality of cells in the divided arrangement area. 2. The method of designing a semiconductor device according to claim 1, wherein the step of inputting the upper limit area value includes a step of inputting an opening width in the X direction and the Y direction. Method. 3. The method of designing a semiconductor device according to claim 1, wherein the step of automatically dividing an arrangement area of the plurality of cells comprises:
Based on the determined number of divisions, the step of determining the placement area of the plurality of cells, the step of determining the number of divisions based on the obtained placement area, and the upper limit area value,
Dividing the layout area of the plurality of cells so as to satisfy the circuit constraint and the logic constraint; determining whether the divided layout area is a charge-up violation; If the violation is an up violation, a step of repeating the processing from the step of inputting the upper limit area value is included. 4. The method of designing a semiconductor device according to claim 1, further comprising a step of outputting layout data after the step of arranging the plurality of cells is completed, wherein the layout data includes a step of forming a gate of a MOS transistor, A method for designing a semiconductor device, which is mask data in a source / drain region forming step. 5. The method of designing a semiconductor device according to claim 1, wherein the upper limit area value is set based on an area of a resist applied on a cell in a manufacturing process of the semiconductor device. Design method. 6. A means for arranging a plurality of cells based on circuit information, wherein the means for arranging the plurality of cells comprises a means for reading an input upper limit area value, and a means for reading the upper limit area value read. A device for designing a semiconductor device, comprising: a unit that automatically divides an arrangement area of the plurality of cells based on the plurality of cells; and a unit that arranges each of the plurality of cells in the divided arrangement area. 7. The semiconductor device designing apparatus according to claim 6, wherein the means for reading the upper limit area value is capable of reading the input vacant widths in the X and Y directions. Equipment design equipment. 8. The device for designing a semiconductor device according to claim 6, wherein the means for automatically dividing the arrangement area of the plurality of cells comprises:
An arrangement area of the plurality of cells is obtained, a division number is determined based on the obtained arrangement area and the upper limit area value, and circuit constraints and logic constraints are satisfied based on the determined division number. Dividing the arrangement area of the plurality of cells to determine whether the divided arrangement area is a charge-up violation, the result of the determination, if the charge-up violation, in the upper limit area value of A device for designing a semiconductor device, which is capable of repeating processing from an input. 9. The semiconductor device design apparatus according to claim 6, wherein layout data can be output after the arrangement of the plurality of cells is completed, and the layout data includes a step of forming a gate of a MOS transistor, A semiconductor device design apparatus, which is mask data in a source / drain region forming step. 10. The semiconductor device design apparatus according to claim 6, wherein the upper limit area value can be set based on an area of a resist applied on a cell in a manufacturing process of the semiconductor device. Characteristic semiconductor device design device.