JPH065681B2 - Method for manufacturing semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, particularly a thin film field effect transistor (TFT). The present invention has a low interband level density, high dark resistance, and photoconductivity. It has a feature that it uses a small semiconductor and has a high on-current, a small off-current, and a small photoconductivity due to external incident light, so that external light such as switching elements such as image display devices and image sensors is inevitable. A TFT that can be used even in an environment where light is incident is easily and reliably obtained.

Structure of Conventional Example and Its Problems FIG. 1 shows a structural cross-sectional view of a typical thin film field effect transistor (TFT) using a hydrogen amorphous silicon (a-Si: H) semiconductor layer.

The manufacturing process of this TFT is shown below. First, a metal such as Cr is vapor-deposited on a substrate 1 such as glass, and etching is performed while leaving a portion to be the gate electrode 2. Next, the silicon nitride film 3 (hereinafter referred to as SiN) is deposited by plasma CVD to 0.1 to 0.5 μm,
An aSi: H film 5 having a thickness of 0.1 to 0.5 .mu.m and an n ⁺ doped aSi: H film 5 is continuously deposited on the order of 500 Å. Next, the portion to be left as a TFT is covered with a resist, and the remaining portion of n ⁺ aSi: H, a
Si: H is removed by etching.

Next, a metal such as Al is vapor-deposited, and the source 6 and drain 7 electrodes are patterned. Further, by using the Al electrodes 6 and 7 as a mask, the partial region 8 of n ⁺ aSi: H existing between both electrodes is etched to complete the structure of FIG. 1a.

However, the above-mentioned conventional example has the following problems. First, in manufacturing, it is difficult to completely remove the partial region 8 of the n ⁺ aSi: H layer 5 described above. Although aSi: H can be etched with a hydrofluoric acid / nitric acid-based solution, it has poor etching selectivity between the n ⁺ doped region 8 and the undoped region. Further, near the metal / semiconductor junction, abnormal high-speed etching occurs probably due to the action of the battery or the like through the etching solution. Therefore, as shown in the partially enlarged view (Fig. 2b), the partial region 9 of the aSi: H layer 4 which must be stored as the channel of the TFT tends to disappear. Further, when the etching is turned over, part of the n ⁺ layer 8 which must be completely removed remains and the OFF resistance does not become sufficiently large. Complete removal control of only the partial region 8 is extremely difficult as described above. If the etching is a little too small, the off resistance of the TFT is not sufficiently large, and if the etching is too large, the TFT operation itself disappears.

Next, there is a problem caused by the fact that aSi: H is a good photoconductive semiconductor. Good ON / O when the structure of Fig. 1a is dark
Even when the FF current ratio (normally 5 digits or more) is shown, photo-excited charges are generated when light is incident on the semiconductor portion from the outside, and the OFF resistance is reduced. Therefore, in order to block the incident light to the semiconductor portion, it is necessary to additionally provide the metal light shielding film 11 via the insulating film 10 as shown in FIG. This complicates the manufacturing process and is also the main cause of the yield reduction.

SUMMARY OF THE INVENTION Therefore, the present invention provides a method for reliably preventing etching of a channel portion, reducing an increase in OFF current when external light is incident, and easily and reliably manufacturing a TFT having good TFT characteristics. The purpose is to do.

According to the present invention, a gate electrode and a gate insulating film are formed on a substrate, and a first semiconductor layer having a silicon carbide layer containing hydrogen or a halogen group element is formed on the gate insulating film. A second semiconductor layer for ohmic contact comprising a silicon layer containing hydrogen or a halogen group element doped with impurities is formed on the first semiconductor layer, and the first and second semiconductor layers are selectively formed. And selectively forming source and drain electrodes on the second semiconductor layer, and selectively removing the second semiconductor layer on the first semiconductor layer using the source and drain electrodes as a mask. In addition, the TFT is manufactured by leaving the first semiconductor layer between the source and drain electrodes.

Description of Embodiments The present invention will be described in detail below with reference to the drawings using embodiments.

[Embodiment 1] FIG. 3 shows a first embodiment. The device of this example was manufactured as follows. First, 1000 Å of Cr is sputter-deposited on one main surface of the substrate 1 made of glass or the like, and is removed by etching except a desired portion to be left as the gate 2. Next, this substrate is placed in a plasma CVD apparatus, heated to a desired temperature, and then gas containing SiH ₄ and NH ₃ is introduced to carry out glow discharge decomposition to deposit a silicon nitride film 3 of 0.2 μm. After replacing the gas in the plasma CVD device, SiH ₄ and CH ₄ were replaced.
Is introduced at a desired mixing ratio, and the aSi _1-x C _x : H film 21 is deposited by 0.2 μm by glow discharge decomposition in this gas. Then, after gas replacement, SiH ₄ is introduced again to form aSi: H film 22 with 50
After 0 Å deposition, SiH ₄ and PH ₃ were introduced to deposit an n ⁺ aSi: H layer 23 doped with 0.5% phosphorus at 500 Å. Next, a desired region of the semiconductor layer deposited in the above step is left, and the other part is removed by plasma etching. (Layer 2 at this stage
2, 23 partial regions 22 'and 23' remain. ) Next, Al is vapor-deposited and patterned to form the source electrode 6 and the drain electrode 7. A formed after that
The structure of FIG. 3 is completed by removing the n ⁺ aSi: H and aSi: H partial regions 23 ′ and 22 ′ with a mixed solution of fluorinated nitric acid using the l electrode pattern.

The feature of the above process is that the aSi _1-x C _x film 21 has a strong resistance to the fluorinated nitric acid solution, and therefore the aSi: H film 23 ′, 2
The point is that the etching selectivity with 2'is large. Therefore, the disadvantage that the semiconductor layer is removed as illustrated in FIG. 1B is eliminated, and the layers 22 'and 23' for ensuring ohmic contact can be removed with extremely high selectivity.

Further, in the above step, the films 21, 22, and 23 can be continuously deposited and formed on the silicon nitride film 3 as the gate insulating film only by gas replacement, and the films 21, 22, and 23 are selectively etched simultaneously. Thus, a laminated pattern of the films 21, 22, and 23 can be formed, and the TFT manufacturing process is not complicated. And the source and drain electrodes 6 and 7
With the mask as a mask, the partial regions 22 'and 23' can be reliably removed, and the film 21 can be left between the source and drain electrodes 6 and 7, and the process at this time is not complicated at all.
As described above, according to the present invention, it is possible to manufacture the TFT of FIG. 3 easily and surely by effectively using the laminated deposition of the films, which is industrially very convenient.

The n ⁺ aSi: H layer 23 introduced in the present embodiment is for ensuring ohmic contact between the source 6 and drain 7 electrodes and the semiconductor layers 21 to 23, and the intrinsic layer 22 is n ⁺
After removing the partial layer 23 'of aSi: H, it is introduced to sufficiently remove P as an n-type impurity on the surface of the layer 21.

The drain current I _D vs. gate voltage V _D characteristics of the TFT manufactured according to this example are shown in the curves a and b in FIG. Curve a is the characteristic in the dark when no external light is incident, and curve b is 3000L _x
It is a characteristic when the outside light of is irradiated.

Curves c and d in the same figure are characteristics of the TFT manufactured by the method of the above-mentioned conventional example at dark and at 3000 L _x irradiation, and are shown for comparison.

The TFT manufactured according to the present embodiment has an O level compared to the conventional example even when external light does not enter (curves a and c).
The current at FF (V _G = 0) is small and the ON / OFF current ratio can be made larger. Furthermore, when irradiating with 3000 L _x of outside light, O
In contrast to the FF current increasing to about 100 nA, this embodiment is on the order of pA. In order to keep the OFF current at the time of incidence of external light small, it is necessary to provide a light shielding means in addition to the structure of FIG.
The structure shown in the figure can be used even when external light is incident.

Example 2 A TFT having the layer 22 of the previous example omitted was manufactured by the same method as that of the previous example shown in FIG. OFF during light irradiation
The outline of the current and voltage characteristics including the increase of the current was substantially the same as that of the previous example. However, the variation in the OFF current in the dark was slightly larger than that in the previous example, and the ON current was slightly smaller than that in the previous example.

[Example 3] By the same manufacturing method as in Example 1, TFTs in which the composition x of the amorphous silicon carbide layer 21 in Fig. 3 was changed were manufactured.

Compared to the conventional example (composition x = 0), the composition x is 1% and the partial layer 2
A clear advantage was found in the selective etching of 3'and 22 ', and a decrease in the photocurrent at the time of OFF was also recognized.

On the other hand, when x exceeds 70%, the gate voltage required to turn on the TFT becomes high and the practicality is lowered.

[Embodiment 4] FIG. 5 shows a sectional view of an apparatus according to a fourth embodiment. The difference from the first embodiment is that after the silicon nitride film 3 is deposited to a thickness of 0.4 μm, S
An a-Si: H layer 24 was deposited by 0.3 μm by plasma decomposition of iH ₄ , and then a silicon carbide layer 25 was deposited by 500 μm by decomposition of SiH ₄ and CH ₄ . The subsequent steps are the same as in Example 1. In the present embodiment, the a-SiH: layer 24 that can obtain good TFT characteristics is used as a channel, and the presence of the silicon carbide layer 25 causes the partial layers 23 'and 2 to be formed.
The complete selective removal of 2'is very easy, and the problem of disappearing the semiconductor layer between the source and drain illustrated in FIG. 1b has disappeared. Further, although the silicon carbide layer 25 is light-absorbing, since the photoconductivity is small, the OFF current at the time of light irradiation is reduced as compared with the conventional example.

Amorphous semiconductor aSi _1-x C _{x of} the TFT described in the above embodiment
The distribution of carbon composition x therein is shown in FIG. 6 as a function of distance d from the insulator-semiconductor interface. FIG. 10A shows the composition distribution of Example 1. A silicon carbide layer having a constant composition x is provided for 0 ≦ d ≦ d ₁ and aSi: H, d ₂ d is provided for x = 0 between d _{1 and} dd _2.
Between d ₃ is an n ⁺ -doped aSi: H layer. T of Example 2
In FT, the aSi: H layer between d _{1 and} dd ₂ is omitted.

FIG. 6b shows the composition distribution of the TFT of Example 4. 0d
aSi: H between d _{1 and} aSi _1-x C _x layer between d ₁ dd ₂ and d ₂ d
d ₃ between the aSi: H layer, aSi between d ₃ dd ₄ is that n ⁺ doped:
It is the H layer.

Although not specifically described as an example, the concentration distribution and other distributions illustrated in FIG. 7 using the same coordinate system as in FIG. 6 are also considered as one embodiment of the idea of the present invention.

In the semiconductor layer described above, crystallized silicon may be used as the amorphous silicon layer containing no carbon, and a halogen group may be used instead of hydrogen contained in the semiconductor.

Effects of the Invention As described above, according to the present invention, a silicon carbide layer containing hydrogen or a halogen group element is formed on a gate insulating film on a gate electrode, and an impurity for ohmic contact is further doped on the silicon carbide layer. After forming a silicon layer containing hydrogen or a halogen group element and selectively etching these layers, the source and drain electrodes formed on the silicon layer are used as a mask to selectively remove only the unnecessary silicon layer between both electrodes. That is, the silicon carbide layer and the silicon layer can be easily and continuously deposited and formed, and the silicon layer can be selectively and completely removed using an electrode mask. Further, according to the present invention, it is possible to completely prevent the etching of the channel portion of the TFT in the selective removal of the doped layer for ohmic contact, and to use the photoconduction of the external incident light without special light shielding means. A TFT with a small increase in OFF current
It is possible to easily manufacture without complicating the manufacturing process. Therefore, the present invention provides sufficient ON / OFF as a switching element for an image display device or an image reading device.
A TFT in which a large number of TFTs (10 ⁴ ) having a current ratio are integrated
This is a major industrial contribution to obtaining an array easily and with high yield.

[Brief description of drawings]

1a is a view showing a cross section of a TFT of a conventional example, FIG. 1b is a partially enlarged view of a channel portion of the TFT, which schematically shows a pattern of disappearance of a semiconductor, and FIG. 2 is a view for preventing incidence of external light. FIG. 3 is a sectional view of a conventional TFT in which light is shielded, FIG. 3 is a sectional view of a TFT in the first embodiment of the present invention, and FIG. Hour and 3000L _x
FIG. 5 is a diagram showing static characteristics during irradiation, FIG. 5 is a cross-sectional view showing a TFT of another embodiment of the present invention, and FIGS. 6a, 6b and 7a, b are gate insulating film / semiconductor interfaces (d = 0) amorphous aSi _1-x
Is a diagram illustrating an example of distribution of the composition of C _x. 1 ... Substrate, 2 ... Gate electrode, 3 ... Gate insulating film,
6, 7 ... Source / drain electrodes, 21 ... Amorphous silicon carbide film, 22 ... Non-doped aSi: H layer, 23 ... N ⁺ -doped aSi: H layer, 22 ', 23' ... aSi: H Selective removal area, 24 ... aSi: H layer, 25 ... amorphous silicon carbide layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ikunori Kobayashi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Shigenobu Shirai, 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 56) References JP-A-58-112365 (JP, A) JP-A-58-33872 (JP, A) JP-A-58-18966 (JP, A)

Claims (1)

[Claims] 1. A gate electrode and a gate insulating film are formed on a substrate, and a first semiconductor layer having a layer of silicon carbide containing hydrogen or a halogen group element is formed on the gate insulating film. A second semiconductor layer for ohmic contact comprising a hydrogen-containing or halogen-group-containing silicon layer doped with impurities is formed on one semiconductor layer, and the first and second semiconductor layers are selectively removed. Source and drain electrodes are selectively formed on the second semiconductor layer, and the second semiconductor layer on the first semiconductor layer is selectively removed using the source and drain electrodes as a mask. A method for manufacturing a semiconductor device, characterized in that the first semiconductor layer is left between the source and drain electrodes.