JPH0346374A - Thin film transistor - Google Patents

Thin film transistor

Info

Publication number
JPH0346374A
JPH0346374A JP18338289A JP18338289A JPH0346374A JP H0346374 A JPH0346374 A JP H0346374A JP 18338289 A JP18338289 A JP 18338289A JP 18338289 A JP18338289 A JP 18338289A JP H0346374 A JPH0346374 A JP H0346374A
Authority
JP
Japan
Prior art keywords
film
region
light
semiconductor film
amorphous semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18338289A
Other languages
Japanese (ja)
Inventor
Shoichiro Nakayama
中山 正一郎
Shigeru Noguchi
能口 繁
Keiichi Sano
佐野 景一
Hiroshi Iwata
岩多 浩志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP18338289A priority Critical patent/JPH0346374A/en
Publication of JPH0346374A publication Critical patent/JPH0346374A/en
Priority to US07/818,745 priority patent/US5231297A/en
Pending legal-status Critical Current

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  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To suppress an increase in a current by the irradiation with light by forming a noncrystalline semiconductor film of a polycrystallized region and the residual region of an amorphous semiconductor film, and providing the residual amorphous region corresponding to the position of a gate electrode film. CONSTITUTION:An insulating board 1, a gate electrode 2, a gate insulating film 3, an amorphous semiconductor film 4, a polycrystalline semiconductor film 6, an impurity implanted amorphous semiconductor layer 7, drain and source electrodes 8, 8, a passivation film 9 and a shielding film 10 are provided. In this case, the film 4 is formed of a polycrystallized region irradiated with a high energy beam to amorphous semiconductor and the residual region of the amorphous semiconductor film, and the residual region is provided corresponding to the position of the film 2. Accordingly, the amorphous region sensitive to light for forming a semiconductor operation channel can shield light projected from the side of the electrode 2 by the electrode 2, and even if the light is directed to the polycrystallized region having low sensitivity to the light which is not shielded, characteristic change can be suppressed. Thus, stable switching characteristic which is not affected by the influence of the light is obtained.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は非結晶半導体膜を備えた薄膜トランジスタの構
造に関する。゛ (ロ)従来の技術 従来から結晶半導体に代えて、非晶質、多結晶これらの
混晶半導体などの非結晶半導体を用いた薄膜トランジス
タ(以下TPTと略記する)が開発されてきた。
DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to the structure of a thin film transistor including an amorphous semiconductor film. (b) Prior Art Thin film transistors (hereinafter abbreviated as TPT) using non-crystalline semiconductors such as amorphous, polycrystalline and mixed semiconductors have been developed in place of crystalline semiconductors.

非結晶半導体のなかでも、非晶質半導体材料、特にアモ
ルファス・シリコン(以下a−Siと略記する)は、ト
ランジスタとしての半導体特性が安定しており、大面積
成膜が可能なプラズマCVD法が採用できる利点から、
大型基板へのTPTの大量形成に適している。
Among non-crystalline semiconductors, amorphous semiconductor materials, especially amorphous silicon (hereinafter abbreviated as a-Si), have stable semiconductor characteristics as transistors, and the plasma CVD method, which can form large-area films, has been used. From the advantages that can be adopted,
Suitable for mass formation of TPT on large substrates.

従って:近年では、アクティブマトリクス型液晶表示装
置のスイッチングトランジスタアレイ基板に上述のよう
なa −5iT F Tが搭載され、実用化に至ってい
る。
Therefore: In recent years, the above-described a-5iT F T has been mounted on a switching transistor array substrate of an active matrix liquid crystal display device, and has been put into practical use.

このようなTPTは、上述の如く、プラズマ反応の大面
積半導体膜形成の容易さといった利点をいかしたもので
あるが、同反応法によってゲート絶縁膜やパッシベーシ
ョン膜となる窒化シリコン(SiNx)膜や酸化シリコ
ン(Sin!>膜をも反応ガスを変えるだけで連続形成
できるという長所も利用している。
As mentioned above, this type of TPT takes advantage of the ease of forming large-area semiconductor films using plasma reactions. It also takes advantage of the fact that silicon oxide (Sin!) films can be formed continuously by simply changing the reaction gas.

従来のアクティブマトリクス型液晶表示装置、特に、所
謂液晶TVに於ては、液晶の電荷蓄積作用を利用して、
映像を表示しているため、1フレーム毎に液晶に充電さ
れた電荷は、lフレーム期間保持され続けなければなら
ないので、もしこの期間で電流リークにより液晶の保持
電圧が低下したならば、表示品質の劣化を招くことにな
る。
Conventional active matrix type liquid crystal display devices, especially so-called liquid crystal TVs, utilize the charge storage effect of liquid crystals to
In order to display images, the charge charged to the liquid crystal for each frame must be maintained for one frame period, so if the holding voltage of the liquid crystal decreases due to current leakage during this period, the display quality will deteriorate. This will lead to deterioration.

また、液晶TVとしては、バックライトを備えた光透過
型の液晶表示装置が一般的であるが、上述のTPTのa
−5i材料は、太陽電池材料としても使用されるように
光に対して過敏であるため、光■射下で0FFii流が
増大してしまう不都合があった(特開昭61−1458
69号)。
In addition, as a liquid crystal TV, a light transmission type liquid crystal display device equipped with a backlight is common, but the above-mentioned TPT a
Since the -5i material is sensitive to light as it is also used as a solar cell material, it has the disadvantage that the 0FFii current increases under light irradiation (Japanese Patent Application Laid-Open No. 61-1458
No. 69).

このような光対策としては、従来からTPTの半導体膜
のa−5iのバンドギャップを大きくしたり、あるいは
、a−5iを完全に被うような遮光膜を設けるなどが提
案されている。しかし、前者の対策では本質的な膜質の
劣化、後者のそれでは戒嗅プロセスの追加による製造歩
留まりの低下は避けられなかった。
As measures against such light, it has been proposed to increase the a-5i band gap of the TPT semiconductor film, or to provide a light-shielding film that completely covers the a-5i. However, the former measure inevitably deteriorates the film quality, while the latter inevitably reduces the manufacturing yield due to the addition of an odor process.

(ハ)発明が解決しようとする課題 本発明は、上述の点に鑑みてなされたものであす、半導
体膜に有効な光対策を施して、光照射下の毛流増加が抑
制できるTPTを提供するものである。
(c) Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned points, and provides a TPT that can suppress the increase in hair flow under light irradiation by applying effective light countermeasures to the semiconductor film. It is something to do.

(ニ)課題を解決するための手段 本発明のTPTは、絶縁基板上に、ゲート電極膜、絶縁
膜、非結晶半導体膜、及びドレイン電極膜並びにソース
を極膜を積層Fil戊したTPTであって、上記非結晶
半導体膜が、非晶質半導体に高エネルギー線照射した多
結晶化領域と非晶質半導体膜の残存領域からなり、該残
存非晶質領域をゲート電極膜位置に対応して設けたもの
である。
(d) Means for Solving the Problems The TPT of the present invention is a TPT in which a gate electrode film, an insulating film, an amorphous semiconductor film, a drain electrode film, and a source electrode film are stacked on an insulating substrate. The amorphous semiconductor film is composed of a polycrystalline region obtained by irradiating the amorphous semiconductor with high-energy rays and a remaining region of the amorphous semiconductor film, and the remaining amorphous region is arranged in a manner corresponding to the position of the gate electrode film. It was established.

(ホ)作用 本発明のTPTによれば、非結晶半導体膜の内ゲート′
2It極膜位置に対応した領域を非晶質領域、その他の
領域を多結晶化領域としたので、ゲートを極側からの光
照射に対して、半導体動作チャンネルをなす光に敏感な
非晶質領域はゲートを極で遮光され、この他の遮光され
ない光に対して鈍感な多結晶化領域では光電流の発生は
殆どない。
(E) Function According to the TPT of the present invention, the inner gate ' of the amorphous semiconductor film is
The region corresponding to the 2It pole film position is an amorphous region, and the other regions are polycrystalline regions, so that when the gate is irradiated with light from the pole side, it becomes a light-sensitive amorphous region that forms a semiconductor operating channel. The region is shielded from light by the gate pole, and almost no photocurrent is generated in the polycrystalline region, which is insensitive to other unshielded light.

(へ)実施例 第1図に本発明のTPTの一実施例の構造断面図を示し
、第2図にそのプロセス断面図を示す。
(F) Embodiment FIG. 1 shows a structural sectional view of an embodiment of the TPT of the present invention, and FIG. 2 shows a process sectional view thereof.

第1図において、(1)は絶縁性基板、(2)はゲート
電極、(3)はゲート絶縁膜、〈4)は非晶質半導体膜
、(6)は多結晶半導体膜、(7)は不純物導入非晶質
半導体膜、<8! (8)はドレイン電極及びソース電
極、(9)はパッシベーション膜、00)は遮光膜であ
る。
In Figure 1, (1) is an insulating substrate, (2) is a gate electrode, (3) is a gate insulating film, (4) is an amorphous semiconductor film, (6) is a polycrystalline semiconductor film, (7) is an amorphous semiconductor film, and (7) is an amorphous semiconductor film. is an impurity-introduced amorphous semiconductor film, <8! (8) is a drain electrode and a source electrode, (9) is a passivation film, and 00 is a light shielding film.

第1図のTPTが特徴とするところは、半導体膜が多結
晶半導体膜(6)領域と非晶質半導体膜(4)領域とか
らなり、該非晶質半導体膜(4)領域をゲート電極(2
)位置に対応して設けた点にある。
The TPT shown in FIG. 1 is characterized by that the semiconductor film consists of a polycrystalline semiconductor film (6) region and an amorphous semiconductor film (4) region, and the amorphous semiconductor film (4) region is connected to the gate electrode ( 2
) is located at a point provided corresponding to the position.

次に、第2図(a)〜(e)のプロセス図に基づき、製
造プロセスを説明する。
Next, the manufacturing process will be explained based on the process diagrams shown in FIGS. 2(a) to 2(e).

まず、ガラス板を成形してなる透明基板(1)上にゲー
ト電極(2)を形成パターニングする(第2図(a)]
。次に、SiNxからなるゲート絶縁膜(3)とa−5
iからなる非晶質半導体膜(4)を形成した後、この非
晶質半導体膜(4)を島状にパターニングする(同図(
b))。
First, a gate electrode (2) is formed and patterned on a transparent substrate (1) made of a glass plate (Fig. 2 (a)).
. Next, a gate insulating film (3) made of SiNx and a-5
After forming an amorphous semiconductor film (4) consisting of i, this amorphous semiconductor film (4) is patterned into an island shape (see FIG.
b)).

次に透明基板側からレーザー光などの高エネルギー線(
5)で非晶質半導体膜(4)を照射する。この時ゲート
を極(2)がマスクとなり、非晶質半導体膜(4)は後
工程のソース、ドレインコンタクトに相当する部分にの
み照射される[同図(C)]。
Next, from the transparent substrate side, high-energy rays such as laser light (
In step 5), the amorphous semiconductor film (4) is irradiated. At this time, the gate pole (2) serves as a mask, and only the portions of the amorphous semiconductor film (4) corresponding to the source and drain contacts in the subsequent process are irradiated [FIG. 4(C)].

このようにセルファラインで、高エネルギー線照射され
た非晶質半導体膜(4)領域はアニール効果によって多
結晶化され、多結晶半導体膜(6)領域となる。
In this manner, the amorphous semiconductor film (4) region irradiated with high-energy rays is polycrystallized by the annealing effect and becomes a polycrystalline semiconductor film (6) region.

この時の高エネルギー線(5)としては1例えば、Xe
Clエキシマレーザ−が使用でき、この場合には、10
0〜250 mJ/cm’のエネルギー条件が好ましい
。斯して得られる多結晶半導体膜(6)領域では、導電
率の向上と光感度の低下が確認できる。
At this time, the high energy ray (5) is 1, for example, Xe
A Cl excimer laser can be used, in this case 10
Energy conditions of 0-250 mJ/cm' are preferred. In the thus obtained polycrystalline semiconductor film (6) region, it can be confirmed that the conductivity is improved and the photosensitivity is reduced.

その後、燐を導入したn”a−5iからなる不純物導入
非晶質半導体膜(7)、ソース電極並びにドレイン電極
(8)(8)を形成する(同図(d))。
Thereafter, an impurity-doped amorphous semiconductor film (7) made of n''a-5i doped with phosphorus, a source electrode, and a drain electrode (8) (8) are formed (FIG. 4(d)).

なお、本実施例では、不純物導入非晶質半導体膜i7)
形成を上述の高エネルギー線(5)照射後に行ったが、
これの照射前でも可能である。
Note that in this example, the impurity-introduced amorphous semiconductor film i7)
The formation was carried out after the above-mentioned high energy beam (5) irradiation, but
This is possible even before irradiation.

その後、パッシベーション膜(9)及び遮光膜00)を
積層形成し、素子は完成する(同図(e))。
Thereafter, a passivation film (9) and a light shielding film 00) are laminated to complete the device (FIG. 2(e)).

斯して得られるTPTに於ては、上述のレーザーアニー
ルによる多結晶半導体膜(p−5i)(6)領域のダレ
インサイズは100人〜5000人であり、暗状態と光
照射状態での導電率の比σph/σ6が2桁以下になる
。これは、アニールされない非晶質半導体膜(a−5i
)(4)領域のそれが5桁以上であるのに比べて、導電
率の向上が認められ、光感度の低下も理解できる。
In the TPT obtained in this way, the dale size of the polycrystalline semiconductor film (p-5i) (6) region by laser annealing described above is 100 to 5000, and the diameter is 100 to 5000 in the dark state and in the light irradiation state. The conductivity ratio σph/σ6 becomes two digits or less. This is an amorphous semiconductor film (a-5i
) (4) The improvement in electrical conductivity is observed compared to that in the region (4), which is more than 5 orders of magnitude, and the decrease in photosensitivity can also be understood.

上述の実施例によれば、ゲート電極(2)や遮光膜(1
0)で遮光されない半導体部分のみを多結晶半導体膜(
6)とすることにより、光を受けないチャンネルのa−
5i領域で0N10FF比が大きいTPTを実現しなが
ら、光を受けるチャンネル外の部分のp−5i領域で光
に影響されないTPT特性を得ている。
According to the above embodiment, the gate electrode (2) and the light shielding film (1
Polycrystalline semiconductor film (
6), the a− of the channel that does not receive light
While realizing a TPT with a large 0N10FF ratio in the 5i region, a TPT characteristic that is not affected by light is obtained in the p-5i region outside the channel that receives light.

(トノ発明の効果 本発明のTPTは、非結晶半導体膜の内ゲート電極膜位
置に対応した領域を非晶質領域、その他の領域を多結晶
化領域としたので、ゲート電極側からの光照射に対して
、半導体動作チャンネルをなす光に敏感な非晶質領域は
ゲート電極で遮光できると共に、遮光されない光感度の
低い多結晶化領域に光照射があっても特性変化を抑制で
きる。
(Effects of the Invention) In the TPT of the present invention, the region of the amorphous semiconductor film corresponding to the gate electrode film position is an amorphous region, and the other regions are polycrystalline regions, so that light irradiation from the gate electrode side On the other hand, the light-sensitive amorphous region forming the semiconductor operating channel can be shielded from light by the gate electrode, and even if the unshielded polycrystalline region with low photosensitivity is irradiated with light, changes in characteristics can be suppressed.

従って、本発明によれば、光照射に影響されない安定し
たスイッチング特性を得るTPTが実現できる。
Therefore, according to the present invention, it is possible to realize a TPT that has stable switching characteristics that are not affected by light irradiation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明TPTの一実施例の断面図、第2図(a
)乃至(e)は第1図のTPTの製造プロセスを示す断
面図である。 (1)・・・絶縁性基板、(2)・・・ゲート1を極、
(3)・・・ゲート絶縁膜、〈4)・・・非晶質半導体
膜、(5)・・・高エネルギー線、(6)・・・多結晶
半導体膜、(7)・・・不純物導入非晶質半導体膜、(
8)・・・ソース、ドレイン電極、(9)パッシベーシ
ョン膜、(lO)・・・遮光膜。
Figure 1 is a sectional view of one embodiment of the TPT of the present invention, and Figure 2 (a
) to (e) are cross-sectional views showing the manufacturing process of the TPT shown in FIG. 1. (1)...Insulating substrate, (2)...Gate 1 as a pole,
(3)...gate insulating film, <4)...amorphous semiconductor film, (5)...high energy rays, (6)...polycrystalline semiconductor film, (7)...impurity Introducing amorphous semiconductor film, (
8)...source, drain electrode, (9) passivation film, (lO)...light shielding film.

Claims (1)

【特許請求の範囲】[Claims] (1)絶縁基板上に、ゲート電極膜、絶縁膜、非結晶半
導体膜、及びドレイン電極膜並びにソース電極膜を積層
構成する薄膜トランジスタに於て、上記非結晶半導体膜
は、非晶質半導体に高エネルギー線照射した多結晶化領
域と非晶質半導体膜の残存領域とからなり、該残存非晶
質領域をゲート電極膜位置に対応して設けたことを特徴
とする薄膜トランジスタ。
(1) In a thin film transistor in which a gate electrode film, an insulating film, an amorphous semiconductor film, a drain electrode film, and a source electrode film are laminated on an insulating substrate, the amorphous semiconductor film has a high 1. A thin film transistor comprising a polycrystalline region irradiated with energy rays and a remaining region of an amorphous semiconductor film, the remaining amorphous region being provided corresponding to the position of a gate electrode film.
JP18338289A 1989-07-14 1989-07-14 Thin film transistor Pending JPH0346374A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP18338289A JPH0346374A (en) 1989-07-14 1989-07-14 Thin film transistor
US07/818,745 US5231297A (en) 1989-07-14 1992-01-07 Thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18338289A JPH0346374A (en) 1989-07-14 1989-07-14 Thin film transistor

Publications (1)

Publication Number Publication Date
JPH0346374A true JPH0346374A (en) 1991-02-27

Family

ID=16134793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18338289A Pending JPH0346374A (en) 1989-07-14 1989-07-14 Thin film transistor

Country Status (1)

Country Link
JP (1) JPH0346374A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6194740B1 (en) * 1997-07-16 2001-02-27 Semiconductor Energy Laboratory Co., Ltd. Optical sensor
US6323069B1 (en) 1992-03-25 2001-11-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor using light irradiation to form impurity regions
WO2003088331A1 (en) * 2002-04-15 2003-10-23 Advanced Lcd Technologies Development Center Co., Ltd. Semiconductor device having semiconductor thin-films of different crystallinities, substrate thereof, process for producing these, liquid crystal display unit and process for producing the same
US6787808B1 (en) 1997-07-16 2004-09-07 Semiconductor Energy Laboratory Co., Ltd. Optical sensor
JP2008098638A (en) * 2006-10-09 2008-04-24 Korea Electronics Telecommun Thin-film transistor having chalcogenide layer, and manufacturing method therefor

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323069B1 (en) 1992-03-25 2001-11-27 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor using light irradiation to form impurity regions
US6569724B2 (en) 1992-03-25 2003-05-27 Semiconductor Energy Laboratory Co., Ltd. Insulated gate field effect transistor and method for forming the same
US6887746B2 (en) 1992-03-25 2005-05-03 Semiconductor Energy Lab Insulated gate field effect transistor and method for forming the same
US6194740B1 (en) * 1997-07-16 2001-02-27 Semiconductor Energy Laboratory Co., Ltd. Optical sensor
US7176495B2 (en) 1997-07-16 2007-02-13 Semiconductor Energy Laboratory Co., Ltd. Optical sensor
US6787808B1 (en) 1997-07-16 2004-09-07 Semiconductor Energy Laboratory Co., Ltd. Optical sensor
JPWO2003088331A1 (en) * 2002-04-15 2005-08-25 株式会社 液晶先端技術開発センター SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR THIN FILMS WITH DIFFERENT CRYSTALLINES, ITS SUBSTRATE, AND ITS MANUFACTURING METHOD
US7087505B2 (en) 2002-04-15 2006-08-08 Advanced Lcd Technologies Development Center Co., Ltd. Semiconductor device including semiconductor thin films having different crystallinity, substrate of the same, and manufacturing method of the same, and liquid crystal display and manufacturing method of the same
WO2003088331A1 (en) * 2002-04-15 2003-10-23 Advanced Lcd Technologies Development Center Co., Ltd. Semiconductor device having semiconductor thin-films of different crystallinities, substrate thereof, process for producing these, liquid crystal display unit and process for producing the same
CN1306559C (en) * 2002-04-15 2007-03-21 株式会社液晶先端技术开发中心 Semiconductor device including semiconductor thin films having different crystallinity, substrate of the same, and manufacturing method of the same, and liquid crystal display and manufacturing method
US7352002B2 (en) 2002-04-15 2008-04-01 Advanced Lcd Technologies Development Center Co., Ltd. Semiconductor device including semiconductor thin films having different crystallinity, substrate of the same, and manufacturing method of the same, and liquid crystal display and manufacturing method of the same
JP4616557B2 (en) * 2002-04-15 2011-01-19 株式会社 日立ディスプレイズ Thin film semiconductor device substrate manufacturing method and liquid crystal display device manufacturing method using the same
JP2008098638A (en) * 2006-10-09 2008-04-24 Korea Electronics Telecommun Thin-film transistor having chalcogenide layer, and manufacturing method therefor

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