JPH0542833B2 - - Google Patents

Info

Publication number
JPH0542833B2
JPH0542833B2 JP20707183A JP20707183A JPH0542833B2 JP H0542833 B2 JPH0542833 B2 JP H0542833B2 JP 20707183 A JP20707183 A JP 20707183A JP 20707183 A JP20707183 A JP 20707183A JP H0542833 B2 JPH0542833 B2 JP H0542833B2
Authority
JP
Japan
Prior art keywords
film
semiconductor film
amorphous silicon
semiconductor
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP20707183A
Other languages
Japanese (ja)
Other versions
JPS6098680A (en
Inventor
Tsuneo Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP20707183A priority Critical patent/JPS6098680A/en
Publication of JPS6098680A publication Critical patent/JPS6098680A/en
Publication of JPH0542833B2 publication Critical patent/JPH0542833B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78663Amorphous silicon transistors
    • H01L29/78669Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Description

【発明の詳細な説明】 本発明は、オン電流が大きくとれ、動作速度の
早い電界効果型薄膜トランジスタの実現に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the realization of a field-effect thin film transistor with a large on-current and high operating speed.

近年、ガラスなどな絶縁性基板上に形成できる
薄膜トランジスタの開発が各所で盛んである。絶
縁性基板上に、薄膜トランジスタからなるスイツ
チ素子をアレイ状に設けたアクテイブマトリクス
型の液晶、エレクトロクロミツク、エレクトロル
ミネツセンスなどの表示装置は、画素間のクロス
トークが無く、高速動作が可能なのでTV画像な
どの表示を可能にする。薄膜トランジスタに用い
る半導体膜としては、プラズマCVD法などによ
つて、ガラスなどの基板上に低温で大面積かつ安
価に形成できる水素化非晶質シリコン膜やフツ素
化非晶質シリコン膜などが有望とされている。
In recent years, development of thin film transistors that can be formed on insulating substrates such as glass has been active in various places. Active matrix liquid crystal, electrochromic, and electroluminescent display devices, in which switch elements made of thin film transistors are arranged in an array on an insulating substrate, have no crosstalk between pixels and are capable of high-speed operation. Enables display of TV images, etc. Promising semiconductor films for use in thin film transistors include hydrogenated amorphous silicon films and fluorinated amorphous silicon films, which can be formed at low temperatures, over a large area, and at low cost, on substrates such as glass using plasma CVD methods. It is said that

しかし、一方これら非晶質シリコン膜で形成し
た薄膜トランジスタで得られる電界効果移動度は
0.1〜1cm2(V・sec)なので、10V程度の動作電
圧で10-5A以上で電流を得られるトランジスタの
実現は困難である。この為、動作周波数が数10K
Hz以上の回路を非晶質シリコンのトランジスタで
実現するのは困難とされていた。非晶質シリコン
薄膜トランジスタは、アクテイブマトリクス型表
示装置の画素毎のスイツチトランジスタとしては
充分な動作速度を有するものの、数MHz以上の動
作周波数を要求される、TV画像表示用の周辺回
路の適用には不充分な動作速度である。従来の方
法では、この種の周辺回路は単結晶シリコン基板
上に形成したMOSICを用い、表示装置との間を
数百ケ所の端子で接続してアクテイブマトリクス
型表示装置は、 (1) 回路接続の費用が安価にできない (2) 周辺回路の部分をコンパクトにできない (3) 実装後の信頼性が劣る。
However, on the other hand, the field effect mobility obtained with thin film transistors formed using these amorphous silicon films is
Since it is 0.1 to 1 cm 2 (V·sec), it is difficult to realize a transistor that can obtain a current of 10 −5 A or more with an operating voltage of about 10 V. For this reason, the operating frequency is several tens of kilometres.
It was considered difficult to implement circuits with frequencies higher than Hz using amorphous silicon transistors. Although amorphous silicon thin film transistors have sufficient operating speed as switch transistors for each pixel in active matrix display devices, they are not suitable for use in peripheral circuits for TV image display, which require an operating frequency of several MHz or more. Insufficient operating speed. In the conventional method, this type of peripheral circuit uses a MOSIC formed on a single-crystal silicon substrate and is connected to the display device through several hundred terminals. (2) The peripheral circuitry cannot be made compact (3) The reliability after mounting is poor.

などの欠点を持つていた。It had some drawbacks.

非晶質シリコン薄膜トランジスタは、ガラス基
板上に形成した、光などのセンサーとしても応用
が期待されているが、この場合も周辺回路との接
続の問題は、表示装置の事情と同様である。
Amorphous silicon thin film transistors are also expected to be used as light sensors formed on glass substrates, but in this case as well, the problem of connection with peripheral circuits is similar to that of display devices.

本発明の目的は、動作速度の速い薄膜トランズ
シタを実現することにより、上記のごとき従来の
欠点を無くして、同一絶縁性基板上に、表示装置
あるいは、センサーとそれらの周辺回路を同時に
設ける手段を提供することである。
An object of the present invention is to eliminate the above-mentioned conventional drawbacks by realizing a thin film transistor with high operating speed, and to provide a means for simultaneously providing a display device or a sensor and its peripheral circuits on the same insulating substrate. It is to provide.

以下、実施例に基づいて、図面により本発明を
詳細に説明する。第1図aは、本発明の電界効果
型の薄膜トランジスタの、チヤンネル領域の断面
での、フラツトバンド状態の、バンド構造を示す
図である。第1図aで、1はゲート電極金属、2
はゲート絶縁膜、3は禁制帯幅Eg2、厚さ1000Å
以上の第二半導体膜で、Eg1>Eg2である。Ec1
は、Ev1は第一の半導体膜3のそれぞれ伝導帯
端、価電子帯端のエネルギーであり、Ec2、Ev2
は第二の半導体膜4の、それぞれ、伝導帯端、価
電子帯端のエネルギーである。EFGはゲート電
極1のフエルミレベル、EFは半導体膜3,4に
共通したフエルミレベルである。1にゲート電極
金属の材料の一例としては、スパツタ法、真空蒸
着法などで形成される、アルミニウム、クロム、
モリブデン等が用いられ、厚さは、通常500〜
3000Åである。2のゲート絶縁膜は、スパツタ
法、真空蒸着法、プラズマCVD法などで形成さ
れる、二酸化シリコン、窒化シリコン等が用いら
れ、厚さは通常500〜3000Åである。
Hereinafter, the present invention will be explained in detail based on examples and drawings. FIG. 1a is a diagram showing a band structure in a flat band state in a cross section of a channel region of a field effect thin film transistor of the present invention. In Figure 1a, 1 is the gate electrode metal, 2
is the gate insulating film, 3 is the forbidden band width Eg 2 , and the thickness is 1000 Å
In the above second semiconductor film, Eg 1 >Eg 2 . Ec 1
Ev 1 is the energy at the conduction band edge and valence band edge of the first semiconductor film 3, respectively, and Ec 2 and Ev 2
are the energies of the conduction band edge and the valence band edge of the second semiconductor film 4, respectively. EFG is the Fermi level of the gate electrode 1, and EF is the Fermi level common to the semiconductor films 3 and 4. 1. Examples of gate electrode metal materials include aluminum, chromium, etc. formed by sputtering, vacuum deposition, etc.
Molybdenum etc. are used, and the thickness is usually 500~
It is 3000Å. The gate insulating film 2 is formed by sputtering, vacuum evaporation, plasma CVD, etc., and is made of silicon dioxide, silicon nitride, etc., and has a thickness of usually 500 to 3000 Å.

本発明の薄膜トランジスタはガラスなどの、単
結晶ではない絶縁性基板上に形成されるので、3
および4の半導体膜としては、プラズマCVD法、
光CVD法などで、500℃以下の基板上に形成でき
る、非晶質あるいは微結晶化半導体膜が用いられ
る。特に非晶質シリコンはプラズマCVD法、
CVD法などで形成すると、禁制帯内の局在準位
密度が1017/cm3・ev以下の良好な半導体膜が得ら
れることが知られているので本発明に用いる半導
体膜として適している。非晶質半導体の禁制帯幅
は、膜の形成方法によつて大きくも小さくもでき
ることが知られている。即ち、プラズマCVD法
で形成した非晶質シリコンを基準に考えると、炭
素、窒素、酵素を非晶質シリコン中に不純物とし
て混入すると禁制帯幅を大きくすることができ
る。逆に、ゲルマニウム、スズ等を非晶質シリコ
ン中に不純物として混入すると禁制帯幅を小さく
することができる。更に、プラズマCVD法によ
れば非晶質シリコンと100Å程度の結晶の混ざり
あつた微結晶化シリコン膜を形成でき、これは非
晶質シリコン膜よりも小さな禁制帯幅を持つこと
が知られている。従つて、半導体膜3,4の組合
わせとしては種々可能である。例えば (1) 半導体膜3として、微結晶シリコン 半導体膜4として、非晶質シリコン (2) 半導体膜3として、非晶質シリコン 半導体膜4として、窒素を含む非晶質シリコ
ン (3) 半導体膜3として、ゲルマニウムを含む非晶
質シリコン 半導体膜4として、非晶質シリコン (4) 半導体膜3として、ゲルマニウムを含む非晶
質シリコン、半導体膜4として、窒素を含む非
晶質シリコン などがある。
Since the thin film transistor of the present invention is formed on an insulating substrate such as glass that is not a single crystal,
And as the semiconductor film of 4, plasma CVD method,
An amorphous or microcrystalline semiconductor film is used, which can be formed on a substrate at 500°C or lower using a photo-CVD method or the like. Especially for amorphous silicon, plasma CVD method,
It is known that a good semiconductor film with a localized level density in the forbidden band of 10 17 /cm 3 ·ev or less can be obtained when formed by a CVD method, so it is suitable as a semiconductor film for use in the present invention. . It is known that the forbidden band width of an amorphous semiconductor can be made larger or smaller depending on the film formation method. That is, when considering amorphous silicon formed by plasma CVD as a standard, the forbidden band width can be increased by mixing carbon, nitrogen, and enzymes as impurities into the amorphous silicon. Conversely, if germanium, tin, or the like is mixed into amorphous silicon as an impurity, the forbidden band width can be reduced. Furthermore, the plasma CVD method can form a microcrystalline silicon film that is a mixture of amorphous silicon and crystals of about 100 Å, which is known to have a smaller bandgap than an amorphous silicon film. There is. Therefore, various combinations of the semiconductor films 3 and 4 are possible. For example, (1) Microcrystalline silicon as the semiconductor film 3 Amorphous silicon as the semiconductor film 4 (2) Amorphous silicon as the semiconductor film 3 Amorphous silicon containing nitrogen as the semiconductor film 4 (3) Semiconductor film 3, amorphous silicon containing germanium; semiconductor film 4, amorphous silicon (4) semiconductor film 3, amorphous silicon containing germanium; semiconductor film 4, amorphous silicon containing nitrogen, etc. .

次に、本薄膜トランジスタの動作について説明
する。第1図bは、第1図aの薄膜トランジスタ
のゲート電極に正電圧を加えてオン状態としたと
きのバンド図を示す。半導体層3の伝導帯に誘起
された電子は、厚さ150Å以下の非常に薄い領域
に閉じ込められる。この為、半導体層3の厚さ方
向の電子の運動は量子化され、半導体層3の伝導
帯上の電子は二次元電子ガスとして振るまう。特
に、半導体層3の膜厚が薄くなるほど、量子化さ
れたエネルギー順位は大きく分離され、熱的なエ
ネルギー程度では電子が高いエネルギー順位へ遷
移されにくくなり、二次元電子ガス状態が維持さ
れやすくなる。二次元電子ガスの状態密度は、伝
導帯端では0で、一定のエネルギー△Eだけ上の
所から有限の0でない値を取り、二次元電子ガス
化していない場合と比べ、大きな自由電子密度を
得る。本発明における半導体層3は、基本的には
エネルギーバンドを持つものであれば良い。しか
し、実際半導体層3を作成するにあたり、エネル
キーバンドギヤツプとして形成可能な膜厚は、例
えば半導体原子としてSiを使用する場合は、Siの
原子数層分の厚さとして10Å程度の膜厚となる。
また、非晶質物質中の伝導帯を流れる電子は伝導
帯からのエネルギー差が大きな程、不規則な原子
配列によるポテンシヤルから受ける影響が小さく
なり、大きなモビリテイー(>10cm2/v・sec)
を有する。こうして、電子濃度とモビリテイーが
大きな第1図bのトランジスタは大きな電流を流
せるので、高速で動作する。室温付近で二次元電
子ガスが得られる条件は、第1図bで△E+△
Ecが0.3eV以上で、半導体層3の厚さが150Å以
下と薄い場合である。価電子帯側の正孔について
も、電子と同様二次元ガスを形成し得るが、こち
らは、トランジスタのソース、ドレインにn型層
を設けることにより、伝導に寄与しないようにで
きる。
Next, the operation of this thin film transistor will be explained. FIG. 1b shows a band diagram when a positive voltage is applied to the gate electrode of the thin film transistor of FIG. 1a to turn it on. Electrons induced in the conduction band of the semiconductor layer 3 are confined in a very thin region with a thickness of 150 Å or less. Therefore, the movement of electrons in the thickness direction of the semiconductor layer 3 is quantized, and the electrons on the conduction band of the semiconductor layer 3 behave as a two-dimensional electron gas. In particular, as the thickness of the semiconductor layer 3 becomes thinner, the quantized energy levels become more separated, and it becomes difficult for electrons to transition to higher energy levels with thermal energy, making it easier to maintain a two-dimensional electron gas state. . The density of states of a two-dimensional electron gas is 0 at the conduction band edge, and takes a finite non-zero value from a certain energy △E above, and has a large free electron density compared to the case where it is not converted into a two-dimensional electron gas. obtain. The semiconductor layer 3 in the present invention basically only needs to have an energy band. However, in actually creating the semiconductor layer 3, the film thickness that can be formed as an energy band gap is, for example, when using Si as semiconductor atoms, a film thickness of about 10 Å, which is the thickness of several layers of Si atoms. becomes.
In addition, the larger the energy difference from the conduction band for electrons flowing through the conduction band in an amorphous material, the less influenced by the potential due to irregular atomic arrangement, and the greater the mobility (>10cm 2 /v・sec).
has. Thus, the transistor of FIG. 1b, which has a large electron concentration and mobility, can carry a large current and therefore operates at high speed. The conditions for obtaining a two-dimensional electron gas near room temperature are △E+△ in Figure 1b.
This is the case when Ec is 0.3 eV or more and the thickness of the semiconductor layer 3 is as thin as 150 Å or less. Although holes on the valence band side can also form a two-dimensional gas like electrons, they can be prevented from contributing to conduction by providing an n-type layer at the source and drain of the transistor.

以上の説明のごとく本発明による、薄膜トラン
ジスタは、ゲート電圧の印加により、チヤンネル
のコンダクタンスを制御でき、かつ大きなオン電
流が流せ高速で動作する。
As described above, the thin film transistor according to the present invention can control the channel conductance by applying a gate voltage, can flow a large on-current, and operates at high speed.

第2図は、本発明の薄膜トランジスタの第一の
実施例の構造の断面を示す図である。第2図で、
5はガラスなどの絶縁性基板、6はアルミニウ
ム、クロム等のゲート電極、7は二酸化シリコ
ン、チツ化シリコン等よりなるゲート絶縁膜、8
は微結晶化シリコン等よりなる厚さ150Å以下の
第一の半導体膜、9,10はそれぞれソース、ド
レイン接触の為のn+非晶質シリコン膜、11,
12はそれぞれソース、ドレイン電極、13は、
半導体膜8より大きなバンドギヤツプを有する第
二の半導体膜である非晶質シリコン膜、14は保
護用絶縁膜で二酸化シリコン、チツ化シリコン等
よりなる。第2図の構造では、ゲート電極6、ゲ
ート絶縁膜7、第一の半導体膜8を形成後、ソー
ス、ドレイン電極9,10,11,12を形成
し、その後で、第二の半導体膜13、保護膜14
を形成している。
FIG. 2 is a diagram showing a cross section of the structure of the first embodiment of the thin film transistor of the present invention. In Figure 2,
5 is an insulating substrate such as glass; 6 is a gate electrode made of aluminum, chromium, etc.; 7 is a gate insulating film made of silicon dioxide, silicon nitride, etc.;
9 and 10 are n + amorphous silicon films for source and drain contact, respectively; 11,
12 are source and drain electrodes, 13 are
The amorphous silicon film 14, which is a second semiconductor film having a larger band gap than the semiconductor film 8, is a protective insulating film made of silicon dioxide, silicon nitride, or the like. In the structure shown in FIG. 2, after forming the gate electrode 6, the gate insulating film 7, and the first semiconductor film 8, the source and drain electrodes 9, 10, 11, and 12 are formed, and then the second semiconductor film 13 is formed. , protective film 14
is formed.

第3図は、本発明の薄膜トランジスタの第二の
実施例の構造の断面を示す図である。第3図で、
15はガラスなどの絶縁性基板、16はゲート電
極、17はゲート絶縁膜、18は非晶質シリコン
よりなる厚さ150A以下の第一の半導体膜、19,
20はそれぞれソース、ドレイン接触の為のn+
非晶質シリコン膜、21,22はそれぞれソー
ス、ドレイン電極、23は第二の半導体膜で窒素
を不純物として含む非晶質シリコン膜、24は保
護用絶縁膜である。第3図の構造では、ゲート電
極16、ゲート絶縁膜17、ソース・ドレイン電
極19,20,21,22を形成し、その後、第
1の半導体膜18、第2の半導体膜23、保護膜
24を形成する。
FIG. 3 is a diagram showing a cross section of the structure of a second embodiment of the thin film transistor of the present invention. In Figure 3,
15 is an insulating substrate such as glass, 16 is a gate electrode, 17 is a gate insulating film, 18 is a first semiconductor film made of amorphous silicon and having a thickness of 150A or less, 19,
20 are n + for source and drain contact respectively
Amorphous silicon films 21 and 22 are source and drain electrodes, respectively, 23 is a second semiconductor film which is an amorphous silicon film containing nitrogen as an impurity, and 24 is a protective insulating film. In the structure shown in FIG. 3, the gate electrode 16, the gate insulating film 17, the source/drain electrodes 19, 20, 21, and 22 are formed, and then the first semiconductor film 18, the second semiconductor film 23, and the protective film 24 are formed. form.

第4図は、従来構造を持つ単層アルモフアスシ
リコン薄膜トランジスタのドレイン電圧対ドレイ
ン電流の関係を、ゲート電圧を変化させて測定し
た結果を示す。ソース・ドレイン電極の間隔は、
10μm、ソース、、ドレイン電極の長さは100μm
である。ゲート電極の電圧が20V、ドレイン電圧
が20Vのときのドレイン電流は、3×10-7Aであ
つた。
FIG. 4 shows the results of measuring the relationship between drain voltage and drain current of a single-layer amorphous silicon thin film transistor having a conventional structure by varying the gate voltage. The distance between the source and drain electrodes is
10μm, source, drain electrode length is 100μm
It is. The drain current was 3×10 −7 A when the gate electrode voltage was 20 V and the drain voltage was 20 V.

第5図と第6図は、本発明による二層構造を持
つ薄膜トランジスタの電気特性を示す。半導体膜
3として、厚さ100Åから150Åの間の厚さを持つ
微結晶化シリコン、半導体膜4をアモルフアスシ
リコンを形成し、ソース・ドレイン電極の間隔
は、10μm、ソース、ドレイン電極の長さは100μ
mとした。第5図が光を照射しないダーク特性、
第6図が2000ルツクスの光を照射したときのもの
である。第5図において、ゲート電圧20V、ドレ
イン電圧20Vに対して、ドレイン電流は約2×
10-6Aが得られた。
5 and 6 show the electrical characteristics of a thin film transistor having a two-layer structure according to the present invention. The semiconductor film 3 is made of microcrystalline silicon with a thickness of between 100 Å and 150 Å, the semiconductor film 4 is made of amorphous silicon, the distance between the source and drain electrodes is 10 μm, and the length of the source and drain electrodes is is 100μ
It was set as m. Figure 5 shows the dark characteristic of not irradiating light.
Figure 6 shows the result when irradiated with 2000 lux light. In Figure 5, for a gate voltage of 20V and a drain voltage of 20V, the drain current is approximately 2×
10 -6 A was obtained.

以上に記した本発明の薄膜トランジスタは、ガ
ラスなどの絶縁性基板上に形成でき、高速の動作
が可能であるので、同一基板上に駆動回路と表示
部を形成した、回路接続が安価で、コンパクト、
信頼性の高いアクテイブマトリクス型表示装置
や、同一基板上にセンサーと駆動回路を有するデ
バイスの実現を可能にする。
The thin film transistor of the present invention described above can be formed on an insulating substrate such as glass and can operate at high speed. Therefore, the drive circuit and display section can be formed on the same substrate, making the circuit connection inexpensive and compact. ,
This enables the realization of highly reliable active matrix display devices and devices that have sensors and drive circuits on the same substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aと第1図bはそれぞれ本発明の実施例
のバンド構造を示す図、第2図、第3図はそれぞ
れ本発明の第一と第二の実施例の断面構造を示す
図であり、第4図は半導体膜を一層とした従来薄
膜トランジスタの電気特性を示す図であり、第5
図と第6図は、本発明による薄膜トランジスタの
電気特性を示す図であり、第5図がダーク特性、
第6図が光照射下の特性をそれぞれ示す。 1……ゲート電極、2……ゲート絶縁膜、3,
4……半導体膜、5……ガラス基板、6……ゲー
ト電極、7……ゲート絶縁膜、8……半導体膜、
9,10……n+非晶質シリコン膜、11……ソ
ース電極、12……ドレイン電極、13……半導
体膜、14……絶縁膜、15……ガラス基板、1
6……ゲート電極、17……ゲート絶縁膜、18
……半導体膜、19,20……n+非晶質シリコ
ン膜、21……ソース電極、22……ドレイン電
極、23……半導体膜、24……絶縁膜。
Figures 1a and 1b are diagrams showing the band structure of the embodiment of the present invention, and Figures 2 and 3 are diagrams showing the cross-sectional structure of the first and second embodiments of the invention, respectively. Figure 4 is a diagram showing the electrical characteristics of a conventional thin film transistor with a single layer of semiconductor film.
6 and 6 are diagrams showing the electrical characteristics of the thin film transistor according to the present invention, and FIG. 5 shows the dark characteristic,
FIG. 6 shows the characteristics under light irradiation. 1... Gate electrode, 2... Gate insulating film, 3,
4... Semiconductor film, 5... Glass substrate, 6... Gate electrode, 7... Gate insulating film, 8... Semiconductor film,
9, 10...n + amorphous silicon film, 11... source electrode, 12... drain electrode, 13... semiconductor film, 14... insulating film, 15... glass substrate, 1
6... Gate electrode, 17... Gate insulating film, 18
... Semiconductor film, 19, 20 ... n + amorphous silicon film, 21 ... Source electrode, 22 ... Drain electrode, 23 ... Semiconductor film, 24 ... Insulating film.

Claims (1)

【特許請求の範囲】 1 絶縁性基板上に形成されたゲート電極、ゲー
ト絶縁膜、前記ゲート絶縁膜と接する半導体膜な
どから成る電界効果型薄膜トランジスタにおい
て、 前記半導体膜は、少なくとも第1の半導体膜と
第2の半導体膜とが積層した構造を有し、 前記第1の半導体膜は前記ゲート絶縁膜と接
し、膜厚が10Åから150Åであり、 前記第1の半導体膜のバンドギヤツプは、前記
第2の半導体膜のバンドギヤツプよりも小さいこ
とを特徴とする電界効果型薄膜トランジスタ。 2 前記第1の半導体膜は、微結晶化シリコン膜
であり、前記第2の半導体膜は、非晶質シリコン
膜であることを特徴とする特許請求の範囲第1項
記載の電界効果型薄膜トランジスタ。 3 前記第1または第2の半導体膜は、炭素、窒
素、酸素、ゲルマニウム、スズのいずれか一つま
たは複数を不純物として含む、非晶質シリコン膜
であることを特徴とする特許請求の範囲第1項記
載の電界効果型薄膜トランジスタ。
[Claims] 1. A field effect thin film transistor comprising a gate electrode, a gate insulating film, a semiconductor film in contact with the gate insulating film, etc. formed on an insulating substrate, wherein the semiconductor film is at least a first semiconductor film. and a second semiconductor film, the first semiconductor film is in contact with the gate insulating film and has a thickness of 10 Å to 150 Å, and the band gap of the first semiconductor film is the same as that of the first semiconductor film. A field-effect thin film transistor characterized by having a bandgap smaller than that of the semiconductor film described in No. 2. 2. The field effect thin film transistor according to claim 1, wherein the first semiconductor film is a microcrystalline silicon film, and the second semiconductor film is an amorphous silicon film. . 3. The first or second semiconductor film is an amorphous silicon film containing one or more of carbon, nitrogen, oxygen, germanium, and tin as an impurity. The field effect thin film transistor according to item 1.
JP20707183A 1983-11-04 1983-11-04 Field effect type thin film transistor Granted JPS6098680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20707183A JPS6098680A (en) 1983-11-04 1983-11-04 Field effect type thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20707183A JPS6098680A (en) 1983-11-04 1983-11-04 Field effect type thin film transistor

Publications (2)

Publication Number Publication Date
JPS6098680A JPS6098680A (en) 1985-06-01
JPH0542833B2 true JPH0542833B2 (en) 1993-06-29

Family

ID=16533715

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20707183A Granted JPS6098680A (en) 1983-11-04 1983-11-04 Field effect type thin film transistor

Country Status (1)

Country Link
JP (1) JPS6098680A (en)

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