JPH0654585B2 - Digital recording / reproducing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital recording / reproducing apparatus capable of punch-in and punch-out recording of a digital audio signal or the like.

[Conventional technology]

2. Description of the Related Art Conventionally, there is known a fixed head type digital recording / reproducing apparatus which converts an audio signal of 2 channels or 16 or 32 channels into a digital signal and records it on a plurality of tracks. These digital recording / reproducing apparatuses are required to be capable of punch-in and punch-out (hereinafter referred to as punch-in / out) recording for recording a signal continuous with the original signal on the already recorded signal. ing. FIG. 7 shows the structure of a magnetic head for performing this punch-in / out. Reference numeral 17 is a magnetic tape as a recording medium, 13 is a recording head, and 12 is a reproducing head. FIG. 7A is a recording-reproducing-recording head configuration,
FIG. 3B shows a reproducing-recording-reproducing head structure. A read-write head is required to perform punch-in / out, while a record-playback head is required to perform simultaneous monitoring, so two configurations are possible. Punch in
First, the reproducing head 12 reproduces the original signal to return it to an audio signal, re-encodes it, and switches to the recording mode when a predetermined signal passes through the recording head 13. Punch out consists in canceling the recording mode. FIG. 8 shows a punch-in / out signal form diagram.
The signal B is recorded in a certain section of the signal A. Signal A and Signal B
Crossfades are performed in the sections 48 and 49 at the joints. Section 50 indicates a newly recorded portion.
In the section 50, the continuity of the magnetic tape pattern at the recording start portion C and the recording end portion D becomes a problem. That is, even if the distance between the reproducing head 12 and the recording head 13 in FIG. 7 is strictly measured and the timing from the reproducing mode to the recording mode is attempted to match, the head-to-head distance due to running unevenness or abrasion of the tape running system is The change causes a discontinuity in the tape pattern.

In order to solve such problems, various digital recording / reproducing devices have been proposed recently. FIG. 9 shows JP-A-5
8-9204 is an explanatory view showing a recording format of a conventional multi-channel PCM recording / reproducing apparatus as this type of digital recording / reproducing apparatus, in which 17 is a magnetic tape, 51-1 to 51- 8 is an information track on which information of a total of 8 channels of audio is recorded, and 52-1 and 52-2 are the information tracks 51-1 to 51-1.
51-8 is a redundant track for recording a redundant signal for error correction of voice information data, for example, a parity check code.

FIG. 10 is an explanatory view showing a method of adding the redundant tracks 52-1 and 52-2, where a _{1 to} a ₈ are information tracks 51.
Each information signal recorded on the -1~51-8, c ₁ ~
c ₂ is a redundant signal for error correction recorded on the redundant tracks 51-1 and 52-2, and b is a bit length.

In order to create the redundant tracks 52-1 and 52-2, the information signals a _{1 to} a ₈ are extracted b bits from the information tracks 51-1 to 51-8 at positions adjacent to each other in the tape width direction, and a total of 8b is obtained. Error correction signal c from bit information signal
₁ and c ₂ are obtained and are recorded in the redundant tracks 52-1 and 52-2.

FIG. 11 is an explanatory diagram showing the configuration of the one block.
A large number of the data shown in FIG. 0 are arranged in the tape running direction, and a redundant signal is added in the tape running direction. In FIG, S is a synchronization mark, d ₁ to d ₁₀ is information track 51-1～51-8, redundant tracks 52-1,
Both 52-2 are redundant signals added every 7b bits.

The redundant signals d _{1 to} d ₁₀ are usually cyclic redundancy checks (CR) or less.
A CRC code (information signal-redundant signal) generated by an algorithm of a C code and generated in this way.
Further, a synchronization mark S is added to each track. Hereinafter, the synchronization mark S to the redundant signal di (i = 1 to 10) will be referred to as a frame. This frame is collected for 10 tracks to form one code block CB.

According to the above-mentioned recording format, 2 in 1 code block
It is known that errors up to the track can be corrected.
Therefore, even if the recording condition of any one track is bad and a lot of code errors occur, it can be sufficiently corrected. In addition, even if one track completely fails and becomes inoperable and dropout occurs in another track, it can be corrected, so the operation of the recorder is not impaired and the stability of the recorder is greatly improved. It has increased.

FIG. 12 is an explanatory diagram showing changes in information when punch-in / out is performed in such a multi-channel PCM recording / reproducing apparatus. In the figure, the hatched portion is the portion where the recording is performed again, and A is one section of the tape 17. Therefore,
It is re-recorded in track units.

Next, the operation will be described. A conventional digital recording / reproducing apparatus is provided with a time axis correction circuit for outputting reproduction data at a predetermined timing without time axis fluctuation by using detection signals of plural kinds of synchronization marks in order to correctly reproduce punch-in / out points. This ensures that code blocks can be reconstructed correctly. That is, two types of sync marks S ₀ and S ₁ are prepared, and both sync marks are added at a constant period during recording. For example, S ₀ , S ₁ ,
S ₁ , S ₁ , S ₀ , S ₁ , ... And the synchronization mark S ₀ is added every four frames, and the synchronization mark S ₁ is added to the remaining frames. In this case, the recording format is the first
As shown in FIG. 3, by paying attention to the synchronization mark S ₀ , there is no danger that the combination of frames indicated by diagonal lines is regarded as one code block. That is, the synchronization mark S
The number of frames from a certain frame of ₀ is always counted, and the code block is reconstructed by the frame of the same count value based on the count value.

[Problems to be solved by the invention]

Since the conventional digital recording / reproducing apparatus is constructed as described above, there is a problem that the code block cannot be reconstructed when a shift of 1/2 or more of the interval of the synchronization mark S ₀ occurs at punch-in / out. there were.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a digital recording / reproducing apparatus capable of accurately reconstructing a code block when punching in / out.

[Means for solving problems]

The digital recording / reproducing apparatus according to the present invention performs punch-in and punch-out in block units.
By adding consecutive block numbers to each block and controlling the recording position in the relocation memory using this block number, the digital data is relocated and the digital data is written and read in the relocation memory. If the write position deviates from the predetermined range, the detecting means detects it and adjusts the amount of the reproduction signal from the recording medium to set the write position of the digital data in the rearrangement memory to the predetermined position. It is designed to be returned within the range.

[Action]

The detecting means in the present invention detects a shift in the write position to the reallocation memory caused by a block number jump or a duplicate rearrangement during reproduction, and when the shift in the write position exceeds a predetermined range, The writing position of the digital data in the rearrangement memory is held within a predetermined range by instructing the adjusting means to adjust the amount of reproduction signal from the recording medium.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
FIG. 1 is a block diagram showing a digital recording / reproducing apparatus according to an embodiment of the present invention, and FIG. 2 is a recording format for recording / reproducing 2-channel digital audio signals on / from a magnetic tape by an 8-track fixed head. It is a data configuration diagram showing. FIG. 2 (a) shows a frame structure, and one frame is a P having 20 quantization bits.
It consists of 16 samples of CM data (PD) (320 bits), 16 bits of sync signal (S), 8 bits of identification signal (I), and 16 bits of C1 check data for error detection and correction, for a total of 360 bits. There is. Further, FIG. 2 (b) shows a block structure, in which a frame-structured signal is converted into a PCM
6 tracks for data PD ₁ -PD _6, recorded on eight tracks of two tracks as the error detection and correction for C2P _1, C2P _2. The configuration of the identification signal I is 1-1, 1-2 is ID data for identifying sampling frequency, number of quantization bits, tape speed, etc., 1-3, 1-4 are block numbers, 1-5.
˜1-8 are C3 parities. This error correction code is
Reed-Solomon code is used, for example, input data v
Is given by v = [ID ₁ , ID ₀ , BA ₁ , BA ₀ , C3P ₃ , C3P ₂ , C3P ₁ , C3P ₀ ], and the parity check matrix H is Then, C3P ₃ to C3P ₀ are generated so that v · H ^t = 0. Here, a is, for example, a root of the primitive polynomial X ⁸ + X ⁴ + X ³ + X ² +1 on GF (2 ⁸ ). 1-
Since 1 to 1-8 are each 8 bits, the block number is B
A _1, BA becomes ₀ and the combined with 16 bits taken, it becomes sufficiently long to perform punch-in / out.

Further, in FIG. 1, 2 is an analog signal input terminal,
3 is an analog / digital conversion circuit (hereinafter referred to as A / D conversion circuit), 4 is a first switch, 5 is an interleave circuit for rearranging data from the first switch 4, 6
Is a C ₂ encoder connected to the interleave circuit 7, 7 is a C3 and C1 encoder (block number adding means), and 8 is C
3, a block number generator connected to the C1 encoder 7, 9
Is a synchronizing signal adding circuit, 10 is a delay circuit for adjusting punch-in / out recording timing, 11 is a modulator for converting digital data into a pattern for recording on the magnetic tape 17, 12 and 14 are reproducing heads, and 13 is recording. A head, 15 is a second switch, 16 is a capstan motor for controlling the running of the tape, 18 is a demodulator for returning the signal reproduced by the magnetic tape 17 to digital data, 19 is a wow and flutter generated by the magnetic tape and the running mechanism, A time axis correction circuit for removing jitter and the like, 20 is a servo circuit at the output of the time axis correction circuit 19, 21 is a C1 and C3 decoder (block number detecting means), 22 is a C1 and C3 decoder 2
Deinterleave circuit for returning the order of data from 1 to 23, C2 connected to the deinterleave circuit 22
Decoder, 24 is a digital-analog conversion circuit (hereinafter,
D / A conversion circuit), 25 is an analog signal output terminal from the D / A conversion circuit 24, 26 is a first clock generator for supplying a clock to an area 28 surrounded by a dotted line, 2
A second clock generator 7 supplies a clock to an area 29 surrounded by a dotted line and acts as an adjusting means.

Next, the operation will be described. First, normal recording, here, simultaneous monitoring will be described. The analog signal input from the input terminal 2 is sampled at the sampling frequency of 48 KHz by the A / D conversion circuit 3, and then the quantization bit number is 1
6 digital data. This digital data passes through the first switch 4 and the interleave circuit 5
The data order is rearranged with. During this time, Reed-Solomon coding is performed by the C2 encoder 6. The output C3 and C1 encoder 7 from interleave circuit 5 encodes one block. That is, the block number generator 8
Generate 16-bit block numbers BA ₁ and BA ₀ at
C3 coding as shown in FIG. 2B is performed, and then C1 coding is performed for each frame in the tape longitudinal direction. This error-correction-coded data is sent to the sync signal adding circuit 9 to which the sync mark S is added, and the delay circuit 10
Sent to. The data delayed by the delay circuit 10 is sent to the modulator 11 to be modulated and recorded on the magnetic tape 17 by the recording head 13.

Next, the signal reproduced by the reproducing head 14 passes through the second switch 15 and is demodulated by the demodulator 18. Then, the time axis correction circuit 19 absorbs the jitter, and the C1, C3 decoder 21
Sent to. C1, C3 detects an error in the tape longitudinal direction at the decoder 21 in first C1 decoder, after correction, block number BA _1, BA ₀ is corrected by C ₃ decoder. The deinterleave circuit 2 is configured by using the block numbers BA ₁ and BA _0.
Digital data is input to 2. The servo circuit 20 drives the capster motor 16 in synchronization with the clock of the second clock generator 27.

Next, a block diagram of the deinterleave circuit 22 and the second clock generator 28 is shown in FIG. 36 in FIG.
Is a data input terminal, 37 is a block number BA ₁ , BA ₀
Input terminal, 38 is a data output terminal, 30 is a memory for data rearrangement and deinterleaving, 31 is an address selection circuit of the memory 30, and 32 is data for outputting data to the D / A conversion circuit 24. Read address circuit,
33 is a write / read address circuit for exchanging data with the C2 decoder 23, 34 is a write address circuit for writing data in the memory 30, and 35 is a memory write position detection circuit which functions as a detection means. The data from the C1 and C3 decoder 21 input to the input terminal 36 is stored in the memory 30 according to the address generated by the write address circuit 34 based on the corrected block numbers BA ₁ and BA ₀ input to the input terminal 37. The data written and written in the memory 30 is read according to the address generated by the read address circuit 32,
It is output from the output terminal 38 to the D / A converter 24. As a result, the digital data is rearranged, and the original block can be reliably constructed. While the digital data is rearranged by the deinterleave circuit 22, the data in the memory 30 is sent to the C2 decoder 23 for error detection and correction based on the address generated by the write / read address circuit 33. Then, it is returned to the memory 30 again. The data sent from the output terminal 38 to the D / A converter 24 is converted into an original analog signal and output from the output terminal 25 as a reproduced signal.

On the other hand, the second clock generator 27 includes a phase detector 39,
This is a general PLL oscillator including a voltage controlled frequency variable oscillator 40 and a frequency divider 41, 42 is a system clock output terminal, and 43 is a control clock output terminal to the servo circuit 20. This second clock generator 27 locks with the reference clock from the first clock generator 26,
If there is no detection signal from the memory write position detection circuit 35, the frequency division ratio of the frequency divider 41 is set so as to generate the same clock as the clock of the first clock generator 26. Here, in the area indicated by 29 in FIG. 1, the tape speed is adjusted in synchronism with the clock frequency of the second clock generator 27 so that the reproduction signal amount can be varied.
Since the regions 28 and 29 are operated by the clock having the same frequency, the memory 3 of the deinterleave circuit 22 is
In the case of 0, the input signal amount and the output signal amount of data are the same and the normal operation is performed.

Next, the case of punch-in / out will be described. The switches 4 and 15 first select the b ₁ and a ₂ sides, respectively. The output terminal 25 outputs the signal A reproduced by the reproducing head 12.
While listening to the signal, the first switch 4 is switched to the a ₁ side in order to record the signal B. If the total time of the delay time in the deinterleave circuit 22 and the interleave circuit 5 and the delay time in the delay circuit 10 is set equal to the time until the signal reproduced by the reproducing head 12 passes through the recording head 13, recording is performed. Good. In this case, rewrite all the tracks.
As described above, although precise beginning and end of the magnetic pattern in the section 50 that the combined delay time shown in FIG. 8, etc. running irregularity of the delay circuit 10 is shifted, block number BA _1, B
Since A ₀ is recorded, even if the block numbers are skipped or duplicated, there is no problem in forming the original block.

FIG. 4 is a data flow diagram of the block reconfiguration in the deinterleave circuit 22 as described above. Reference numeral 44 is a delay section required for deinterleaving, and 45 is deinterleaving, which is an allowable range of the write position of the input data of the cyclic memory 30 of the circuit 22. FIG. 4 (a) shows a case where a data string of block numbers 1, 2, 3, 4, ... Is input to the memory 30. There is no skip or duplication of block numbers, and the write position in the memory 30 is the fixed position A. FIG. 4 (b) shows the case where the data strings of block numbers 1, 2, 4, 5, ... Are input, and there is a jump in the block numbers. In order to rearrange the blocks, the input data of block number 4 is input. At the time of writing, the writing position in the memory 30 is moved to the position B which is deviated from the fixed position A by one block. In this case, although the data of the block number 3 is missing, since the arrangement of the blocks is restored, the correction can be performed by the error correction of the C2 decoder 23. FIG. 4 (c) shows a block number sequence 1,
The case where a data string of 2, 2, 3, 4, ... Is input is shown. Since the block numbers are duplicated and the blocks are rearranged, the write position in the memory 30 is changed from the fixed positions A to B when the input data of the second block number 2 is written.
And moves to the position C which is shifted one block in the opposite direction. In the case of FIG. 4 (b) and FIG. 4 (c), the data write position is A
The allowable range 45 of the writing position of the input data is provided so that there is no problem even if any blocks are shifted in the same direction, though → B and A → C. However, if the allowable range 45 is exceeded, the delay section 44 required for deinterleaving is entered and normal deinterleaving cannot be performed.

Therefore, in the present invention, the allowable range 45 of the write position of the memory 30 is divided into the following three sections, and this is detected by the memory write detection position circuit 35, and the divider 41 of the second clock generator 27 is detected. The amount of data input to the memory 30 is controlled by changing the frequency division ratio. This operation will be described with reference to FIG.

The allowable range 45 of the writing position of the input data is set to the section D,
Divide into E and F. When the block jump occurs a plurality of times and the write position enters the section F, this is detected by the memory write position detection circuit 35, and the second clock generator 2 is detected.
The frequency division ratio of the frequency divider 41 of 7 is increased, and the clock in the region indicated by 29 in FIG. 1 is made lower than the clock of the first clock generator 26 to reduce the amount of signal reproduction. Then, in the memory 30, the read signal amount is constant and the write signal amount decreases, and the write position returns to the section D. If the block number of the reproduced signal is duplicated a plurality of times and the write position enters the section E, this is detected by the memory write position detection circuit 35 and the second clock generator 2 is detected.
The frequency division ratio of the frequency divider 41 of 7 is made small, the clock of the area 29 is made higher than the clock of the first clock generator 26,
Increase the amount of signal reproduction. Then, in the memory 30, the read signal amount is constant and the write signal amount increases, and the write position returns to the section D.

Next, the detection characteristic of the memory write position detection circuit 35
Shown in the figure. The abscissa indicates the write position in the memory 30, the sections D, E, and F, and the ordinate indicates the clock frequency of the second clock generator 27. If you enter section F from section D,
Feedback is applied so that the clock frequency of the second clock generator 27 is lowered to return to the section D. Here, once the section F is entered and the clock frequency is lowered, the section D
The clock frequency is kept low until it returns to the center position A of 1, and a hysteresis is given to prevent oscillation. Similarly, when the section E enters the section E from the section D, the clock frequency of the second clock generator 27 is increased and feedback is given to return to the section D.
When the clock frequency rises upon entering, the clock frequency is kept raised until it returns to the sensor position A in the section D, and hysteresis is provided. The increase rate and the decrease rate of the clock frequency of the second clock generator 27 change the system clock of the area 29 including the servo circuit 20, so that it is necessary to set the reproduction servo lock level.

In the above embodiment, the frequency of the second clock generator 27 is increased / decreased stepwise in FIG. 6, but if it is gradually increased / decreased stepwise, the reproduction servo lock will not be lost, and It is possible to quickly return to the center position A of the area D.

Further, in the above embodiment, the memory for data rearrangement and the memory for de-interleaving are performed by the same memory, but they may be configured by different memories.

Further, in the above embodiment, the block skipping and the block duplication caused by the punch-in / out have been described. However, in the case where the magnetic tape is cut once by the manual cutting process and the magnetic tape is connected again by the splicing tape, At the time of priming, two magnetic tapes should be overlapped and connected, or they should be connected at an interval. In this case as well, block skips and block duplications occur. The same effect as the embodiment is obtained.

〔The invention's effect〕

As described above, according to the present invention, the rearrangement memory for controlling the recording position of the block to rearrange the digital data by using the continuous block number added for each block is provided. When the writing position of the digital data of is deviated from the predetermined range, by adjusting the reproduction signal amount from the recording medium, the write data amount of the digital data to the rearrangement memory is adjusted, and the writing position is set within the predetermined range. Since it is configured to return, even if the write position to the relocation memory is deviated due to the block number jump or the relocation of the duplicate at the time of reproduction, the write position is always kept within the predetermined range. , The code block can be accurately reconstructed, the normal reproducing operation can always be performed, and a highly reliable digital recording / reproducing apparatus can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital recording / reproducing apparatus according to an embodiment of the present invention, FIGS. 2 (a) and 2 (b) are explanatory views showing the data structure of one block, and FIG. A block diagram showing the details of the deinterleave circuit and the clock generator 2 of FIG. 2, FIGS. 4 (a) to 4 (c) are data flow diagrams of a memory for rearranging blocks, and FIG.
FIG. 6 is a conceptual diagram for explaining the operation of the memory write position detection circuit, FIG. 6 is an explanatory diagram showing the characteristics of the memory write position detection circuit, and FIGS. 7 (a) and 7 (b) are punch-in / out. FIG. 8 is a diagram showing the configuration of a magnetic head for carrying out the above, FIG. 8 is an explanatory diagram showing a signal form of pitch-in / out, FIG. 9 is a format diagram showing a recording format of a conventional digital recording / reproducing apparatus, and FIG. 10 is its redundant track. 11 is a block diagram showing the structure of one block thereof, FIG. 12 is a signal form diagram of punch-in / out,
FIG. 13 is a format diagram showing a recording format in the case of having two kinds of synchronization marks. In the figure, 1-3 and 1-4 are block numbers, 17 is a magnetic tape (recording medium), 27 is a second clock generator (adjusting means), 30 is a memory (relocation memory), and 35 is a memory writing position. Detection circuit (detection means). In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. Digital data of one or a plurality of channels is distributed to a plurality of tracks, a sync signal is periodically added to each track to form a frame, and the frame of each track is recorded simultaneously. In a digital recording / reproducing apparatus capable of punch-in / punch-out recording, block numbers adding means for adding consecutive block numbers to each block by using the frames of the plurality of tracks simultaneously recorded as one block,
Block number detecting means for detecting the block number from the reproduction data, relocation memory for relocating the digital data by controlling the recording position of the block using the detected block number, and the relocation memory From the recording medium on the basis of the detection signal from the detection unit, which detects the positional relationship between the writing position and the reading position of the digital data to the digital data, and generates a detection signal when the writing position deviates from a predetermined range. By adjusting the reproduction signal amount of the digital data to adjust the write data amount of the digital data to the rearrangement memory to return the write position to within the predetermined range. Recording / playback device.