JPH0463463B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fixed head type multi-channel PCM recording and reproducing apparatus.

FIG. 1 is a diagram showing the recording format of a multi-channel PCM recording and playback device.
1 is a magnetic tape, (2-1) to (2-8) are information tracks on which information for one audio channel is recorded;
(5-1) and (5-2) are redundant tracks on which redundant signals for error correction of the audio information data of the information track 2, such as parity check codes, are recorded.

Figure 2 shows the above redundant tracks (5-1) (5-2).
In this figure, a ₁ to a ₈ are information signals recorded on information tracks (2-1) to (2-8), respectively, and c ₁ to _{c 2} are redundant tracks (5-1) ( 5
-2), where b is the bit length of the redundant signal for error correction recorded.

In order to create redundant tracks (5-1) and (5-2), the above information tracks (2-1) to (2-
8), information signals a ₁ to _{a 8} of b bits each are extracted from adjacent positions in the tape width direction, error correction signals c ₁ and c ₂ are obtained from the information signal of a total of 8 b bits, and these are sent to the redundant track (5 -1) Record in (5-2).

In FIG. 3, a large number of data shown in FIG. 2 are arranged in the tape running direction, and redundant signals are also added in the tape running direction. In the figure, S is a synchronization mark, and d ₁ to _{d 10} are information tracks (2-1) to
(2-8), redundant tracks (5-1) and (5-2) are redundant signals added every 7b bits.

The redundant signals d ₁ to _{d 10} are usually generated by a CRC code algorithm, and a synchronization mark S is further added to each track to the CRC code (information signal + redundant signal) generated in this way. Hereinafter, the period from the synchronization mark S to the redundant signal di (i=1 to 10) will be referred to as a frame. A collection of 10 tracks of these frames constitutes one code block CB.

It is known that according to the above recording format, errors in up to two tracks in one code block can be corrected. Therefore, even if the recording condition of any one track is poor and code errors occur frequently, they can be sufficiently corrected. In addition, even if one track completely fails and becomes inoperable, it can be corrected even if dropouts occur in other tracks, so the operation of the recorder is not impaired and the stability of the recorder is greatly increased. That means you did it.

Conventionally, there has been a multi-track PCM recording/playback device for recording in the above format as shown in FIG. In the figure, 1 is tape,
D is the tape running direction, 7 is a multitrack playback head, 101 is an amplifier that amplifies the output of the playback head 7, and 201 is a time axis correction circuit that temporarily stores the output of the amplifier 101 and outputs the crystal oscillator accuracy at timing. , 102 is an error correction circuit for error correcting the output of the circuit 201, 103 is a D/A converter for D/A converting the output of the error correction circuit 103, 1
04 is an audio amplifier that amplifies the output of the D/A converter, and the circuit elements 101, 201, 10
2, 103, and 104 form a reproduction side digital circuit 9 (hereinafter referred to as reproduction circuit), and 8 is an output terminal of the circuit 9. Further, 11 is an input terminal, 106 is an audio amplifier that amplifies the audio signal from the input terminal 11, and 107 is an A/D converter that A/D converts the output of the audio amplifier 106. Both are input-side digital circuits. 10 (hereinafter referred to as an input circuit). 12 is the output of the error correction circuit 102 on the reproduction side and the input circuit 10 on the recording side.
105 is a delay circuit for head interval compensation that delays the input signal from the switch 12 for a predetermined time; 108 is a delay circuit that applies a synchronization mark S and an error correction code di=( i=1 to 8); 109 is the error correction code addition circuit 108;
Both of them form a recording-side digital circuit 15 (hereinafter referred to as a recording circuit). Reference numeral 6 denotes a multi-track recording head for recording the output of the recording circuit 15 onto the tape 1.

Although FIG. 4 shows only the circuits on the reproduction side and the recording side of the information track for simplicity, the configuration of the redundant track is different from the above, and the reproduction side circuit has only circuits 7, 101, 201, and 102. , its output is supplied to all error correction circuits of the information track for error correction. Furthermore, the recording signals of all the information tracks are supplied to the recording side circuit of the redundant track, and furthermore, during overdubbing, all the reproduction signals of the information tracks other than the recording track are supplied to the recording side of the redundant track via the switch 12 of each track. It is now being supplied to the circuit. Furthermore, the reproduction side circuit of the information track is not as shown in FIG. 4, but the error correction circuit of each track is supplied with reproduction data of all other tracks for error correction.

Next, the operation will be explained.

The output of the reproduction head 7 is amplified by a reproduction amplifier 101 and applied to a time axis correction circuit 201. Then, the playback information signal is subjected to time axis correction circuit 201 that absorbs time axis fluctuations (hereinafter referred to as jitter) caused by uneven running of the tape, etc.
2, code errors are corrected, the signal is converted back to an analog signal by the D/A converter 103, amplified by the audio amplifier 104, and output from the output terminal 8 to the outside.

On the other hand, the audio signal applied to the input terminal 11 is amplified by the audio amplifier 106, and the A/D converter 10
7, it is converted to a PCM signal. The output of this A/D converter 107 is sent to the delay circuit 1 via the switch 12.
05, and after being delayed for a predetermined time by the delay circuit 105, the error correction code adding circuit 108 outputs the synchronization mark S and the error correction redundant signal di (i=1
8) are added, amplified by the recording amplifier 109, and recorded on the tape 1 by the recording head 6.

Note that the switch 12 and the recording amplifier 10
9 is controlled by an external operation button (not shown), and when switch 2 is connected to the output side of error correction circuit 102, recording amplifier 109 does not operate.

A conventional multi-channel PCM recording/playback device is configured as described above, and the PCM recorder can completely absorb jitter during playback using the time axis correction circuit shown in Figure 4. This is one of the features of PCM recorders.

By the way, in order to completely absorb jitter with the above-mentioned time axis correction circuit, tape running is controlled by a phase-controlled servo system that compares the reference phase of the crystal oscillator precision with the reference reproduction phase of the reproduction information signal. I need to be there. It is generally known to use the detection information of the synchronization mark of an arbitrary track shown in FIG. 3 as the reference reproduction phase of the reproduction information signal. However, if a servo system is constructed that is controlled using the position of the synchronization mark of one existing track as a reference reproduction phase, the following problem will occur if the track becomes unreproducible for some reason. That is, according to the above recording format, a one-track error is completely uncorrectable.
Although the information signal within the frame can be reproduced by error correction, since there is no synchronization mark, a reference reproduction phase cannot be obtained, the tape running is disturbed, and normal reproduction cannot be performed.

Furthermore, even if a dedicated servo track for recording the reference reproduction phase is provided in addition to the track for recording PCM information, if the servo track becomes unreproducible, normal reproduction of PCM information will become impossible. Unfortunately, it was a problem.

Furthermore, one function of the multi-channel PCM recording/playback device is overdubbing processing. Overdubbing refers to recording the reproduced sound of a previously recorded track onto another track after a predetermined delay in synchronization with the reproduced sound of a previously recorded track. However, when overdiving is performed, the following problems occur.

In FIG. 4, during overdubbing, the audio information signal _a2 of the information track (2-2) is sent from the input circuit 10 to the switch 12 of the track (2-2).
The information signals of the other information tracks (2-1), (2-3) to (2-8) are supplied to the recording circuits (not shown) of the redundant tracks (5-1) and (5-2) via the
a ₁ , a ₃ to _{a 8} are also connected to redundant tracks (5-1) via the switch 12 of each track by the reproduction circuit 9.
(5-2) is supplied to the recording circuit (not shown),
Redundant signals c ₁ and c ₂ are generated by the recording circuit.
In this case, information tracks (2-1) (2-3) ~
(2-8) If the information signals a ₁ , a ₃ to a ₈ are newly recorded, the deterioration due to code errors will increase.
Accordingly, it is necessary to re-record only the redundant tracks (5-1) and (5-2) whose redundant signals should be changed.

FIG. 5 is a diagram showing how the information on each track changes due to overdubbing. In the figure, the shaded area is the re-recorded area, and A is one section on the tape 1.

FIG. 6 is an enlarged view of section A in FIG.

In the overdubbing process, the playback head 7
A redundant signal is generated based on the information signals a ₁ , a ₃ to _{a 8} of the reproduced frames excluding the information of the information track 2-2 reproduced in , and the information signal a ₂ of the newly recorded second channel.
Create c ₁ and c ₂ and add the second channel information and redundant signal
Since only c ₁ and c ₂ are recorded, the frames other than the second channel that will not be recorded this time and the frames of the second channel that will be newly recorded need to be recorded correctly lined up on tape 1 as shown in Figure 3. be. Therefore, the signal to be recorded is delayed by a predetermined period of time, and the sum of this delay time and the time required for signal processing is calculated by the reproducing head 7.
It is necessary to accurately match the tape running time from the tape to the recording head 6, and for this adjustment
The PCM recording/playback device includes a delay circuit 105. Then, due to the function of this delay circuit 105, the sixth
As shown in the figure, it is ensured that one code block is composed of 10 frames lined up in the vertical direction.

However, if variations occur in the tape running time from the playback head to the recording head due to jitter, etc., the actual recording state will shift as shown in Figure 7, and the area separated by the broken line in the figure
There was a risk that one code block would be constructed by a combination of diagonally shaded frames instead of code blocks.

The present invention has been made in order to eliminate the drawbacks of the conventional ones as described above, and provides a time axis correction circuit that outputs reproduced data at a predetermined timing without time axis fluctuation using detection signals of multiple types of synchronization marks. It is an object of the present invention to provide a PCM recording/playback device that can reliably reconstruct code blocks correctly by providing a PCM.

An embodiment of the present invention will be described below with reference to the drawings.

First, the principle of the present invention will be explained.

In the present invention, two types of synchronization marks S ₀ and S ₁ are prepared, and both synchronization marks are added at regular intervals during recording. For example, S ₀ , S ₁ , S ₁ , S ₁ , S ₀ , S ₁ ,...
Assume that a synchronization mark S ₀ is added to every four frames, and a synchronization mark S ₁ is added to the remaining frames. In this case, the recording format becomes as shown in FIG. 8, and by paying attention to the synchronization mark _S0 , there is no danger of regarding the combination of frames shown with diagonal lines as one code block. In other words, we constantly count the number of frames from the frame with synchronization mark S ₀ , and based on that count,
This means that the code block is reconstructed using frames with the same count value.

FIG. 9 is a circuit diagram of a time axis correction circuit in a PCM recording and playback device according to an embodiment of the present invention,
In the figure, the same symbols as in FIG. 4 indicate the same parts as in FIG. 4, and 202 is an input terminal for playback data;
206 is a synchronization mark detection circuit that discriminates and detects two types of synchronization marks S ₀ and S ₁ from the reproduced data signal from the input terminal 202; C is a detection circuit that detects when the circuit 206 detects synchronization marks S ₀ and S ₁ ; signal line that outputs output,
B is a signal line that outputs a detection output when the circuit 206 detects only the synchronization mark _S0 , 205 is an input terminal to which a reproduced clock with time axis fluctuation obtained from reproduced data is applied, and 209 is the output of a crystal oscillator. 210 is an input terminal to which the read address of the information bit in the frame that is obtained from the frame and has no time fluctuation is input, and 210 indicates the number of the frame from the frame to which the synchronization mark S ₀ is added, which also has time axis fluctuation. The input terminal 207 to which a read frame address that is not present is applied is reset for each frame by the detection output of the signal line C, and counts the reproduced clock of the input terminal 205 to create a write bit address indicating the information bit in the frame. A first counter 211 is connected to the output of the first counter 207 and the bit address input terminal 20.
a first selector that selects the input from 9 and applies it to the memory 203 as a bit address signal;
08 is a second counter that is reset by the detection output of the synchronization mark S ₀ on the signal line B and counts the frame address based on the detection output of the synchronization marks S ₀ and S ₁ on the signal line C; D is the second counter 208; The count output signal line 212 is a second selector that selects the count output of the signal line D and the input of the input terminal 210 and applies it to the memory 203 as a frame address signal. Alternatively, 2 indicates that the bit length of the signal flowing through each signal line is n or 2, respectively. 203 inputs the reproduced data of the terminal 202 to the first,
This is a memory that stores addresses determined by the write bits and frame addresses that are the outputs of the second selectors 211 and 212, and outputs the contents of the read bits and frame addresses that are the outputs of both selectors to the terminal 204 at the time of reading. 203, 207, 208, 211, and 212 form a time axis correction circuit 201 that uses the output of the synchronization mark detection circuit 206 to output reproduced data at a predetermined timing without time axis fluctuation.

Next, the operation will be explained.

First, the first counter 207 is reset every frame by the detection output of the synchronization marks S ₀ and S ₁ of the synchronization mark detection circuit 206, and by counting the reproduced clock applied to the input terminal 205,
A write address in the memory 23 corresponding to the information bit in the frame is created. Further, the second counter 208 is reset by the detection result of the synchronization mark S ₀ by the synchronization mark detection circuit 206, counts the synchronization marks S ₀ and S ₁ , and calculates the number of frames starting from the frame to which the synchronization mark S ₀ was added. A write frame address in the memory 3 indicating which frame is created is created.

FIG. 10 shows the relationship between the detection results of the synchronization marks S ₀ and S ₁ and the write frame address. In the figure, B indicates the timing at which synchronization mark S ₀ was detected, D ₁ and D ₂ are the signal waveforms of the lower bit and upper bit of the 2-bit signal line D signal, and 0 to 3 are the signal waveforms of signal line D. This is the value when considered as a decimal number.

In this figure, even if S ₀ cannot be detected at the position X, the second counter 208 counts based on the signal C, and the value of the write frame address is correctly updated to "0".

Next, if the frame address deviates for some reason, there is a risk that the code block will be erroneously reconstructed and the error correction ability will be significantly reduced.

However, in this embodiment, when the count value of the second counter 208 indicates "3" during normal operation,
When synchronization mark S ₀ is detected, the count value becomes “0”
Since the configuration is such that it is reset to
As shown in the figure, if the synchronization mark _S0 is detected when the count value of the counter 208 is other than "3", it can be determined that some kind of defect has occurred in the signal C as shown in FIG. The contents of the frame from the time when the synchronization mark _S0 was last detected are set to all "1" or a value equivalent to that, and in such a case, it is forcibly processed as if an error has occurred. .

The above situation is shown in FIGS. 11 and 12.

FIG. 11 is a diagram showing a case where the audio information signal in the frame has changed to the synchronization mark _S1 , and even though the synchronization mark is not generated, the signal line D
When becomes “0” (D ₁ = 0, D ₂ = 0), the synchronization mark S ₀ is detected after a predetermined time T ₁ , so the synchronization mark S 0 is detected up to the last frame before that and S ₀ is detected. It can be seen that an error is included in section E of . Therefore, the contents of these frames are rewritten to all "1"s or a value equivalent thereto to forcibly generate an error.

FIGS. 1 and 2 are diagrams showing a case where the tape is running faster and one synchronization mark _S1 cannot be detected.

In this case, since the synchronization mark S ₀ is detected when the signal line D is "2", the period F up to the frame where S ₀ was last detected before that point is similar to the above.
It is assumed that the contents of the frame are rewritten to all "1"s or equivalent contents over the period of time, and that an error is forcibly generated.

According to the PCM recording and playback device of this embodiment, a frame address and a bit address within the frame are created by counting the playback clock using the detection results of two types of synchronization marks, and the frame address and the bit address within the frame are stored in the memory. When playback data is written and a write address created from a clock with no time axis fluctuation is input to memory, the contents of that address are output, so one synchronization mark may be missing or the tape may rotate. Even if there is time-axis fluctuation in the reproduced data due to unevenness or the like, it is possible to obtain a reproduction output without time-axis fluctuation, and as a result, it is possible to listen to undistorted audio.

Note that the synchronization mark detection circuit for detecting the synchronization marks S ₀ and S ₁ in the above embodiment detects the synchronization marks S ₀ and S ₁ at the positions where the synchronization marks S 0 and S 1 _are to be detected.
Pseudo sync mark even if S ₁ is not detected
A circuit may be included that outputs a synchronization mark detection output assuming that S ₀ and S ₁ have been detected.

Furthermore, the number of tracks on a periodic tape is not limited to 10, and the number of channels and the number of tracks may not match.

As described above, according to the present invention, code blocks are reconstructed by focusing on a specific synchronization mark among two types of synchronization marks, and reproduced data is output at a timing without time axis fluctuation.
Even if a discrepancy occurs between tracks due to overdubbing or the like, code blocks can be reliably and correctly reconstructed, and audio without distortion can be heard.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the recording format of a multi-track PCM recording/playback device, Fig. 2 is a diagram explaining a method of adding redundant tracks, Fig. 3 is a diagram explaining code blocks, and Fig. 4 is a diagram showing a conventional multi-track PCM recording/playback device.
A block configuration diagram of the PCM recording/playback device. Figure 5 shows the tracks that are rewritten during overdubbing. Figure 6 shows the recording format of multiple tracks. Figure 7 shows the relative position of the recording tracks when overdubbing. 8 is a diagram showing a recording format in which two types of synchronization marks are added. FIG. 9 is a block diagram of a time axis correction circuit according to an embodiment of the present invention. Figure 10 is a time chart showing the write address according to an example of operation in Figure 9;
FIG. 12 is a time chart showing write addresses in another example of operation shown in FIG. 9, and FIG. 12 is a time chart showing write addresses in still another example of operation shown in FIG. 206... Synchronization mark detection circuit, 201... Time axis correction circuit, 202... Playback data input terminal,
Input terminal, 205... Regeneration clock input terminal, 2
07,208...first and second counters, 21
1,212...first and second selectors, 209...
...Read bit address input terminal, 210...
Read frame address input terminal, 203...
Memory, 204...output terminal. Note that the same numbers in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. A synchronization mark for converting the audio signal of one or more channels into a digital signal and recording it on a plurality of tracks in the longitudinal direction of the tape, and for synchronizing the data when playing back the audio information signal of each track. In a PCM recording/playback device that configures a frame by periodically adding sync marks to the same position in the tape width direction, two or more types of synchronization marks are added to the audio information signal at a predetermined period, respectively, and are provided for each recording side circuit of each track. a synchronization mark addition circuit for each track, a synchronization mark detection circuit for discriminating and detecting the plurality of types of synchronization marks provided for each playback circuit of each track, and a synchronization mark detection circuit provided for each playback circuit for each track. write bit address generation means for generating a write bit address by counting the reproduced clock having time axis fluctuation obtained from the reproduced data; A write frame address creating means that creates a frame address and sets the write frame address to a desired value when a playback synchronization mark other than the specific synchronization mark is detected; a read bit address that has no time axis fluctuation from the write bit address; a first selector that selects and outputs the write frame address and a read frame address that does not include time axis fluctuation; a second selector that selects and outputs the write frame address and the read frame address that does not include time axis fluctuation; when the outputs of both selectors are write addresses, the playback data corresponds to The present invention is characterized by comprising a memory from which data written at an address is read out when the output of both selectors is a read address, and a time axis correction circuit that adjusts the reproduced data using the output of the synchronization mark detection circuit. PCM recording and playback device. 2. Converting the audio signal of a single or multiple channels to a digital signal and recording it on multiple tracks in the longitudinal direction of the tape, and placing synchronization marks on the audio information signal of each track at the same location in the width direction of the tape to synchronize the data during playback. In a PCM recording/playback device that configures a frame by periodically adding synchronization marks to positions, a synchronization mark is provided for each recording side circuit of each track and adds two or more types of synchronization marks to the audio information signal at predetermined intervals. an additional circuit, a synchronization mark detection circuit provided in each playback circuit of each track to discriminate and detect the plurality of types of synchronization marks, and a synchronization mark detection circuit also provided in the playback circuit corresponding to each track, which is obtained from the playback data. A write bit address generation means that generates a write bit address by counting reproduced clocks having time axis fluctuation; A write frame address is generated based on the detection result of a specific synchronization mark among the above two or more types of synchronization marks, and the above specified A write frame address generating means sets the write frame address to a desired value when a playback synchronization mark other than the synchronization mark is detected; 1 selector, a second selector that selects and outputs the write frame address and a read frame address that does not include time axis fluctuation; when the output of both selectors is a write address, the playback data is written to the address; When the output of is a read address, the data at the address is read, and when the synchronization mark detection device detects a reproduction synchronization mark other than the specific synchronization mark, and the write frame address is different from the value that should be taken at that time, the above It consists of a memory that forcibly switches the playback data to an incorrect value by going back a predetermined period from the time when a playback synchronization mark other than a specific synchronization mark is detected, and uses the output of the above-mentioned synchronization mark detection circuit to change the playback data without time axis fluctuation. A PCM recording and playback device characterized by comprising a time axis correction circuit that outputs output at a predetermined timing.