JPH0239036B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fixed head type PCM signal recording apparatus suitable for burst error correction, and more particularly to a PCM signal recording apparatus effective for a fixed head type PCM recording and reproducing apparatus.

In general, means for converting audio signals into PCM signals and magnetically recording and reproducing them can be broadly classified into rotating head systems and fixed head systems, depending on the mechanism used.

The advantages of the fixed head system are (1) the number of channels can be freely selected by increasing the number of tracks and widening the tape width; (2) Recording and playback can be performed for each channel (SYNC recording), and a portion of a recorded channel can be re-recorded (punch-in/out). (3) If the recording head and reproducing head are provided separately, the recording results can be monitored.

On the other hand, when recording digital signals, it is necessary to generate error correction parity data from the digital signal and record it together with the digital signal so that the errors can be corrected during playback. Since burst errors are less likely to occur in the width direction of the tape, a multi-track is usually configured, one track of which is allocated to record parity data, and the parity data is separated from the digital signal in the width direction of the tape. The correction ability is improved by recording with
A playback circuit and time base corrector are required for each track, increasing hardware costs.

In addition, in a multi-track fixed head type recording and reproducing device, the recording track extends in the tape's traveling direction (longitudinal direction), so the vertical movement of the tape,
The accuracy of the tape width becomes a problem, and to solve this problem it is necessary to make the track width wider than in the rotary head system and provide a card band between the tracks, but as a result, the recording surface density is reduced. On the other hand, if the track pitch and track width are narrowed in order to increase the areal density on the tape, there is a problem in that drop-outs due to dust on the tape are not limited to just one track, but also affect adjacent tracks.

Also, when recording one channel on one track, the tape speed must be increased.
Since the recordable time becomes shorter, in order to record for a long time, it is necessary to slow down the tape speed to, for example, 30 inches/second or less, and divide the PCM signal of one channel into two or more tracks. Not only does the increase in the number of tapes cause the above-mentioned problems, but there is also the problem that the range of influence of dropouts becomes wider as the tape speed is lowered.

Note that a method of time-divisionally transmitting multiple channels on one transmission path is known, but this method is useful when the amount of data transmitted per channel is small relative to the transmission capacity of the transmission path. This is a technology that divides a channel by transmission capacity and transmits each channel separately. However, there is still no known concrete method for effectively utilizing a recording medium such as a magnetic tape that is extended in the longitudinal direction and has a plurality of tracks arranged in the width direction.

On the other hand, interleaving technology is also known, which provides a transmission method that is enhanced against burst errors by changing the order of data, but this technology is related to one transmission path and cannot be used with recording media having multiple tracks. It is not known about its application in use.

The present invention has been made in view of these points, and effectively combines the long-known time division transmission method and interleave technology to effectively utilize a transmission path using a recording medium having multiple tracks. This invention provides a fixed head type PCM signal recording device that records signals on two or more tracks, which can widen the track width for recording digital signals, and can also reduce errors. To provide a fixed head type PCM signal recording device that can reduce the influence of burst errors on error correction parity data without separately providing a dedicated track for recording correction parity data.

An embodiment of the present invention will be described in detail below with reference to FIGS. 1 to 9.

Figures 1 to 3 show the basic form of the code structure related to the PCM signal recording method of the present invention, in which one channel of audio signal is converted to a PCM signal and distributed to n transistors for recording. Consider the case. First, one word of the PCM signal for each sampling period is set as W, and a word string of ⁿ² words is arranged in a matrix of n words on n tracks as shown in FIG. 1 to form an information bit sequence. At this time, each word is W ^m _n (m is 1 to n
).

Next, an error correction code, for example, a parity bit sequence P, is formed for this information bit sequence,
Arrange as shown in Figure 2. Each parity of this parity bit series P can be obtained by calculating words in the same column of the matrix-like information bit series in the direction across the tracks according to the mod.2 addition method.

For example, the parity P _n of the mth column is P _n =W ¹ _n ...W ^m _n ...W ⁿ _n (1) or P _n =W ¹ _n ...W ^m _n ...W ⁿ _n (1)'. However, is an operator that indicates addition of mod.2.

Similarly, the parity of the first to nth columns is determined, and in order to reduce the number of tracks, they are arranged so as to be distributed to each track after the information bit series as shown in FIG. As a result of such an arrangement, a matrix type code structure consisting of an information bit series of n rows and n columns and a parity bit series of n rows and 1 column is obtained.

At the stage of recording on the solid line, blocks of the information bit series and blocks of the parity bit series are separated by a distance of l words (where l is a positive integer) so that information is not lost at the same time due to a single dropout on the tape. The information is recorded in a time-division manner, and for each track, a CRC (Cyclic
Redundancy Check) code, etc. error detection code C
Add. The code structure arranged in this way is shown in FIG. In addition, in Fig. 3, for example
P ₁ ±l indicates that a parity P is placed at a position where parity P ₁ is placed in FIG. 2, and is located at a distance of l words in either direction relative to parity P ₁ .

Now, the rate at which errors occur due to dropouts, etc. in the track m of the tape recorded in the format shown in Fig. 3, errors are detected using the error detection code C _n , and the code structure shown in Fig. 2 is determined. The information on the lost track m can be duplicated by performing the following calculation on the decoded state.

W ^m ₁ = W ¹ ₁ …W ^m-1 ₁ …W ^m+1 ₁ …W ⁿ ₁ P ₁ (2) 〓 W ^m _n =W ¹ _n …W ^m-1 _n …W ^m+1 _n …W ⁿ _n P _n (2)′ 〓 W ^m _o =W ¹ _o …W ^m-1 _o …W ^m+1 _o …W ⁿ _o P _o (2)″ This can be further explained in Figures 4 to 6. Let us now consider the case where an error occurs in word W ^m ₁ of track m due to dropout, etc. For example, one word consists of 5 bits, and each word recorded on each n track when there is no error. If the bit string of track m has a value as shown in FIG. 4, its parity P ₁ becomes the bit string shown in the bottom row of FIG. Although an error occurs in word ^{W m 1 and the bit string of word W m 1} _{changes as} ^shown _in FIG. The value will be as shown in this 6th
The bit string of word W ^m ₁ in the figure is the same as the bit string of word W ^m ₁ in FIG. 4 before the error occurred, and it can be seen that the lost information has been restored.

FIG. 7 shows an embodiment in which the above-described invention is applied to a PCM signal recording and reproducing apparatus using, for example, a fixed head type tape recorder. In this embodiment, a case will be explained in which recording is performed on one channel and two tracks. In Fig. 7, an analog signal such as an audio signal is sampled at the input terminal 1, and one of the sampling outputs is an information bit series, for example, as shown in Fig. 8.
An information bit sequence consisting of 84 words W ₁ to _{W 84} is provided. Odd-numbered words W ₁ , W ₃ ...W ₈₁ , W ₈₃ of the input information bit series are processed by the parallelization circuit 2.
and even-numbered words W ₂ , W _{4 .} . . W ₈₂ , W ₈₄ are separated and arranged in parallel as shown in FIG. Odd-numbered words and even-numbered words are supplied to time-base compression circuits 3 and 4, respectively, where they are time-base compressed and used to insert parity P for error correction, a CRC code for error detection, and a synchronization signal SYNC. A period of missing data is formed.

On the other hand, the words arranged in parallel are also supplied to the parity forming circuit 5, where the parity for each column, that is, the words W ₁ and W ₂ is determined according to the above equation (1).
P ₃ , ...word for P ₁ , word W ₃ , W ₄
P ₈₁ is calculated for W ₈₁ and W ₈₂ , and P ₈₃ is calculated for words W ₈₃ and W ₈₄ . These parities P ₁ , P ₃ ,
... _P81 and _P83 are delayed by 2d words (d is the number of words in one block, for example) by the delay circuit 6.
P _1-2d , P _3-2d , ...P _81-2d , P _83-2d .

Delayed parity P _1-2d , P _3-2d , ...P _81-2d ,
_P83-2d is time-divisionally arranged in parallel by the parallelization circuit 7 as shown in FIG. 8, and inserted into the corresponding data missing period formed by the time axis compression circuits 3 and 4. For example, parity P _1-2d is a word
Parity P 3-2d is inserted after words W ₁ and W ₃ , and parity P _3-2d is inserted after words W ₂ and W ₄ to obtain a code structure in a matrix format of 2 rows and 3 columns. Similarly, other parities are sequentially inserted after each corresponding word, and the CRC codes generated from CPC code generation circuits 8 and 9 are added to the adder circuit for the 14 words inserted into each track within one horizontal period. 1
0 and 11 are added as shown in FIG. For example, in this example, parity P _25-2d , P _27-2d ,
After P _53-2d , P _55-2d , P _81-2d , P _83-2d respectively
A CRC code is added. Furthermore, the synchronizing signal SYNC generated by the synchronizing signal generating circuit 12 is added to the code thus formed by adding circuits 13 and 14 as shown in FIG.

Therefore, one word is 16 bits, parity is 16 bits, CRC code is 16 bits, and synchronization signal is 24 bits.
In terms of bits, one horizontal period per track, or 1/600 second, is (42 x 16 + 21 x 17 + 16 x 3
+24=1101 bits) will be inserted.

The PCM signals thus formed are supplied to recording heads 17 and 18 through amplifiers 15 and 16, etc., and are recorded at predetermined positions on magnetic tape 19.

Figure 9 shows the PCM when one horizontal period is tripled.
In the example shown in FIG. 9, 14 words are included in one horizontal period per track, that is, 1/1800 seconds.

Furthermore, in the case of reproduction, the above-described operation may be performed in reverse. That is, the synchronization signal is separated from the PCM signal extracted by playback from a fixed head tape recorder, etc., and then supplied to a decoder (not shown).
Here, processes such as time axis expansion, error detection, and error correction are performed to create parallel codes, which are then DA-converted and the analog output is passed through a low-pass filter (not shown).
You can take it out through it.

As is clear from the above description, according to the present invention, word-by-word parity data is generated from a plurality of words selected without duplication from each row of the matrix, so that errors caused by multiple bits can be avoided. In addition, since the parity data and the multiple words that generated the parity data are recorded in a time-division manner with a relative delay, burst errors can be corrected without having to provide a dedicated track for parity data. Correction ability can be improved and recording surface density can also be improved.

Furthermore, when recording PCM signals of multiple channels onto multiple tracks, it may be necessary to further narrow the track pitch and track width in order to increase the areal density on the tape. Therefore, when recording PCM signals of r channels (r is a positive integer of 2 or more) on each of n tracks (n is a positive integer of 2 or more), as shown in FIG. The r tracks are divided into n blocks so that each block contains r tracks, and the signals of one channel are recorded in n blocks so that they are recorded on n tracks that are at least one track apart from each other. However, since the R channel PCM signal is recorded in a track interleaved manner, even if errors occur in two or more tracks at the same time, the correction ability will not be degraded. Note that FIG. 10 shows the case where n=2. Note that the method of inserting the error detection code C shown in Fig. 3 is not limited to this, and the insertion gap can be adjusted depending on the recording density of the system, the nature of errors, etc. and word W of each row of multiple W is generated from word W of each row of W.
If the CRC code is C ¹ , ..., C ^m , ..., C ⁿ , and 〓=C ¹ 〓 C ^m 〓 C ⁿ , then 〓 ₁ 〓 ₂ 〓 ₃ 〓 ₁ 〓 ₄ 〓 ₅ 〓 ₆ 〓 ₂ …… Various other formats can be configured.

Furthermore, if you want to find the parity bit series P, use mod.2
Instead of adding , it may be found by simple addition,
For example, if the above equation (1) is expressed by simple addition, it becomes P _n =W ¹ _n +...+W ^m _n +...+W ⁿ _n (3).

[Brief explanation of drawings]

Figures 1 to 3 are schematic diagrams showing the basic code structure of the present invention, Figures 4 to 6 are schematic diagrams for explaining the case of restoring lost information, and Figure 7. FIG. 8 is a block diagram showing one embodiment of the present invention;
FIG. 9 is a schematic diagram for explaining the operation of FIG. 7, and FIG. 10 is a schematic diagram for explaining an embodiment of the present invention in the case of multiple channels. 2 and 7 are parallelization circuits, 3 and 4 are time axis compression circuits, 5 is a parity formation circuit, 6 is a delay circuit, 8,
9 is a CRC code generation circuit, 10, 11, 13,
14 is an adder circuit, 12 is a synchronization signal generation circuit, 1
7 and 18 are recording heads.

Claims (1)

[Scope of Claims] 1. A fixed head type PCM signal recording device that records at least one channel of digital signals on a plurality of tracks extending in the longitudinal direction of a recording medium and arranged in parallel in the width direction of the recording medium, wherein the at least one channel input means to which a digital signal is supplied; means for distributing the digital signal of at least one channel into a plurality of rows in a matrix form for each predetermined number of words; means for generating word-by-word parity data for the plurality of words from the plurality of words; and a word that generated the parity data by interposing each parity data with a word that generated other parity data. means for relatively delaying each parity data and a plurality of words that generated the parity data so as to be separated from each other by a predetermined length; 1. A fixed head type PCM signal recording apparatus, comprising a recording means for time-divisionally recording the parity data. 2 Digital signals of channels (r: a positive integer of 2 or more) are supplied to the input means, while n tracks (n: a positive integer of 2 or more) that are separated from each other by at least one track are supplied to the recording medium. 2. The fixed station according to claim 1, wherein r sets are formed, and the recording means time-divisionally records the digital signal of each channel and the parity data on each of the n tracks of each set. head method
PCM signal recording device.