JPH09213012A - Magnetic recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To edit a specific program without deteriorating the error resistance at the reproducing time by dividing a block of the same program into plural sectors and performing interleaving processing on a signal after adding an external code to a space between the sectors. SOLUTION: An input signal is converted into a signal divided into blocks A-C dividing one track of recording information in a processing circuit 82, and is then turned into a signal with external code parities, each added to each sector in the block by an external code encoder 83, and is sent to a switch circuit 84. A signal is sent by the circuit 84 to a 3-block interleaving processing circuit 85 at the usual recording time, and to a switch circuit 86 at the multiprogram recording time. An internal code parity is added to each sink block from the circuit 85 by an internal code encoder 87, and its output signal is sent to a processing circuit 88, and then an output signal of the circuit 88 is supplied as a recording current to a recording head 91.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a magnetic recording device for recording information signals such as video signals and audio signals on a magnetic recording medium such as a magnetic tape.

[0002]

2. Description of the Related Art A video tape recorder (hereinafter referred to as "V") also having a function as a magnetic recording device for recording information signals such as video signals and audio signals on a magnetic recording medium such as a magnetic tape.
(Abbreviated as TR), usually, when the recorded signal is reproduced, the reproduction output may be lost due to dropout, scratch, or the like. When the VTR is a digital VTR that converts an analog signal into a rectangular pulse digital signal having a short cycle and records the signal, if the reproduction output is lost as described above when the recording signal is reproduced, the reproduction is performed. The information obtained based on the output may be incorrect information. Therefore, in order to prevent these, an error correction code addition circuit is essential in a digital VTR, and this circuit is divided into an outer code addition circuit and an inner code addition circuit.

Further, when there are long dropouts and scratches, burst errors due to these occur, and in order to enhance the correction capability for these burst errors, digital information is divided into a plurality of blocks and interleaved. The method of performing is often used.

On the other hand, when recording digital data in a digital VTR, the recording method is as follows.
There are a normal method of recording one kind of data (for example, one program) on one track and a method of recording a plurality of kinds of data (for example, multiprogram) on one track.

FIG. 14 shows a block diagram of a recording system in a conventional digital VTR having a function as a magnetic recording device. Further, FIG. 15 is a schematic diagram showing a data processing process for one track at the time of normal (1 program) recording in the same conventional example, and FIG. 16 is a view showing normal (1 program) recording in the same conventional example. It is a schematic diagram of the track pattern of a data part.

A signal input from the input terminal 131 of FIG. 14 is divided into three blocks A to C composed of k byte × l sync block by the recording system signal processing circuit E132 as shown in FIG. The converted signal 151 is converted and supplied to the outer code encoder 133. The outer code encoder 133 has a signal 151 divided into three blocks.
Is a circuit for generating a signal 152 in which P bytes of outer code parity is added to each block.

Next, the signal 152 is supplied to a three-block interleave processing circuit 134. The inter-block interleaving processing circuit 134 is a circuit for generating a signal 153 in which sync block data is alternately extracted from each block of the three blocks of the signal 152 to which the outer code parity is added.

Next, the signal 153 is the inner code encoder 13
5 is supplied. The inner code encoder 135 outputs the signal 15
Add the inner code of Q bytes to each sync block of 3,
This is a circuit for generating the signal 154.

Next, the signal 154 is converted by the recording system signal processing circuit F136 into a signal composed of serial data suitable for recording after being subjected to sync and ID addition. The output signal composed of serial data from the recording system signal processing circuit F136 is supplied as a recording current to the recording head 139 via the modulator 137 and the recording amplifier 138.

The control signal supplied from the input terminal 140 is supplied to the recording system signal processing circuit E132, the outer code encoder 133, the inner code encoder 135, and the recording system signal processing circuit F136 for normal reproduction and multi-programming. It is used to optimally control each circuit.

As shown in FIG. 16, since the outer code is interleaved between three blocks in the track pattern, even if there is a scratch as shown in FIG. 3 times stronger than none.

FIG. 17 is a schematic diagram showing a data processing process for one track at the time of recording a multi-program (3 programs) in the conventional example, and FIG. 18 is a multi-program (3 programs) in the conventional example. It is a schematic diagram of a track pattern of a data part at the time of recording.

A signal input from the input terminal 131 of FIG. 14 is a recording system signal processing circuit E132, and as shown in FIG. 17, three programs of blocks A to C composed of k bytes × l sync blocks for each program. It is converted into a signal 171 divided into blocks and supplied to the outer code encoder 133. The outer code encoder 133 is a circuit that generates a signal 172 by adding P bytes of outer code parity to each block (each program) of the signal 171 divided into three blocks.

Next, the signal 172 is supplied to the inter-block interleaving processing circuit 134. The inter-block interleaving processing circuit 134 is a circuit that generates a signal 173 by alternately extracting sync block data from each block of the three blocks of the signal 172 to which the outer code parity is added.

Next, the signal 173 is the inner code encoder 13
5 is supplied. The inner code encoder 135 outputs the signal 17
Add the inner code of Q bytes to each sync block of 3,
A circuit that generates a signal 174.

Next, the signal 174 is converted by the recording system signal processing circuit F136 into a signal composed of serial data suitable for recording after being subjected to sync and ID addition. The output signal composed of serial data from the recording system signal processing circuit F136 is supplied as a recording current to the recording head 139 via the modulator 137 and the recording amplifier 138.

The control signal supplied from the input terminal 140 is supplied to the recording system signal processing circuit E132, the outer code encoder 133, the inner code encoder 135, and the recording system signal processing circuit F136 for normal reproduction and multi-program. It is used to optimally control each circuit.

As shown in FIG. 18, in the track pattern, the outer code is interleaved between three blocks (three programs). Therefore, even if there is a scratch as shown in FIG. 18, error correction for a burst error is performed. Ability is tripled compared to no interleave.

[0019]

However, in the magnetic recording device provided in the conventional digital VTR as described above, the data of a multi-program composed of a plurality of types of programs in one track, for example, data of three programs A to C. To record the three programs A
When it is necessary to record or update only a specific program of C to C (usually, VTR insert editing corresponds to this), an error correction encoder for performing interleave processing as shown in FIG. When the above three programs A to C are recorded using a VTR having a recording system provided, as shown in FIGS. 17 and 18, blocks A to C corresponding to the respective programs of the three programs A to C are added when the outer code is added. Since the programs C and C are interleaved, the three programs A to C can be recorded or updated at the same time, but only a specific program cannot be recorded or updated.

On the other hand, in order to record or update only a specific program of the three programs A to C, the information of the same program (same block) is recorded in a plurality of tracks at the same position of each track without inter-block interleaving. Preferably. However, if data is recorded at the same position on each track without interleaving, the error correction capability (error tolerance) with respect to errors, especially burst errors, deteriorates significantly.

In view of the above point, the present invention, in the data recording of a multi-program composed of a plurality of types of programs, does not deteriorate the error resistance at the time of reproducing the recorded data, and a certain program of the recorded data is recorded. (EN) Provided is a magnetic recording device capable of recording so that only the editing can be performed.

[0022]

In order to solve the above-mentioned problems, a magnetic recording apparatus according to claim 1 of the present invention comprises a plurality of digitized information signals arranged in parallel on a magnetic recording medium. A magnetic recording device for recording on a track,
An interleave in which an error correction code is added to an information signal in which one type of record information is divided into a plurality of blocks for error correction coding, and the information signals are alternately extracted and rearranged between the blocks. First error correction code adding means for outputting the processed signal as a recording signal for each track, and information in which a plurality of types of recording information are arranged corresponding to each block of a plurality of blocks for each recording information. Second error correction code adding means for outputting a signal not subjected to the interleave processing between the blocks as a recording signal for each track to the signal, and when recording one kind of recording information And a switch means for selecting the first error correction code adding means and for selecting the second error correction code adding means when recording a plurality of types of recording information. That.

According to this structure, when recording data of a multi-program composed of a plurality of types of programs, a block of the same program of the multi-program is divided into a plurality of sectors, and an outer code is added between the sectors. Interleave the subsequent signal.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION A magnetic recording apparatus showing an embodiment of the present invention will be described below with reference to the drawings.

A magnetic recording apparatus showing a first embodiment corresponding to claims 1 and 2 will be described. FIG. 1 shows a block diagram of a recording system in a digital VTR equipped with the magnetic recording device of the first embodiment.

In FIG. 1, the signal input from the input terminal 81 is recorded by the recording system signal processing circuit C82 as shown in FIG.
It is converted into a signal 119 divided into C and supplied to the outer code encoder 83.

The outer code encoder 83 has three blocks A to
As shown in FIG. 2, to each block of the signal 119 divided into C, a signal 12 in which P bytes of outer code parity is added
This is a circuit that generates 0. The signal 120 output from the outer code encoder 83 is supplied to a switch circuit 84 as a switch means.

The switch circuit 84 serves as a first error correction code adding means during normal recording (recording one program, that is, one type of digital information on one track) based on the control signal supplied from the input terminal 92. In the interleave processing circuit 85 between the three blocks, the multi-program recording (3 programs, that is, three kinds of digital information
At the time of recording on a track), a signal is supplied to each of the switch circuits 86 serving as switch means.

Interleave processing circuit 85 between three blocks
Is the same as the inter-block interleaving processing circuit 134 described in the prior art shown in FIG. 14, and the three blocks of the signal 120 to which the outer code parity is added are alternated from the three blocks.
This is a circuit for extracting sync block data.

Based on the control signal supplied from the input terminal 92, the switch circuit 86 outputs the signal of the inter-block interleaving processing circuit 85 during normal recording and the signal of the switch circuit 84 during multi-program recording to the inner code encoder. Output to 87. Inner code encoder 87
2 is a circuit for generating a signal 121 in which an inner code parity of Q bytes is added to each sync block, as shown in FIG. This signal 121 is supplied to the recording system signal processing circuit D88.

The recording system signal processing circuit D88 is a circuit which performs sync, ID addition, etc. on the signal 121 which is an input signal and converts it into a signal composed of serial data suitable for recording. The output signal of the recording system signal processing circuit D88 is supplied as a recording current to the recording head 91 via the modulator 89 and the recording amplifier 90.

The control signal supplied from the input terminal 92 is, in addition to the switch circuits 84 and 86, a recording system signal processing circuit C82, an outer code encoder 83, an inner code encoder 87, a recording system signal processing circuit D88, and a recording system. It is supplied to the amplifier 90 and is used to optimally control each circuit during normal recording and during multi-program recording.

Next, the data recording of the multi-program in the digital VTR equipped with the magnetic recording device of the first embodiment will be explained. FIG. 2 is a schematic diagram showing the process of processing data for one track during multi-program recording in the digital VTR equipped with the magnetic recording device of the first embodiment, and FIG. 3 is a data diagram during multi-program recording. The schematic diagram showing the track pattern of a part is shown. Here, a case where the multi-program is composed of three types of programs will be described as an example.

In FIG. 2, three kinds of programs A, B, and C constituting a multi-program are included in the recording system signal processing circuit C82, and each program has one block consisting of k bytes × i sync blocks. It is configured so as to correspond to each of the three blocks A to C, and is output as a signal 119 for one track. Signal 119
In the outer code encoder 83, as shown by the signal 120, P bytes of outer code parity is added to each block. Further, in the signal 120, the inner code encoder 87 adds Q-byte inner code parity to each sync block, as indicated by the signal 121.

The signal 121 has blocks A, B, and C on one track as in the track pattern shown in FIG.
Each program corresponding to each block is divided into three blocks and recorded, and a constant gap G exists between each block in the track length direction for editing for each program. However, the burst error resistance when scratches as shown in FIG. 3 are reduced to 1/3 as compared with the normal recording because the interleave processing is not performed.

By the above operation, as an error correction circuit in the digital VTR, it is possible to switch the presence / absence of interleaving processing during normal recording and during multi-program recording. During normal recording, interleaving processing between blocks is performed to cause a burst error. Although the endurance is strengthened and it is recorded without inter-block interleaving at the time of multi-program, information of the same program which is also the same block can be recorded at the same position of each track over a plurality of tracks. Editing such as recording or updating can be performed only on.

A magnetic recording apparatus according to a second embodiment corresponding to claims 3 and 5 to 9 will be described.
FIG. 4 shows a block diagram of a recording system in a digital VTR equipped with the magnetic recording apparatus of the second embodiment.

In FIG. 4, the signal input from the input terminal 1 is converted into a digital signal suitable for the error correction encoder in the subsequent stage by the recording system signal processing circuit A2, and is supplied to the switch circuit 3 as the switch means. It

Based on the control signal supplied from the input terminal 11, the switch circuit 3 uses the error correction encoder A4 as the first error correction code adding means in the normal recording and the second error in the multi-program recording. The signal is supplied to the error correction encoder B5 as the correction code adding means.
The outputs of the above two error correction encoders are supplied to a switch circuit 6 as a switch means.

Based on the control signal supplied from the input terminal 11, the switch circuit 6 outputs the signal of the error correction encoder A4 at the time of normal recording and the signal of the error correction encoder B5 at the time of multi-program recording to the recording system signals. Output to the processing circuit B7.

The recording system signal processing circuit B7 performs sync and ID addition to the input signal from the switch circuit 6, and
It is a circuit for converting into a signal composed of serial data suitable for recording. The output signal of the recording system signal processing circuit B7 is
The recording head 10 passes through the modulator 8 and the recording amplifier 9.
Is supplied as a recording current.

The control signal supplied from the input terminal 11 is, in addition to the switch circuits 3 and 6, a recording system signal processing circuit A2, an error correction encoder A4, an error correction encoder B5, a recording system signal processing circuit B7. , Is supplied to the recording amplifier 9 and is used for optimal control of each circuit during normal recording and during multi-program recording.

Next, the operation of the error correction encoder A4 shown in FIG. 4 will be described. 5 is a block diagram of the error correction encoder A4 shown in FIG. 4, and FIG. 6 is an error correction encoder A shown in FIG.
5 is a schematic diagram showing a process of processing data for one track in FIG.

In FIG. 5, the signal 551 input from the input terminal 21 is composed of three blocks, block A, block B and block C, as data for one track, as shown in FIG. It should be noted that one block is composed of data of k bytes × l sync blocks. Signal 5
Reference numeral 51 denotes an outer code encoder 22, which, as shown in FIG.
A signal 552 is formed by adding P bytes of outer code parity to each of the three blocks.

Next, the signal 552 becomes a signal 553 in which sync block data is alternately extracted from the three blocks to which the outer code parity is added, as shown in FIG. 6, in the inter-block interleaving processing circuit 23. .

Further, the signal 553 is the inner code encoder 2
At 4, the signal becomes a signal 554 in which the inner code parity of Q bytes is added to each sync block and is output to the output terminal 25, as shown in FIG.

FIG. 7 is a schematic diagram showing the track pattern of the data portion during normal recording (1 program / 1 track recording) in the second embodiment. In FIG. 7, 3
Outer codes of three blocks A, B, and C are interleaved among three blocks. Therefore, even if there is a scratch as shown in FIG. 7 on the tape, the error correction capability with respect to burst errors is enhanced three times as compared with the case without interleaving.

Next, the operation of the error correction encoder B shown in FIG. 4 will be described. Figure 8 shows multi-program (3 programs)
FIG. 9 is a block diagram of an error correction encoder B5 used at the time of recording, and FIG. 9 is a schematic diagram showing a data processing process focusing on the program A corresponding to the block A in the data of one track in the error correction encoder B5. is there.

In FIG. 8, the signal 805 input from the input terminal 51 is, as shown in FIG.
It is composed of three blocks, a block A, a block B, and a block C corresponding to each program of B and C. It should be noted that one block is composed of data of k bytes × m sync blocks. Further, one block is further composed of two sectors. The signal 805 is the outer code encoder 52.
Then, as shown in FIG. 9, the signal 806 is obtained by adding the outer code parity of P bytes to each of the two sectors.

Next, the signal 806 is the interleave processing circuit 53 between two sectors in the block, as shown in FIG.
The signal 807 is obtained by alternately extracting sync block data from the two sectors to which the outer code parity is added.

Further, the signal 807 is the inner code encoder 5
At 4, the signal becomes a signal 808 in which the inner code parity of Q bytes is added to each sync block and is output to the output terminal 55, as shown in FIG.

FIG. 10 is a schematic diagram showing a track pattern of the data part at the time of recording a multi-program (three programs) in the second embodiment. As shown in FIG.
One track is divided into three blocks corresponding to each program, and a certain gap G exists between blocks in the track length direction for editing each program. Further, since the outer code is interleaved between the two sectors in the block, even if there is a scratch as shown in FIG. 10 on the tape, the error correction capability for the burst error is the same as that of the first embodiment. Twice as strong as none.

By the above operation, by switching the error correction circuit between the normal recording and the multi-program recording, the multi-program recording can be performed without degrading the burst error resistance and the specific program can be edited. Can be

In the second embodiment shown in FIG. 4, as shown in FIGS. 5 and 8, the outer code encoder 22 of the error correction encoder A4 and the outer code of the error correction encoder B5 are used. Although the encoder 52 is independent, as shown in the signal 552 of FIG. 6 and the signal 806 of FIG. 9, the outer code parity added by each outer code encoder 22, 52 is the same parity composed of P bytes. Therefore, it is clear that the outer code encoders 22 and 52 can be shared.

In the second embodiment shown in FIG. 4, the inner code encoder 24 of the error correction encoder A4 and the inner code of the error correction encoder B5 are used as shown in FIGS. Although the encoder 54 is independent, as shown in the signal 554 of FIG. 6 and the signal 808 of FIG. 9, the inner code parity added by each inner code encoder 24, 54 is the same parity composed of Q bytes. Therefore, it is obvious that the inner code encoders 24 and 54 can be shared.

In this way, each outer code encoder 22, 5
The circuit scale can be reduced by sharing the 2 and the inner code encoders 24 and 54, respectively. However, when the outer code encoders 22 and 52 are shared, the amount of information per track during multi-program recording is reduced.

As described above, each outer code encoder 22,
FIG. 11 shows the configuration of another error correction encoder in which 52 and the inner code encoders 24 and 54 are shared, and the configuration will be described.

FIG. 11 shows a block diagram of another error correction encoder according to the second embodiment. In FIG. 11, the signal input from the input terminal 200 is supplied to the switch circuit 202 as the switch means after the outer code encoder 201 adds the outer code parity.

The switch circuit 202, based on the control signal supplied from the input terminal 208, makes the first
The signal is supplied to the inter-block interleave processing circuit 203 between the three blocks as the error correction code adding means, and the signal is supplied to the inter-block inter-sector interleave processing circuit 204 as the second error correction code adding means during the multi-program recording.

Interleave processing circuit 20 between 3 blocks
3 and inter-sector inter-block processing circuit 2 between 2 sectors
Each output signal of 04 is supplied to the switch circuit 205 as a switch means. Based on the control signal supplied from the input terminal 208, the switch circuit 205 outputs the output signal from the inter-block interleaving processing circuit 203 during normal recording, and the output from the inter-leaving processing inter-block inter-sector 2 between blocks during multi-program recording. The signal is supplied to the inner code encoder 206.

The signal to which the inner code is added by the inner code encoder 206 is output to the output terminal 207. The control signal supplied from the input terminal 208 is supplied to the outer code encoder 201 and the inner code encoder 206 in addition to the switch circuits 202 and 205, and the respective circuits are used during normal recording and multi-program. Used to optimally control the.

In the multi-program of the second embodiment, the information of the same program recorded corresponding to the same block is recorded at the same position between tracks as shown in FIG. , May be recorded at different positions.

In the second embodiment, the interleave processing is completed for each track, but the interleave processing may be performed over a plurality of tracks. By further performing the interleave processing between tracks in this way, the burst error resistance is further improved.

A case where the interleave processing is performed between tracks as described above will be described below as a third embodiment. FIG. 12 shows a block diagram of the error correction encoder in the third embodiment. In FIG. 12, the input terminal 1
The signal input from 11 is temporarily stored in the DRAM 113, and the outer code encoder 114 adds the outer code parity in the DRAM 113. With the addition of the outer code parity, the data is transmitted and received between the outer code encoder 114 and the DRAM 113, and the data is interleaved not only between blocks but also between tracks. As such, the memory control circuit 112 is
This is a circuit for controlling the AM 113.

The data after the addition of the outer code parity is added with the inner code parity by the inner code encoder 115 and is output to the output terminal 116. The input terminal 117 is a terminal for supplying a control signal for distinguishing between normal recording and multi-program recording. The control signal is the memory control circuit 11
2, outer code encoder 114 and inner code encoder 11
5 and controls the operation of each circuit according to the recording mode.

FIG. 13 shows an interleaving method of data when an outer code is added during normal recording according to the third embodiment. In this embodiment, at the time of normal recording, interleaving is performed between 3 blocks in a track and 6 tracks. Here, the data per track is 336 sync blocks, of which the outer code parity (C2) is 30 bytes (sync block), and the number of bytes per sync block is 99 bytes.

Therefore, the number of data per block is 1.
Out of the 12 sync blocks, the outer code parity (C
2) is 10 bytes (sync block). Also, D
(T, g, b) indicates data located at the track number t, the byte number b, and the sync block number g.

The interleave at that time is (Equation 1),
This is performed by a method based on (Equation 2), (Equation 3), (Equation 4).

[0069]

[Equation 1]

Where C = {C_n-1, C_n-2, ・ ・ ・, C
₀ }, C (X) = C_n-1 ・ X^n-1 + C _n-2 ・ X^n-2 +
... + C₀ It expresses. On the other hand, at the time of multi-program,
Divide one block for normal recording into two sectors and
Interleave processing between 2 sectors and 6 tracks
I do. D (t, g, b) is the track number t,
Position b, sync block number g
Data shall be shown.

When the number of sync blocks per sector at that time is R, the interleaving at this time is (Equation 5),
This is performed by a method based on (Equation 6), (Equation 7), (Equation 8).

[0072]

[Equation 2]

As described above, if the inter-track interleaving is further applied to the second embodiment, the burst error resistance is further improved. At this time, inter-track interleaving is performed for 6 tracks in the third embodiment, but the number of tracks may be arbitrarily determined.

In the first, second and third embodiments, the number of blocks per track at the time of normal recording is 3, but the burst error resistance improves as the number of blocks increases. Is clear.

Further, in the second and third embodiments, the number of sectors per block at the time of multi-program is set to 2, but it is clear that the burst error resistance is improved as the number of sectors is increased. is there.

Further, in the first, second and third embodiments, the number of blocks per track during normal recording and the number of blocks (programs) during multi-program are set equal to three. By making the number of blocks equal, the circuit scale can be reduced by sharing the signal processing circuit such as block division.

[0077]

As described above, according to the present invention, at the time of data recording of a multi-program composed of a plurality of types of programs, a block of the same program of the multi-program is divided into a plurality of sectors, and It is possible to interleave the signal after the outer code is added between the sectors.

Therefore, in multi-program data recording, recording can be performed so that only a specific program of the recorded data can be edited without deteriorating the error resistance at the time of reproducing the recorded data. In multi-program data recording, if the number of blocks corresponding to the number of programs is equal to the number of blocks per track during normal recording, the circuit scale of the device can be reduced. In the data recording of the multi-program, if the inner code encoder or the outer code encoder is shared with the normal recording, the circuit scale of the device can be further reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a recording system of a digital VTR according to a first embodiment of the present invention.

FIG. 2 is a data processing diagram at the time of recording three programs / one track according to the same embodiment.

FIG. 3 is a track pattern diagram during three-program / one-track recording of the same embodiment.

FIG. 4 is a recording system block diagram of a digital VTR according to a second embodiment of the present invention.

FIG. 5 is a block diagram of an error correction encoder for normal recording according to the same embodiment.

FIG. 6 is a data processing diagram for one track of the error correction encoder according to the same embodiment.

FIG. 7 is a track pattern diagram during one program / one track recording according to the embodiment.

FIG. 8 is a block diagram of an error correction encoder for recording a multi-program according to the same embodiment.

FIG. 9 is a data processing diagram of one block of the error correction encoder according to the same embodiment.

FIG. 10 is a track pattern diagram during three-program / one-track recording according to the same embodiment.

FIG. 11 is a block diagram of another error correction encoder according to the same embodiment.

FIG. 12 is a block diagram of an error correction encoder according to a third embodiment of the present invention.

FIG. 13 is an explanatory diagram of an interleaving method when an outer code is added during normal recording according to the same embodiment.

FIG. 14 is a block diagram of a recording system in a conventional digital VTR.

FIG. 15 is an explanatory diagram of data processing at the time of recording one program / one track in the conventional example.

FIG. 16 is a track pattern diagram during one program / one track recording in the conventional example.

FIG. 17 is an explanatory diagram of data processing at the time of recording 3 programs / 1 track in the conventional example.

FIG. 18 is a track pattern diagram at the time of recording three programs / one track in the conventional example.

[Explanation of symbols]

3 switch circuit 4 error correction encoder A 5 error correction encoder B 6 switch circuit 84 switch circuit 85 3 inter-block interleave processing circuit 86 switch circuit 202 switch circuit 203 3 inter-block interleave processing circuit 204 intra-block 2 inter-sector interleave processing circuit 205 switch circuit

Claims (9)

[Claims] 1. A magnetic recording device for recording a digitized information signal on a plurality of tracks arranged in parallel on a magnetic recording medium, wherein one type of recording information is divided into a plurality of blocks. On the other hand, an error correction code is added to perform error correction coding, and an interleaved signal that alternately extracts and rearranges information signals between the blocks is output as a recording signal for each track. The first error correction code adding means and the information signal in which a plurality of types of record information are arranged corresponding to each block of a plurality of blocks for each record information, and the interleaving process between the blocks is performed. Second error correction code adding means for outputting a signal which is not applied as a recording signal for each track, and first for recording one kind of recording information.
And a switch means for selecting the second error correction code adding means when a plurality of types of recording information are recorded. 2. When recording an information signal in which a plurality of types of recording information are arranged corresponding to each block of a plurality of blocks for each recording information, the blocks corresponding to the same type of recording information are spread over a plurality of tracks. The magnetic recording device according to claim 1, wherein the magnetic recording devices are arranged at the same position on each track. 3. When recording an information signal in which a plurality of types of recording information are arranged corresponding to each block of a plurality of blocks for each recording information, each block is divided into a plurality of sectors by the second error correction code adding means. 3. The magnetic recording device according to claim 1, wherein the magnetic recording device is divided into two and interleaved between the respective sectors. 4. The magnetic according to claim 1, 2 or 3, wherein the first error correction code adding means and the second error correction code adding means are configured to perform interleave processing between a plurality of tracks. Recording device. 5. The method according to claim 1, wherein the number of blocks per track when recording one kind of recording information is equal to the number of blocks per track when recording plural kinds of recording information. The magnetic recording device according to any one of 1. 6. The first error correction code adding means and the second error correction code adding means, when recording one kind of record information and when recording plural kinds of record information, are duplicated or more. 6. The magnetic recording apparatus according to claim 1, further comprising one error correction code adding means configured to perform error correction coding with the same number of check symbols. 7. The method according to claim 6, wherein the first error correction code adding means and the second error correction code adding means share the inner code adding means for adding an inner code parity as error correction coding. Magnetic recording device. 8. The method according to claim 6, wherein the first error correction code addition means and the second error correction code addition means share the outer code addition means for adding the outer code parity as error correction coding. Magnetic recording device. 9. The first error correction code adding means and the second error correction code adding means include an inner code adding means for adding an inner code parity as error correction coding and an outer code parity as error correction coding. 7. The magnetic recording apparatus according to claim 6, wherein both the external code adding means to be added and the external code adding means are shared.