JPS63306568A - Digital recording and reproducing device - Google Patents

Abstract

PURPOSE:To accurately reconstitute code blocks at the time of punch-in/-out by adjusting the quantity of a reproducing signal obtained from a recording medium and returning the quantity to a value within a prescribed range when a writing position in a relocation memory is shifted from a prescribed range. CONSTITUTION:A deinterleaving circuit 22 is provided with a relocation memory for controlling the recording positions of blocks by using continuous block numbers assigned to respective blocks to relocate digital data. When the writing position of digital data in the relocation memory is shifted from the prescribed range, the writing quantity of digital data in the relocation memory is adjusted by adjusting the quantity of reproducing signal from the recording medium 17 by a 2nd clock generator 27 so that the writing position is returned to the prescribed range. Since the writing position is always kept in the prescribed range, the code blocks can be accurately reconstituted, always normal reproducing operation can be executed and a highly accurate digital recording/ reproducing device can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital recording and reproducing apparatus capable of performing bunch-in and punch-out recording of digital audio signals and the like.

[Conventional technology]

2. Description of the Related Art Conventionally, a fixed head type digital recording/reproducing apparatus is known which converts a 2-channel or 16.32-channel audio signal into a digital signal and records the digital signal on a plurality of tracks. These digital recording and reproducing devices are required to be capable of bunch-in and punch-out (hereinafter referred to as punch-in/out) recording, in which a signal continuous with the original signal is recorded on top of an already recorded signal. ing. FIG. 7 shows the configuration of a magnetic head for performing this pan-nine/out operation. 17 is a magnetic tape as a recording medium, 13 is a recording head, and 12 is a reproduction head. FIG. 7(a) shows a recording-reproducing-recording head configuration, and FIG. 7(b) shows a reproducing-recording-reproducing head configuration. Two configurations are possible because a playback/recording head is required to perform punch-in/out, and a record/playback head is required to perform time monitoring. Punch-in.

First, the reproduction head 12 reproduces the original signal back to an audio signal, re-encodes it, and switches to the recording mode just when a predetermined signal passes through the recording head 13. Punch-out will cancel the recording mode. FIG. 8 shows a punch-in/out signal format, in which signal B is recorded in a certain section of signal A. Sections 48 and 49 at the joint between signal A and signal B are cross-faded, respectively.One section 50 indicates a newly recorded portion.In one section 50, the continuity of the magnetic tape pattern at the recording start section C and the recording end section is shown. becomes a problem. That is, even if you try to precisely measure the distance between the reproducing head 12 and the recording head 13 in FIG. 6 to match the timing from the reproducing mode to the recording mode, the distance between the heads may change due to uneven running of the tape running system, wear, etc. The changes cause discontinuities in the tape pattern.

In order to solve these problems, various digital recording and reproducing devices have recently been proposed. Figure 9 is JP-A-5
8-9204 is an explanatory diagram showing a recording format of a multi-channel PCM recording and reproducing apparatus as a conventional digital recording and reproducing apparatus of this type. In the figure, 17 is a magnetic tape, 51-1 to 51- 8 is an information track in which information of one audio channel and a total of 8 channels is recorded, and 52-1.52-2 are the information tracks 51-1 to 52-2.
This is a redundant track in which a redundant signal, for example, a parity check code, for error correction of the audio information data of 51-8 is recorded.

FIG. 10 is an explanatory diagram showing a method of adding the redundant tracks 52-1, 52-2, and a2 to a1 are information tracks 5
Information signals recorded in 1-1 to 51-8, 01
~c2 is the redundant signal for error correction recorded on the redundant tracks 51-1 and 52-2, and b is the bit length.

To create redundant tracks 52-1 and 52-2, information signals a1 to a of b bits each are extracted from adjacent positions in the tape width direction from the information tracks 51-1 to 51-8, and a total of 8b bits are extracted. The error correction signal cLtc1 is obtained from the information signal of the redundant track 52-1.52-.
Record in 2.

Figure 11 is an explanatory diagram showing the configuration of one block.
In Figure 1, a large number of the data shown in Figure 0 are arranged in the tape running direction, and redundant signals are also added in the tape running direction. 1 to 51-8, redundant track 52-1.
Both 52-2 are redundant signals added every 7b bits.

The redundant signals d□-di. is usually a cyclic redundancy check.
ancyCheck (hereinafter referred to as CRC) code algorithm, and the CRC generated in this way
A synchronization mark S is further added to the code (information signal - redundant signal) for each track. Hereinafter, the period from the synchronization mark S to the redundant signal di (i=1 to 10) will be referred to as a frame. These frames are collected for 10 tracks and constitute one code block CB.

According to the above recording format, 2 out of 1 code block
It is known that errors up to the track can be corrected.

Therefore, even if the recording condition of any one track is poor and code errors occur frequently, they can be sufficiently corrected. In addition, even if one track completely fails and becomes inoperable, it can be corrected even if dropouts occur in other tracks, so the operation of the recorder will not be affected and the stability of the recorder will be greatly improved. This means that there has been an increase.

Figure 12 is an explanatory diagram showing the changes in information when punching in/out is performed in such a multi-channel PCM recording/playback device. This is one section of 17.

Next, the operation will be explained. Conventional digital recording and reproducing devices are equipped with a time axis correction circuit that uses multiple types of synchronization mark detection signals to output playback data at a predetermined timing without time axis fluctuation in order to correctly reproduce bunch-in/out locations. This ensures that code blocks can be reconstructed correctly. In other words, two types of synchronization marks S, and S are prepared, and surface synchronization marks are added to each at a fixed period during recording.
.

Assume that a synchronization mark S0 is added to every four frames, and a synchronization mark S1 is added to the remaining frames. In this case, the recording format becomes as shown in FIG. 13, and by paying attention to the synchronization mark SI, there is no danger of regarding the combination of frames indicated by diagonal lines as one code block. That is, the number of frames from the frame with the synchronization mark S0 is constantly counted, and based on the counted value, a code block is reconstructed using frames with the same counted value.

[Problem that the invention seeks to solve]

Since the conventional digital recording/reproducing device is configured as described above, the synchronization mark S is generated during bunch-in/out. There is a problem in that if a deviation of 172 or more occurs in the interval, the code block cannot be reconstructed.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a digital recording/reproducing apparatus that can accurately reconstruct code blocks during bunch-in/out.

[Means for solving problems]

The digital recording and reproducing apparatus according to the present invention rearranges digital data by adding consecutive block numbers to each block and controlling the recording position in the rearrangement memory using this block number. The positional relationship between writing and reading digital data to the relocation memory is determined, and if the writing position deviates from a predetermined range, the detecting means detects this and adjusts the reproduction signal amount of the recording medium. The writing position of digital data in the relocation memory is returned to within a predetermined range.

[Effect]

The detection means in the present invention detects a shift in the writing position in the relocation memory caused by jumps in block numbers or redundant rearrangements during playback, and if the shift in the write position exceeds a predetermined range, By instructing the adjusting means to adjust the amount of reproduced signals from the recording medium, the writing position of digital data in the relocation memory is maintained within a predetermined range.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
FIG. 2 is a block diagram showing a digital recording and reproducing apparatus according to an embodiment of the present invention, and FIG. 2 shows a recording format for recording and reproducing two-channel digital audio signals on a magnetic tape using an 8-track fixed head. FIG. FIG. 2(a) shows the frame structure, and one frame consists of P
It consists of a total of 360 bits: 16 samples of CM data (PD) (320 bits), 16 bits of synchronization signal (S), 8 bits of identification signal (1), and 16 bits of 01 check data for error detection and correction. There is. Also, FIG. 2(b) shows the block configuration, and the frame-configured signal is converted into PCM.
6 tracks for data PD processing to PD, C2P□ for error detection and correction.

It is recorded as C2P on two tracks, a total of eight tracks.

The configuration of the identification signal I is as follows: 1-1.1-2 is ID data for identifying sampling frequency, quantization bit number, tape speed, etc., 1-3.1-4 is a block number, and 1-5 to 1- 8 is c3 parity.

This error correction code uses a Reed-Solomon code.1For example, input data V is v= ('rDxe &+ 8%g BAOI C3P
3# C3P2# C3Px + C3Pa), and when the quality check matrix IH is given, v-H
C3P, to C3P8 are generated so that t=O. Here, a is, for example, the root of the primitive polynomial Xa+X4+X3+X2+1 on OF (2'). 1-1~1-
8 is 8 bits each, so the block numbers are BAl, B
In total, 16 bits can be obtained from A and A, which is long enough to perform punch-in/out.

In addition, in FIG. 1, 2 is an analog signal input terminal;
3 is an analog-to-digital conversion circuit (hereinafter referred to as an A/D conversion circuit); 4 is a first switch; 5 is an interleaving circuit that rearranges data from the first switch 4; 6;
is a Cs encoder connected to the interleave circuit 7, 7 is a C3, C1 encoder, 8 is a block number generation circuit connected to the C3, C1 encoder 7, 9 is a synchronization signal addition circuit, 10
1 is a delay circuit for synchronizing punch-in/out recording timing; 11 is a modulator for converting digital data into a pattern to be recorded on the magnetic tape 17; 12 and 14 are playback heads; and 13 are recording heads.

15 is a second switch, 16 is a capstan motor that controls the running of the tape, 18 is a demodulator that converts the signal reproduced on the magnetic tape 17 into digital data, and 19 is a wow and flutter, jitter, etc. generated by the magnetic tape and the running mechanism. 20 is the output of this time axis correction circuit 19 and is a servo circuit; 21 is a C1, C3 decoder; 2
2 is a dinterleave circuit that restores the order of data from the C1 and C3 decoders 21, 23 is a C2 decoder connected to the dinterleave circuit 22, and 24 is a digital-to-analog conversion circuit (hereinafter referred to as D/A (referred to as a conversion circuit); 25 is an output terminal for analog signals from the D/A conversion circuit 24;
6 is the first clock supplying the clock to the area 28 surrounded by the dotted line.
The clock generator 27 is a second clock generator that supplies a clock to the area 29 surrounded by the dotted line and acts as a regulating means.

Next, the operation will be explained. First, normal recording.

Here, a case where simultaneous monitoring is performed will be explained.

The analog signal input from the input terminal 2 is sampled by the A/D conversion circuit 3 at a sampling frequency of 48 KHz, and then converted into digital data with a quantization bit count of 16. This digital data passes through the first switch 4, and the interleave circuit 5 rearranges the data order. During this time, the C2 encoder 6 performs Reed-Solomon encoding. The output C3 from the interleaving circuit 5 and the C1 encoder 7 perform encoding within one block. That is, the block number generator 8 generates a 16-bit block number BA, .
BA is generated, C3 encoding as shown in FIG. 2(b) is performed 1, and then C1 encoding is performed for each frame in the longitudinal direction of the tape. This error correction encoded data is sent to the synchronization signal adding circuit 9, where a synchronization mark S is added, and sent to the delay circuit 10. The data delayed by the delay circuit 10 is sent to the modulator 11, modulated, and recorded on the magnetic tape 17 by the recording head 13i.

Next, the signal reproduced by the reproduction head 14 passes through the second switch 15 and is demodulated by the demodulator 18, after which the jitter is absorbed by the time axis correction circuit 19, and the signal is transmitted to the C1 and C3 decoders 21.
sent to. In the ci, cs decoder 21, the C1 decoder first detects and corrects errors in the tape longitudinal direction, and then the C3 decoder detects and corrects block numbers BA1. BA is corrected. Digital data is input to the dinterleave circuit 22 using these block numbers BA, . . . BAll. The servo circuit 20 drives the capstor motor 16 in synchronization with the clock of the second clock generator 27.

Next, a block diagram of the dinterleaving circuit 22 and the second clock generator 28 is shown in FIG.
is the data input terminal, 37 is the block number BA, BA
, 38 is a data output terminal, 30 is a memory for data rearrangement and dinterleaving, 31 is an address selection circuit for the memory 30, and 32 is for outputting data to the D/A conversion circuit 24. 33 is a write/read address circuit for exchanging data with the C2 decoder 23, 34 is a write address circuit for writing data into the memory 30, and 35 is a memory write position detection circuit that acts as a detection means. It is. C1. input to the input terminal 36. C3 decoder 21
The data from is written to the memory 30 according to the address generated by the write address circuit 34 based on the corrected block number BA□, BA input to the input terminal 37, and the data written to the memory 30 is read from the input terminal 37. The data is read out according to the address generated by the address circuit 32 and output from the output terminal 38 to the D/A converter 24.

This rearranges the digital data and ensures that the original block is constructed. While the digital data is rearranged in the dinterleave circuit 22, the data in the memory 30 is transferred to the C2 decoder 23 based on the address generated by the write/read address circuit 33.
The data sent to the D/A converter 24 from the output terminal 38 is converted to the original analog signal, and then sent to the D/A converter 24 from the output terminal 38. 25 as a reproduction signal.

On the other hand, the second clock generator 27 includes a phase detector 39,
This is a general PLL oscillator consisting of a voltage controlled frequency variable oscillation base 401 and a frequency divider 41, 42 is a system clock output terminal, and 43 is a control clock output terminal to the servo circuit 20. This second clock generator 27 locks with the reference clock from the first clock generator 26, and if there is no detection signal from the memory write position detection circuit 35, the second clock generator 27 uses the same clock as the first clock generator 26. The division ratio of the frequency divider 41 is set so as to generate . Here, in the area indicated by 29 in FIG. 1, the tape speed is adjusted in synchronization with the clock frequency of the second clock generator 27, and the amount of reproduced signal can be varied. Since the memory 30 of the dinterleave circuit 22 operates with a clock having the same frequency, the input signal amount and the output signal amount of data are the same, and the memory 30 operates normally.

Next, the case of punch-in/out will be explained. Switches 4 and 15 are initially bl.

A, side is selected. While listening to the signal A reproduced by the reproduction head 12 from the output terminal 25, the first switch 4 is switched to the a□ side in order to record the signal B. Dinterleave circuit 22. Delay time in interleave circuit 5,
The total time including the delay time in the delay circuit 10 is determined by the playback head 1.
It is sufficient to record the signal in the same manner as the time taken for the signal reproduced in step 2 to pass through the recording head 13. In this case, all tracks are rewritten. As mentioned above, the delay circuit 10
Even if the delay time of block number BA1. Since the BA is recorded, there is no problem in configuring the original block even if the block numbers jump or overlap.

FIG. 4 is a data flow diagram of block reconfiguration in such a dinterleave circuit 22.

44 is a delay section required for dinterleaving.

45 is a tinter leave, which is a cyclic memory 3 of the circuit 22.
This is the allowable range of the writing position of 0 input data. Fourth
Figure (a) shows a case where a data string with block numbers 1, 2, 3, 4, etc. is input to the memory 30. There are no jumps or duplications of block numbers, and the writing position to the memory 30 is at a fixed position. It is A. Figure 4(b) shows block numbers 1, 2,
4,5. There is a jump in block numbers indicating that a data string of... is input, and in order to rearrange the blocks, memory 3 is
0 is shifted from the regular position A to position B, which is one block away. In this case, the data of block number 3 is missing, but the block arrangement returns to the original, so the C2 decoder 23 corrects the error. Corrections can be made. FIG. 4(c) shows the block number sequence 1.2, 2.3, 4. ...indicates a case where the data string is input. There is a duplication of block numbers, and in order to rearrange the blocks, the writing position to the memory 30 is changed when writing the input data of the second block number 2. In the case of Figures 4(b) and 4(c), where the data is moved from the regular position A to a position @C that is shifted by one block in the opposite direction to B, the data writing position moves from A-48, A to C. A tolerance range 45 for the writing position of input data is provided so that there is no problem even if the input data is shifted by several blocks in the same direction.

However, if this tolerance range 45 is exceeded, the delay period 44 necessary for dinterleaving is entered, and normal dinterleaving cannot be performed.

Therefore, in the present invention, the allowable range 45 of the write position of the memory 30 is divided into three sections shown below.

This is detected by the memory write detection position circuit 35, and the amount of data input to the memory 30 is controlled by changing the frequency division ratio of the frequency divider 41 of the second clock generator 27. This operation will be explained with reference to FIG.

The allowable range 45 of the writing position of input data is sectioned, and E
, F. If block skipping occurs multiple times and the writing position falls within section F.

This is detected by the memory write position detection circuit 35.

The frequency division ratio of the frequency divider 41 of the second clock generator 27 is increased to make the clock in the area indicated by 29 in FIG. 1 lower than the clock of the first clock generator 26, thereby reducing the amount of signal reproduction. . Then, in the memory 30, the read signal amount is constant and the write signal amount decreases, and the write position returns to the interval. Further, if duplication of block numbers of the reproduced signal occurs multiple times and the write position falls within the section E, this is detected by the memory write position detection circuit 35.

The frequency division ratio of the frequency divider 41 of the second clock generator 27 is reduced, and the clock in the area 29 is transmitted to the first clock generator 26.
to increase the amount of signal reproduction. Then, in the memory 30, the read signal amount is constant and the write signal amount increases, and the write position returns to the interval.

Next, the detection characteristics of the memory write position detection circuit 35 are determined as follows.
In the figure, the horizontal axis shows the write position to the memory 30, interval E, F, and the vertical axis shows the clock frequency of the second clock generator 27. When entering interval F from one interval, Feedback is applied to lower the clock frequency of the clock generator 27 of No. 2 to return to the interval, but here, once it enters interval F and the clock frequency decreases, the clock frequency is lowered until it returns to the center position A of 1 interval. A hysteresis is provided to prevent oscillation. Similarly, when entering section E from section 1,
Feedback is applied to increase the clock frequency of the clock generator 27 to return to the interval, but once it enters the interval E and the clock frequency increases, the sensor position A of the interval
The clock frequency is kept raised until it returns to , providing hysteresis. Since the rate of increase and decrease in the clock frequency of the second clock generator 27 changes the system clock of the area 29 including the servo circuit 20, it is necessary that the rate of increase and decrease in the clock frequency of the second clock generator 27 is set to such an extent that the reproduction servo does not lose lock.

In the above embodiment, the frequency of the second clock generator 27 is increased or decreased in steps in FIG. The area can be quickly returned to the center position A.

Further, in the above embodiment, the memory for relocating data and the memory for dinterleaving are the same memory, but they may be configured with separate memories.

Furthermore, in the above embodiment, block skipping and block duplication that occurred during punch-in/out were explained, but if the part where the magnetic tape was cut once in the one-hand cut editing process is reconnected with splimming tape, During priming, two magnetic tapes are connected overlapping each other or with a gap between them, and in this case too, block skipping and block duplication occur, but it can be applied in such cases, and the method described above can be applied. The same effects as in the embodiment are achieved.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a relocation memory that rearranges digital data by controlling the recording position of the block using consecutive block numbers added to each block. When the writing position of the digital data deviates from the predetermined range, the amount of the digital data written to the relocation memory is adjusted by adjusting the amount of reproduction signal from the recording medium, and the writing position is brought into the predetermined range. Since the configuration is such that the writing position is always kept within a predetermined range even if the writing position to the relocation memory shifts due to jumps in block numbers or duplicate relocation during playback, the writing position is always kept within a predetermined range. This has the effect of providing a highly reliable digital recording and reproducing apparatus that can accurately reconstruct code blocks, always perform normal reproducing operations, and has a high reliability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a digital recording/reproducing apparatus according to an embodiment of the present invention, and FIG. 2(a) is a block diagram showing a digital recording/reproducing apparatus according to an embodiment of the present invention. FIG. 2(b) is an explanatory diagram showing the data structure of the l block, FIG. 3 is a block diagram showing the details of the dinterleave circuit and the clock generator 2 of FIG. 2, and FIGS. 4(a)--
Figure 4(c) is a data flow diagram of the memory that rearranges blocks, Figure 5 is a conceptual diagram for explaining the operation of the memory write position detection circuit, and Figure 6 shows the characteristics of the memory write position detection circuit. Explanatory diagrams shown, Fig. 7(a), Fig. 7(
b) is a configuration diagram of a magnetic head for performing bunch-in/out, FIG. 8 is an explanatory diagram showing the signal form of bunch-in/out, FIG. 9 is a format diagram showing the recording format of a conventional digital recording/reproducing device, and FIG. FIG. 10 is a configuration diagram showing the configuration of the redundant track, and FIG. 11 is a configuration diagram showing the configuration of one block. FIG. 12 is a signal format diagram for punch-in/out, and FIG. 13 is a format diagram showing a recording format when two types of synchronization marks are provided. In the figure, 1-3. '1-4 is the block number, 17 is the magnetic tape (recording medium), 27 is the second clock generator (adjustment means), 3o is the memory (relocation memory), 35 is the memory write position detection circuit (detection means) . In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation No. 7 @ll8I! !

Claims (1)

[Claims] Punch-in, punch-in, in which digital data of a single or multiple channels is distributed to multiple tracks, a synchronization signal is periodically added to each track to form a frame, and the frames of each track are recorded almost simultaneously. In a digital recording/playback device capable of out-recording, the frames of the plurality of tracks recorded simultaneously are treated as one block, a consecutive block number is added to each block, and the recording position of the block is determined using the block number. A relocation memory that rearranges the digital data by controlling the relocation memory, and a positional relationship between a write position and a read position of the digital data in the relocation memory, and detects when the write position deviates from a predetermined range. A detection means for generating a signal and an amount of reproduced signal from the recording medium are adjusted based on the detection signal from the detection means, thereby adjusting the amount of the digital data written to the relocation memory. A digital recording/reproducing apparatus comprising: an adjusting means for returning the writing position to within the predetermined range.