JPH0377589B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a multichannel PCM data recording method in which PCM signals obtained by PCM modulating audio signals of multiple channels are recorded on a magnetic tape as multiple tracks using a fixed head. The required functions for a fixed head type PCM recording/playback device are the ability to perform synchronized recording, in which a recorded channel is played back while recording on another channel, and the punch-in function, in which a part of a recorded channel is corrected and re-recorded. , the ability to perform punch-out editing, and the ability to perform these functions independently for each channel. When realizing such a function, if the discrimination signal for each channel is recorded sequentially on one control track, the discrimination signal for a predetermined channel of this control track can be recorded during sync recording and editing as described above. This results in problems in that the configuration for this becomes complicated and there is a greater possibility of errors occurring during rewriting. In consideration of this point, the present invention records the discrimination signal, which may be rewritten for each channel, on the same track as the data of the corresponding channel. The discrimination signals that can be rewritten for each channel (parameters that can be set for each channel) include a discrimination signal that indicates whether the quantization for that channel is linear or nonlinear, and a signal that indicates whether pre-emphasis has been performed for that channel. There is a discrimination signal that indicates whether or not the vehicle is present.
In one embodiment of the present invention described below, a determination signal is added to determine whether the pre-emphasis is on or off. Further, an embodiment of the present invention will be described with reference to the drawings. In this example, the PCM signal is recorded in any of three recording formats having different numbers of occupied tracks per channel. The number of data tracks formed on a magnetic tape depends on the width of the magnetic tape. As shown in FIG. 1, a 1/4 inch wide magnetic tape 1 has eight data tracks TD ₁ to TD _8.
is formed. Tracks TA ₁ and TA ₂ on which analog signals are recorded along the upper and lower edges of the magnetic tape 1
is formed, and eight data tracks TD ₁ to TD ₈ , a control track TC, and a time code track are formed between analog tracks TA ₁ and TA ₂ .
TT is located. In this case, the control track TC is located above the center of the magnetic tape 1 (indicated by the dashed line), and the data track is located between the analog track TA ₁ and the track TC.
The time code track TT is located below the center of the magnetic tape ₁ , and the time code track TT and _the analog track
Data tracks _TD5 to _TD8 are located between _TA2 . Data track as shown
For TD ₁ to _{TD 8} , (track pitch: a) (track width: b) (guard width: c), and for analog tracks TA ₁ and TA ₂ , (clearance:
d) (Track width: e) and tape width is f, each dimension is determined as follows. a = 480 [μm] b = 280 ~ 380 [μm] c = 200
~100 [μm] d = 540 [μm] e = 445 [μm]
f=6.30 [mm] ⁺⁰ _-20 [μm] An example of the recording format for this 1/4 inch tape width is shown below.

[Table] The above tape speeds are values when the sampling frequency f _s of the PCM signal is 50.4 [kHz]. The sampling frequency f _s is also 44.1 [kHz],
32.0 [kHz] is possible, and the tape speed in that case is
The value will be different from the above value. Furthermore, the PCM signal configuration and modulation format are common to each format. FIG. 2 shows one unit (one selector) of control track TC and data track TD (=TD ₁ to TD ₈ ). The data recording head forms a data track TD, the data reproducing head reproduces the track TD, and the control recording head forms a control track TD.
A track TC is formed and the track TC is played back by the control playback head. This data track TD recording/playback and control track TC
It is assumed that the recording and playback of the two are mutually synchronized.
In other words, by arranging the heads so that the magnetic gaps of the data recording head and the control recording head coincide in the width direction of the magnetic tape, the section of the track TC in which the control signal of one predetermined sector is recorded and the data of one predetermined sector can be matched. Both ends of the recorded track TD section are made to coincide with each other in the width direction. The same relationship applies to the arrangement of the reproduction head. Of course, the positions of the control head and data head may be shifted by an integral multiple of the distance corresponding to one sector. Four blocks of data are recorded as one sector of the data track. At the beginning of each block, a data synchronization signal is recorded as shown by diagonal lines in FIG. One block of data inserted after the synchronization signal has one word of 16 bits.
PCM words W ₁ to W ₁₂ and one word are composed of 16-bit parity words P _O P _E , Q _O Q _E and a CRC code for error detection for these 16 words. PCM words W ₁ to _{W 12} belong to the same channel, and consecutive PCM words are divided into odd and even numbers,
Interleaving processing (arrangement rearrangement) and error correction encoding are performed for each. Parity words P _O and P _E are formed based on odd and even words before interleaving, and parity words Q _O and Q _E are formed based on odd and even words after interleaving. It was formed based on six words each.
Furthermore, within one block, the parity word is located in the center, and before interleaving, adjacent odd or even words, e.g.
W ₁ and W ₃ are separated by the maximum distance within one block. Such error correction encoding makes it easy to correct the reproduced data containing uncorrectable errors, such as interpolation using the average value of correct data located before and after the data. In other words, the possibility that two or more adjacent words in the PCM data series in the original order will become uncorrectable is minimized. The data synchronization signal inserted into each block of data track TD has a length of 16 bits, which is the same as one word, and includes a synchronization pattern indicating the beginning of one block, and a 3-bit block address [B ₂ B ₁ B ₀ 〕
and two flag bits [F _B1 F _B0 ]. The data synchronization signal is recorded using the same modulation method as the data, and the synchronization pattern is a pattern that does not appear in the data. In this example, a modulation method is used in which the minimum value (Tmin) of the magnetization reversal interval is 1.5T (where T is the time slot of 1 bit of the original data) and the maximum value (Tmax) is 4.5T. We are hiring. And the synchronization pattern is 1.5T, 4.5T,
It is said that the reversal interval is 4.5T and 0.5T sequentially. Note that there are two types of polarity of the synchronization pattern depending on whether the number of inversions in the block is odd or even. The most significant bit _B2 of the three bits of the block address is made to match the least significant bit _S0 of the sector address. Therefore, the block address [B ₂ B ₁ B ₀ ] is [000] [001]
...There are eight ways up to [111]. Furthermore, _the flag bits F _B1 and F _B0 are discrimination signals that _indicate whether or not the PCM data has been subjected to emphasis processing.
is set to [00], and when emphasized, it is set to [01]. A flag bit that is present after the [000] block address indicates whether the emphasis is on or off. Both this block address and flag bit are PCM
of each block along with word and parity data.
It is subject to error checking using a CRC code. As shown in Figure 2, one sector of the control track TC consists of a 4-bit synchronization signal, a 16-bit control word, a 28-bit sector address, and a 16-bit CRC code. . This control track
The configuration of TC is format A, format B,
It is the same for format C. The modulation method for control words, sector addresses, and CRC codes is the FM method. If the 1-bit cell of the FM system is T', the synchronization signal is
4 bits (4T'), a preamble period of 0.5T' is provided, and the previous sector is
The least significant bit of the CRC code is “0” or “1”
In either case, the synchronization pattern has a predetermined polarity as shown in the figure. Following the synchronization signal, a 16-bit control word _C0 to _C15 is provided. The four bits _C15 to _C12 determine the sampling frequency _fs , and the three bits _C11 to _C9 determine the format. In this example, all 9 bits from _C0 to _C8 are set to “0”.
I have to. However, if the data code structure, data modulation method, etc. are different, the
Bits C ₀ to C ₈ may also be used. A 28-bit ( _S0 to _S27 ) sector address is inserted after the control word. The sector address is set such that all bits are "0" and increases in an increasing direction for each sector, and indicates the absolute address of each sector. A CRC code (16 bits) for error detection is added to these control words and sector addresses. The format discrimination code (C ₁₁ C ₁₀ C ₉ ) in the control word is different depending on the format. When there are only three formats, as in this example, a 2-bit discrimination code is sufficient, but 3-bit is used in consideration of the greater variety. Figure 3 shows the relationship between data series, block addresses, and sector addresses. Figure 3A shows the case of format A, Figure B shows the case of format B, and Figure C shows the case of format C. It shows the case. This FIG. 3 shows the relationship for one channel, where n and m mean 0 and positive integers. In the case of format A, one channel is recorded as one data track, in the case of format B, one channel is recorded as two data tracks A and B, and in the case of format C, one channel is recorded as four data tracks. The data are recorded as data tracks A, B, C, and D. In one embodiment of the present invention, the discrimination bits C ₁₁ to _{C 9} in the control word are set according to the recording format.
By setting the recording format to a predetermined value and identifying the recording format from this discrimination bit at the time of reproduction, reproduction can be performed without any problem in any of the three recording formats. As an example, magnetic tape 1 is 1/4 inch wide and
The recording system and reproduction system used when the track pattern shown in the figure is formed will now be described. Depending on each format, each channel (CH)
PCM data is recorded.

[Table] Such track ratios are taken into consideration so that the configuration of data distribution or synthesis processing can be simplified even when the formats are different. Furthermore, the configuration of a recording system and a reproducing system in an embodiment of the present invention will be explained. In the recording system shown in FIG. 4, 2a to 2h are input terminals to which digital signals of channels CH ₁ to _{CH 8} are supplied, and these digital inputs are sent to an encoder 4a via input circuits 3a to 3h, respectively. ~4h.
In addition, a format designation signal, a sampling frequency _fs designation signal, and a timing signal are sent from the input terminals 5a, 5b, and 5c to the control encoder 6.
is supplied to The input circuit 3a has a configuration shown in FIG. The other input circuits 3b to 3h are also similar. A digital input of CH ₁ from the input terminal 2a is supplied to the shift register 13 and the synchronization separation circuit 14. As shown in Figure 6, the configuration of one word of digital input is 16-bit PCM data and _a0 to _a4.
This is a serial code consisting of 5-bit control bits and 3-bit synchronization signals _b0 to _b2 .
Whether PCM data is emphasized or not is determined by two bits in the control bits, for example a ₂ ,
Indicated by a ₃ . Other control bits are for prohibiting dubbing and for page flags.
Each word of the digital input supplied to the shift register 13 is taken into the latch circuit 15.
As a latch pulse for this latch circuit 15, a word timing signal from the synchronous separation circuit 14 is used. PCM data in one word appearing as the parallel output of the latch circuit 15 is supplied to a parallel-to-serial converter 16, and its serial output is supplied to the encoder 4a. Two bits a ₂ and a ₃ of the control bits appearing at the output of the latch circuit 15 are supplied to the encoder 4a. The shift pulse of the shift register 13 and the clock pulse of the parallel-to-serial converter 16 are generated by the clock generator 1 based on the synchronization signal.
7. Each of the encoders 4a to 4h is equipped with a data synchronization signal generator, an interleaver, an error correction encoding circuit, a block address generator, a flag bit addition circuit, and a CRC generator, and has a signal configuration as shown in FIG. Generate data. Similarly, the control encoder 6 includes a synchronization signal generator, a sector address generator, and a CRC generator, and generates a signal having the signal configuration shown in FIG. The outputs of encoders 4a to 4h are sent to demultiplexer 7.
is supplied to The demultiplexer 7 is for distributing the data of each channel to eight data tracks TD ₁ to TD ₈ as described above, and is controlled by the controller 8. A format designation signal is supplied to the controller 8, and A, B,
Data is distributed to eight tracks according to each format of C. The eight output series of the demultiplexer 7 are connected to the modulators 9a to 9h and the recording amplifier 10a.
~10h and recording heads HR ₁ ~ _{HR 8} respectively
added to. Further, the output series of the CTL encoder 6 is applied to the recording control head _HRC via the FM modulator 1 and the recording amplifier 12. The track pattern shown in FIG. 1 is recorded by these heads HR ₁ -HR ₈ and HR _C.
In FIG. 4, records regarding analog tracks TA ₁ and TA ₂ and time code track TT are omitted. Note that the reason why the format designation signal is given to the encoders 4a to 4h is to change the timing relationship in which the encoders 4a to 4h output data according to the format. In FIG. 7, HP ₁ to HP ₈ are reproduction heads that reproduce data tracks TD ₁ to TD ₈ , and HP _C
1 shows a reproduction control head for reproducing the control track TC, and the reproduction output of each head is supplied to demodulators 20a to 20h and 21 via reproduction amplifiers 18a to 18h and 19, respectively. The output of the demodulator 21 is supplied to a control decoder 23 after an error is detected by a CRC checker 22 . The control decoder 23 outputs a sampling frequency discrimination code from the control word.
It separates and extracts C ₁₂ to _{C 15} and format discrimination codes C ₉ to _{C 11} , and outputs a synchronization signal and a sector address, respectively. This synchronization signal is supplied to the capstan servo circuit as a comparison signal. Only control words and sector addresses for which the CRC checker 22 determines that there are no errors are considered to be legitimate data.
The format discrimination code from the CTL decoder 23 is supplied to the controller 24, and the controller 24 controls the demultiplexer 25 to operate according to the format. The multiplexer 25 has a configuration in which the input/output relationship of the demultiplexer 7 provided in the recording system is reversed, and converts the reproduced data from each data track appearing at the output of the demodulators 20a to 20h to the data of a predetermined number of channels. Convert to series. The output of multiplexer 25 is supplied to decoders 26a to 26h, respectively. The decoders 26a to 26h are CRC
It has a checker, deinterleaver, and error correction circuit. The reproduced PCM data of each channel is taken out from the decoders 26a to 26h, respectively, to output terminals 27a to 27h. A digital output signal appears at the output terminal 27a (~27h). When obtaining audio output instead of digital output, output terminal 27a (~2
7h) as shown in Figure 8.
A demodulator is connected. First, the reproduced digital output is supplied to the data separation circuit 28, where it is separated into PCM data, block addresses, and flag bits. The PCM data is supplied to the D/A converter 29, and its analog output is passed through the low-pass filter 30.
is returned to the audio signal via the line up 31 and output to the output terminal 32a (~32h).
It is taken out. The line amplifier 31 includes a de-emphasis circuit, and a switch circuit 33 for controlling on/off of the de-emphasis circuit is provided in association with the line amplifier 31. The block address and flag bits from the data separation circuit 28 are supplied to a switching pulse generator 34 to form switching pulses for controlling the switch circuit 33. If the flag bit [F _B1 F _B0 ] after the block address at address 0 where [B ₂ B ₁ B ₀ ] is [000] is [00], the switching pulse that turns off the emphasis is the switching pulse generator. 34, and when this flag bit [F _B1 F _B0 ] is [01], a switching pulse that turns on the emphasis is generated. In this way, de-emphasis is performed only when pre-emphasis is applied during recording. In the embodiment described above, the digital inputs applied to the input terminals 2a to 2h include a discrimination signal indicating whether emphasis is on or off. Differently from this, the present invention may be applied to a case where an audio signal is digitized via a PCM modulation section and supplied to the encoders 4a to 4h. FIG. 9 shows the configuration per channel in this case, in which audio signals are supplied to each of the input terminals 35a (-35h), and are supplied to the line-up 37 via the amplifier 36. The line amplifier 37 includes a pre-emphasis circuit, and an operation switch 38 for specifying ON/OFF of the pre-emphasis is provided in association with the line amplifier 37. The output of the line amplifier 37 is supplied to the A/D converter 40 via the low-pass filter 39, and the PCM data appearing at the output is sent to the encoder 4a (~
4h). A signal corresponding to the state of the operation switch 38 is supplied to a flag bit generator 41, and a flag bit as described above is generated according to whether the emphasis is on or off, and this flag bit is applied to the encoder 4a (-4h). As understood from the description of one embodiment above,
The present invention, which records a discrimination signal that may be rewritten for each channel on the same data track along with the PCM data of the corresponding channel, performs sync recording, punch-in, and punch-out editing independently for each channel. In this case, the possibility that the discrimination signal becomes incorrect can be greatly reduced. Unlike the present invention, if the discrimination signals of each channel are sequentially recorded on one control track, it is troublesome to rewrite the discrimination signals of the control track at the same time as rewriting the PCM data.
However, since only the discrimination signal of a specific channel is rewritten, there is a drawback that errors are likely to occur. According to the present invention, it is necessary to rewrite only the PCM data of a specific channel, and therefore there is an advantage that there is no need to rewrite the control track at all. In other words, each recording format parameter can be set independently for each channel (e.g. quantization, pre-emphasis, dubbing prohibition), or it cannot be set for each channel (e.g. number of channels, number of occupied tracks per channel, tape speed, sampling frequency) to determine whether to record data tracks TD ₁ to TD ₈ or control track TC,
When rewriting PCM data for each channel, parameters that can be set independently for each channel are recorded in the corresponding PCM data track, so even control track TC, which is different from data tracks TD ₁ to TD ₈ , can be recorded. On the other hand, parameters that cannot be set independently for each channel are recorded together in the control track TC, which has the advantage of reducing redundancy compared to recording for each channel. Note that when one channel of PCM data is divided into two or more data tracks and recorded, the discrimination signal may be recorded on some of the data tracks.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram of a track pattern in an embodiment of the present invention, Fig. 2 is a schematic diagram showing the structure of signals recorded as data tracks and control tracks, and Fig. 3 is a diagram of data series and block addresses. A schematic diagram showing the relationship with the sector address, Figure 4 is a block diagram showing the configuration of the recording system, Figures 5 and 6 are block diagrams of a part of the configuration, and a schematic diagram of the digital input signal configuration. , FIG. 7 is a block diagram showing the configuration of the reproducing system, FIG. 8 is a block diagram showing the configuration of the PCM demodulating section, and FIG. 9 is a block diagram of a part of the recording system in the case of analog input. 1 is a magnetic tape, 2a to 2h are digital input terminals, 3a to 3h are input circuits, 7 is a demultiplexer, 25 is a multiplexer, _TD1 to _TD8 are data tracks, TC is a control track,
HR ₁ to _{HR 8} are recording heads, _HRC is a recording control head, HP ₁ to _{HP 8} are playback heads, and _HPC is a playback control head.

Claims (1)

[Claims] 1. Record PCM data of multiple channels independently on multiple data tracks, and
Among the plurality of discrimination signals representing the respective types of the plurality of parameters of the recording format regarding the PCM data of the plurality of channels, different types for each channel correspond to the discrimination signals representing the types of parameters that can be set independently. channel's
The PCM data is recorded on a data track on which PCM data is recorded, and a discrimination signal representing a type of parameter that cannot be set for each channel is recorded on a control track different from the plurality of data tracks. multi channel
PCM data recording method.