JPS6070551A - Magnetic recording and reproducing system - Google Patents

Abstract

PURPOSE:To remove folding noise by switching a pass band for an input analog in accordance with a sampling frequency and also switching a pass band for a D/A converted analog signal. CONSTITUTION:A system control circuit 14 supplies a switching signal fixed in accordance with the sampling frequency by a sampling frequency specifying signal supplied from a key switch 15 to changeover switch circuits S1, S2 and buffer amplifiers 5, 6 as their gain switching signal. Even if the sampling frequency is changed, no folding noise is generated and the difference of losses among low pass filters (LPFs) 3-1-3-3 and among LPFs 4-1-4-3 is compensated. When receiving a control signal from a system control circuit 14 and an output from a master oscillator 16, a tape travelling reference signal generating circuit 18 supplies a tape travelling reference signal having frequency proportional to the sampling frequency to a magnetic head 40-18.

Description

[Detailed Description of the Invention] The light of the tree 5 is fixed, and the light is provided with 1.
The same (i
The present invention relates to a magnetic recording internal/l device that can be processed by an i-arch processing system.

To fix the 7N number, 1' was exchanged for 3 with 1.
CM Shinshi J is ll self-enhanced silver j'■/l 1 direct 1, self ff + A + l) child device p There are things, and there is no unity in the frequency.

T”C sampled at different frequencies and triturated
It would be extremely convenient if M-type bows could be processed using the same transmission system and signal processing system.

(Ll aspect of the invention) The present invention has been made in view of the above, and provides a magnetic recording system that processes 1-1 identical 1j' +3 processing systems and processes 1t) ++)ノ+: device I<l despite the difference in sampling frequency. !
l! However, the following is 1111'.

(The present invention consists of +1 of the symbol)'1-2'g (i'j') "J is converted into a PCM symbol and recorded on a magnetic recording medium, and the silver baride PCM code is detected. [5] In the magnetic recording device produced by analog technology, the number of holes recorded on the magnetic recording medium, the arrangement of the holes constituting the frame, and the number of holes per hole are unchanged. , when recording dU2, the area (1) of the passage of the human cuff is switched according to the rotation speed of the user, and the traveling speed of the magnetic recording medium and (gr3 processing lX
In addition to controlling the double processing speed of the 1i system, it also stores sampling frequency information corresponding to the sampling frequency and the running speed of the magnetic recording medium in the magnetic recording medium, and stores information such as The running speed of the magnetic recording medium and the processing speed of the signal processing system are set to 1lill 1i according to the sampling frequency information.
+l and l+/A conversion analog (l'i"
It is characterized in that the passage (()) remainder of ; is switched.

The present invention will be explained by way of examples.

111; 4(a), (b) and (C) are unissued f
It is a block diagram showing the configuration of -Wk4H of lJ, and the first
Figure (a) shows the recording system, and Figures 1 (b) and (c) show the 11
The reproduction system is shown in each case, and the magnetic tape drive system is the same, so only the reproduction system is shown.

In one embodiment of the present invention, a case will be described using as an example a case where a two-channel analog audio signal is converted into PCM code and recorded + If generated.

First, the recording system will be explained. Input terminal INL, INR
The left and right channel analog audio signals supplied to the left and right channels are respectively supplied to buffer amplifiers 1 and 2, and the output of the buffer amplifier 1 is supplied to low-pass filters 3-1 to 3-3 for preventing aliasing noise. It is. The low-pass filters 3-1 to 3-3 have sampling frequencies fsl, fs2, fs3 (for example, 48
The passband characteristics are set correspondingly to 1kHz, 44kHz, IkHz, 32kHz). Similarly, the output of the buffer amplifier 2 is similarly filtered through low-pass filters 4-1 to 4-4-.
3 (both are 4 combinations. Low pass filter 4 = 1 to 4-
3 has the same configuration as the low-pass filters 3-1 to 3-3.

The outputs of the low-pass filters 3-1 to 3-3 are supplied to a switch circuit S1 that is switched by a switching signal corresponding to the sampling frequency, and the low-pass filters 3-1, 3-2, . 3-3 is selected and supplied to a variable gain buffer amplifier 5, and the output of the eight-flip amplifier 5 is supplied to a sample-and-hold circuit 7. Similarly, low-pass filter 4-1~
The output of 4-3 is supplied to a changeover switch circuit S2 which is switched by a changeover signal corresponding to the sampling frequency.
Low pass filter 4-1 corresponding to the sampling frequency
．． One of the outputs of 4-2 and 4-3 is selected and supplied to a variable gain buffer amplifier 6, and the output of the buffer amplifier 6 is supplied to a sample and hold circuit 8.

The gains of the eight-foot amplifiers 5 and 6 are switched and controlled in accordance with the sampling frequency.

The outputs of the sample and hold circuits 7.8 are each separately supplied to an A/D converter 9.10. The outputs of the A/D converters 9 and 10 are supplied to the circuit 13 and stored therein. The data written t0 in the tα circuit 13 is sent to the P check word generator 11 and the Q check word generator 12 in a predetermined order.
The generated P test word and Q test word are supplied to the storage circuit 13 and stored therein. The PCM codes are then interleaved by changing the reading order.

Here, an address generation circuit for transferring data from the storage circuit 13 to the P check word generator 11 and the Q check word generator 12, and an address generating circuit for transferring data from the P check word generator 11 and the Q check word generator 12 to the storage circuit 13 are used. The address generation circuit and the write address generation circuit and read address generation circuit of the memory circuit 13 are omitted.

On the other hand, 19 is an identification code as sampling frequency information corresponding to the sampling frequency received by receiving a control signal output from the system control circuit 14 corresponding to the sampling frequency, for example, fsI = 48 kl (for z, "01 A sampling frequency discrimination gradient generating circuit that outputs a discrimination code of °'10'' for fs2 = 44.1)1z and °'11°' for fs3 = 32 kHz, 20 is the system control circuit 14
In response to the control signal output from
This sub-code generating circuit outputs a code corresponding to a music number corresponding to a CM code, a code indicating the number of bits of a PCM code, and a code corresponding to time, etc.

The output of the sampling frequency identification code generation circuit 19 is error correction 11: error correction 1 which generates a code and adds it to the identification code.
The output of the error correction code generation circuit 21 and the output of the sub-code generation circuit 20 are supplied to the selector 22, temporally selected, and then supplied to the storage circuit 13 for storage.

The data read from the storage circuit 13 is supplied to a demultiplexer 25 and distributed to the recording sections 30-1 to 30-17. In this embodiment, the case where the magnetic head has 18 tracks is shown, and the recording magnetic head has 40 tracks.
1 to 40-18, and the reproducing magnetic head to 50-1 to 5.
Magnetic hands with the same suffix are marked 0-18 and correspond.

The interleaved PCM codes output from the demultiplexer 25 are sent to recording units 30-1 to 30-12, the P check words are sent to recording units 30-13 and 30-14, and the Q check words are sent to recording units 30-15. 30-1ft, the sampling frequency identification code and sub-code are recorded in the recording unit 30-1ft.
17 respectively.

The recording unit 30-1 includes a CRC code generation circuit 31-1 that receives the output from the multiplexer 25 and generates a CRC code;
It includes a frame synchronization code generation circuit 32-1 that generates a frame synchronization code, a selector 33-1, a modulator 34-1 that performs modulation for recording, and a recording amplifier 35-1. 1, the output of the multiplexer 25, and the output of the CRC code generation circuit 31-1 are supplied to the selector 33-1 and sequentially outputted to the modulator 34.
-1 and modulate it. The output of the modulator 34-1 is supplied to the recording amplifier 35-1, and the output of the amplifier 34-1 is supplied to the magnetic field.

40-1. Recording units 30-2 to 30-1
7 has the same configuration as the recording unit 30-1, and the recording unit 30
-2 to 30-17 outputs are magnetically different!・
40-2 to 40-17.

Therefore, the signal modulated with the synchronization code, the interleaved PCM code, and the CRC code is the magnetic Hent 40-1.
~40-12, and a signal modulated with the synchronization code, P check word and CRC code is sent to the magnetic head 4.0-13.
, 40-14, and a signal modulated with the synchronization phrase, the Q check word, and the CRC code is sent to the magnetic head 40-15.
, 40. -18, and a signal modulated with a synchronization code, a sampling frequency identification code, a sub code, and a CRC code is supplied to the magnetic head 40-1'7.

The signals supplied to the magnetic hand 40-18 will be described below.

The system control circuit 14 uses the sampling frequency designation signal supplied from the key switch 15 to send a switching signal determined corresponding to the sampling frequency to the switching switch circuit S.
1, S2 and as a gain switching signal. 5.6. The system control circuit 14 transmits a control signal determined corresponding to the sampling frequency to a mask oscillator 16.
．． timing pulse generator 17, tape running reference signal generator 18° sampling frequency identification code generation circuit 19,
Speed reference voltage generator 1 via a tape running reference signal generator 102 and a play/record changeover switch 28-1, which will be described later.
53.

Further, the system control circuit 14 supplies a sub-code generation signal based on the sub-code designation signal supplied from the key switch 15.

The mask oscillator 16 that receives the control signal oscillates at a frequency corresponding to the sampling frequency. The timing pulse generator 17 receives the output of the master oscillator 16 and the control signal from the system control circuit 14, and outputs an output at a designated sampling frequency fsl, fs2 or fs3 to the sample and hold circuits 7 and 8. A predetermined timing pulse corresponding to the sampling frequency is sent to the A/D converter 9 and the lO,P test word generation circuit 11.
and the Q check word generation circuit 12, the write address generator and read address generator of the memory circuit 13, the multiplexer 25, and the CRC code generation circuits 31-1 to 31.
-17. Frame synchronization code generation circuit 32-1 to 32-1
7. Selectors 33-1 to 33-17, modulators 34-1 to
34-17 sampling frequency identification code generation circuit 19,
Sub code generation circuit 20. error correction code generation circuit 21;
The signal is supplied to the selector 22.

The tape running reference signal generation circuit 18 receives the control signal from the system 1, the control circuit 14, and the output of the mask oscillator 16, and outputs a tape running reference signal with a frequency proportional to the sampling frequency. 26
supply to. The output of the recording amplifier 26 is sent to the magnetic field 40.
-18.

23 and 24 are non-transmission focus control circuits that set the non-transmission focus to O. For example, when the outputs of A/D converters 9 and 10 are 16 bits, when transmitting 14 hints, The configuration is such that the lower 2 bits of the outputs of A/Df converters 9 and 10 are deleted, and an O pad is inserted at the bits corresponding to the lower 2 bits of the output of A/Df converters 9 and 10. It is controlled by the output of the system control circuit 14 which receives the focus number per word instruction signal from 15.

Next, the running system of the magnetic tape 46 will be explained (first
(See figure (b)). A tape running reference signal generating circuit 102 which generates a tape running reference signal by receiving a control signal from the system control circuit 14 and an oscillation output of the mask oscillator 16 supplies the tape running reference signal to a comparator circuit 41, and the output of the comparator circuit 41 is sent to a servo amplifier 42. It is supplied to The output of the servo amplifier 42 is supplied to a drive circuit 43, the output of the drive circuit 43 is supplied to a capstan motor 44, and the output of the drive circuit 43 drives the capstan motor 44. 45 is a capstan. The capstan motor 44 and the pulse generator 154 are mechanically connected, and the output of the pulse generator 154 is connected to the playback/recording switch 28-.
2 to the comparison circuit 41. In addition, the output of the pulse generator 154 is connected to the playback/recording switch 28-
2 to a frequency-to-voltage converter 155;
Frequency 'lli: The output voltage of the pressure transducer 155 and the speed are referenced. A servo amplifier 42 controls a capstan motor 44 so that the phases match.

In addition, +1) Note: The recording changeover switch is the above-mentioned if
The raw recording off +) switches 28-1 and 28-2 are omitted.

Finally, I will explain +IT production system. magnetic head 50-
The signal detected at 18 is a tape running reference signal with a frequency proportional to the sampling frequency and is supplied to amplifier 100. The output of the amplifier 100 is supplied to a raw signal reproducing circuit 101 when the tape is running.
The output of lf raw enclosure lot is 111 raw record switch 28-
2 to the comparison circuit 41. On the other hand, an output from a control signal generation circuit 115 (to be described later) is supplied to the tape running reference generation circuit 102 in place of the output from the system control circuit 14, and an output from the control signal generation circuit 115 is supplied to the old record changeover switch 28. Speed reference 1 via -1! It is supplied to the q' pressure generator 153.

103 is a sampling frequency identification code and sub♀J?
? It is a demodulator. The signal detected by the magnet '50-17 is supplied to the amplifier 104. Magnetic Hent 50-
The signal detected in step 17 includes the sampling frequency identification code, sub-code, etc. The output of the amplifier 104 is supplied to a waveform equalization circuit 105, and the output of the waveform equalization circuit 105 is supplied to a waveform shaping circuit 106. The output of the waveform shaping circuit 106 is supplied to the bi/so(j1 detection circuit 107, frame 1, synchronization detection circuit 108, and demodulator 109).

FIG. 2 shows the waveform equalization circuit 105 and waveform shaping circuit 106.
- Shows examples. The waveform equalization circuit 105 changes the frequency characteristics while maintaining the linear phase according to the content of the 4T-i signal from the control signal generation circuit 115, that is, the sampling frequency identification code, and changes the frequency within the magnetic tape signal transmission band to 'l1Ill'. Equalizer amplifier 1
05-1 and the content of the sampling frequency identification code to set the delay circuit's 8-field time and output the equalizer amplifier 10.
The pulse width of the output of 5-1 is sandwiched between the centers.

It consists of a pulse slimming circuit 105-2 and an integrating circuit 105-3 that integrates the output of the pulse slimming circuit 105-2. On the other hand, the 1 waveform shaping circuit 106 is used for DC reproduction from the output signal of the waveform equalization circuit 105.
It consists of a current reproduction circuit 106-1 and a voltage comparison circuit 106-2 that compares the output of the waveform equalization circuit 105 and the output of the DC reproduction circuit 106-1. The synchronization detection circuit 107 receives the output of the waveform shaping circuit 106, and when an edge portion of the output occurs, the frequency divider 107-
The knee of the signal made from the output of 4.

an edge extraction circuit 107-5 for extracting the edge portion, and an edge extraction circuit 107-5 for the output edge of the waveform shaping circuit 106;
A phase comparator circuit 107-2 that compares the phase with the edge of the signal produced from the output of the frequency divider 107-4 extracted from the phase comparator circuit 107-1, and an error amplifier 107-2 that amplifies the I7 phase comparison output of the phase comparator circuit 107-1. , the free-running frequency is controlled by the content of the sampling frequency detection code, and the error amplifier 107-
Voltage controlled oscillator (V
It is composed of a PLL circuit consisting of a frequency dividing circuit 107-4 that divides the output of the CO) 107-3 and the output of the VCO 107-3.

The output of the demodulator 109 and the output of the bit synchronization detection circuit 107 are supplied to a sampling frequency identification code detection circuit 110, which detects the sampling frequency identification code.

The output of the identification code detection circuit 110 is sent to the error correction IF circuit 11.
2, and performs error correction 11- on the sampling frequency detection code. The output of the error correction circuit 112 is sent to a code determination circuit 11 that determines the sampling frequency identification code.
3, and the output of the sign discrimination circuit 113 indicates that the sign corresponding to the sampling frequency detection sign is at least once every 1-
It is supplied to a detection number counter 114 that detects whether the sampling frequency detection code has been output, and to a control/roll signal generation circuit 115 that detects whether the signal has been output N times or more and generates an output corresponding to the content of the sampling frequency detection code. . The output of the control signal generation circuit 115 is the waveform equalization circuit 105.12.
7-1 to 127-16, hit synchronization detection circuit 107.1
29-1 to 129=j6. Control circuit 116, master oscillation iiJ+8, decoder 148 (described later), D/A converter 1
42.143"O'" is supplied to the set 151.152 and the timing pulse generation circuit 118. However, D/
A converters 142, 143 and "0'" set 151.
There is also a method in which the control signal 152 receives a control signal from the JllIn circuit 124 on the 11th day.

FIG. 4 shows the court': ill separate circuit 113. Detection number counter 11.4 and control signal generation circuit 115
The blow diagram is shown below.

The code determination circuit 113 converts the output from the error correction circuit 112 into parallel data by a serial/parallel converter 113-1, and from the output of the serial/parallel converter 113-1, the sampling frequencies fcl, fc2,
It consists of data detection circuits 113-2 to 113-4 that respectively determine sampling frequency identification codes corresponding to fc3. Data detection circuits 113-2 to 113-4
are the crystal type 0” side of the sampling frequency identification codes “°01°”, “10”, and °“11” respectively.
On the side, sampling frequency identification code ° “01”, '“1
0" and "I l " are respectively output to the terminal GI2 side.

The detection number counter 114 is connected to the data detection circuit 113-2.
l l 3-3.113-4 respective terminal Gll
a counter 114 that counts the output of the side at least once;
-1, 114-2, 114-3, upon receiving data outputted from the control circuit 116 that forcefully decreases the tape speed, the counters 114-1 to 114-3 detect the ψf deviation.
The outputs of the counters 114-1 to 114-3, each consisting of a 1" fI-return detection circuit 114-4, are supplied to the controller 116.

The control signal generation circuit 115 is the data detection circuit 11
3-2.113-3.113-4 each end A G1
N-ary counter 115-1 to 1 that counts the output on the 1 side
15-3, Nil counters 115-1 to 115-3 output when N is counted, FvJ*Swin fr"1 path 115-5 to 115-7, cut t+ switch circuit 115-5 A latch circuit 115-8 is provided for latching the output from the terminal G12 side of the data detection circuits 113-2 to 113-4 outputted through the control circuits 115-115.
OR circuits 115-9 to 1 that receive empty reproduction instruction pulses
1511.115-22, OR circuit 115
-9 is further supplied with the outputs of counters 115-2 and 115-3, and the OR circuit 115-10 is further supplied with the outputs of counters 115', l and 115-3. The outputs of counters 115-1 and 115-2 are further supplied to the circuit 115-II, and the outputs of the OR circuits 115-9 to 115-11 are individually selected by the counters 115-1 to 115-3. ...resets counters that are not generating output by supplying a current signal. Counters 115-1 to 115-
The output of 3 is supplied to OR circuit 115-12, and the output of OR circuit 1
The output of 15-12 is supplied to delay circuits 115-13 to 116, and is also supplied to latch circuit 115-8 as a latch pulse, and is also supplied to switch circuits 115-14 and 115-11.
5-15 is a switching signal and 1. Launch circuit 115
-8 is output as the output of the control signal generation circuit 115 via the switch circuit 115-14. Data for forcibly instructing the tape speed outputted from the control circuit 116 is supplied to a pattern detection circuit 115-18, which is installed to detect a pattern for example fs3 = 32 kHz, and detect the pattern. The output of the detection circuit 115-Iff is as follows:
A counter l l 5-17 is provided to provide a two count output to controller 116 and auto-stop indicator circuit 117. The rM raw digit instruction pulse from the control circuit 116 is differentiated by the differentiating circuit 115-18, and the counter 115-
Reset 17.

The error detection output from the error correction circuit 112 is sent to the low flip-flop circuit 11 via the OR circuit 115-19.
5-20 as a clock pulse, and the output of the low flip circuit 115-20 is supplied to an M-ary counter 115-21 which inputs the number of errors. The output of counter 11.5-21 that counts the same number of errors is OR circuit 1
15-22, the output of the OR circuit 115-22 is differentiated by a differentiating circuit 115-23, and the launch circuit 115-8 is reset by this differentiated result.

On the other hand, the frame synchronization output signal detected by the frame synchronization detection circuit 10B is reset to the low flip-flop circuit 115-20, and the signal generated for each frame is reset to the low flip-flop circuit 115-20. is reset for each frame.The signal generated for each frame is reset at the same time as the frame synchronization method.
The output of the AND circuit 115-25 is supplied to the differential circuit 1.
Differentiate by 15-25 and use the differential output as counter 115-21
is reset, and the output of the counter 115-21 is reset for each frame. On the other hand, the low flip-flop circuit 1
The output obtained by inverting the output of 15-20 is an AND circuit 115-
24 and is generated for each array when an error is detected.
Prohibits 11- from resetting 21.

The output of the decoder 109, the output of the same 101 detection circuit 107 (hereinafter referred to as the F frame period signal) and the output of the frame period detection circuit 108 (hereinafter referred to as the F frame period signal) are sent to the sub-code decoder 119 and the CRC The signal is supplied to a detection circuit 120, which detects the sub-code from the output of the demodulator 109, and supplies the sub-queue to a sub-queue register 122. The CRC detection circuit 120 detects an error in the sub-code, and when an error is detected, supplies a pointer indicating that F'1 is present to the CRC pointer register 121, and the CRC pointer register 121 stores the pointer as a CRC pointer. 12
The output of 1 is supplied to the sub-waiting register 122, and if there is no pointer in the CRC pointer register, the sub-code register sends the error-checked sub-code to the control circuit 124 and display circuit 123, and if the pointer is 1, the pointer becomes 1'. The control circuit 124 outputs sub-codes for which f errors were not detected.
and sends it to the display circuit 123. Sub-sign register 122
The output of is supplied to a display circuit 123 and a control circuit 124, the display circuit 123 displays the contents of the sub-code set in the sub-code register 122, and the control circuit 1.24 displays the contents of the sub-code set in the sub-code register 122. The output of the control circuit 124 is used to select, for example, the song number l.

The timing pulse generation circuit 111 also generates a bit synchronization signal detected by the bit synchronization detection circuit 107 and a frame reversal signal detected by the frame synchronization detection circuit 108.
The frame brightness detection circuit 108 and the demodulator 109 .
Identification code detection circuit l1l):, error correction circuit 112,
Code discrimination circuit 113, control signal generation circuit 11
A timing pulse corresponding to the output of the bit synchronization detection circuit 107 is supplied to each of the bit synchronization detection circuits 107 and 5.

Further, the outputs detected by the magnetic heads 50-1 to 50-is are separately supplied to the de-f generation sections 125-1 to 125-18, respectively.

The reproducing unit 125-16 includes an amplifier 126-18 and an amplifier 126-I for amplifying the detection output from the magnetic head 50-113.
A waveform equalization circuit 127-16 that equalizes the output of S, and a waveform circuit 128- that shapes the output of the waveform equalization circuit 127-18.
18. A bit synchronization detection circuit 129-18 and a frame synchronization detection circuit 130- detect a hint synchronization signal and a frame synchronization signal from the output of the waveform shaping circuit 128-16, respectively.
18, a demodulator 131-18 that demodulates the output of the waveform shaping circuit 128-18, a bit synchronization signal detected by the bit synchronization detection circuit 129-IB, and a frame synchronization detected by the frame synchronization signal detection circuit 130-18 (from Timing pulse generation circuit 132 that generates timing pulses
-18, which are similar to the code demodulator 103. The output of the waveform shaping circuit 128-16 is supplied to the CRC detection circuit 133-IS. On the other hand, demodulator 13
The demodulated output of 1-IS is supplied to the register 134-18, and the register 104-16 is connected to the CRC detection circuit 133.
-18, the error-checked data is temporarily stored, and the pointer output from the CRC detection circuit 133-18 is stored as a pair with the data, and the data and pointer are sent to the storage circuit 135-18. The output of the register 134-16 is sent to the memory circuit 136-18, and the write address generation circuit 13
The data is stored sequentially at the addresses added by step 6-16. The reproducing unit 125-18 is also provided with a write priority instructing circuit that receives the address generated by the old address generating circuit 136-18 and controls a read address generating circuit 138 (described later) to give priority to writing to the storage circuit 136-18. There is. Timing pulse generation circuit 13
2-18, a frame synchronization detection circuit 130-18, a demodulator 131-16. CRC detection circuit 133-18. Registers 134'-116, write address generation circuit 136
-16 respectively, hit synchronization detection circuit 1'29-16
A timing pulse corresponding to the frequency of the bit periodic signal detected in is supplied.

The playback units 125-1 to 125-15 are the playback unit 125-16.
The playback units 12-1 to t25-
12 receives the detection outputs of the scratchy magnetic heads 50-1 to 50-12, and sends the PC to memory circuits 135-1 to 135-12.
M code is stored and reproduced by parts 125-13 to 125-18.
receives the detection outputs of the magnetic heads 5o-13 to 50-16, and stores P test word data and Q test word data in storage circuits 135-13 to 135-1fli, respectively.

A read instruction signal generation circuit 139 that generates a data read instruction signal and a din-leave control signal supplies the data read instruction signal to a read address generation circuit 138, and the read address generation circuit 138 reads data at a cycle corresponding to the sampling frequency. The address is supplied to the memory circuits 135-1 to 135-18.

The data read from the memory circuits 135-1 to 135-1[i is supplied to the deinterleaving circuit 140, and the data written to the deinterleaving circuit 140 is used for error correction 1[.
The error correction 11 is taken into the circuit 156 in a predetermined order of 11 nights.
− is received, deinterleaved by the dinning circuit 140, and supplied to the error correction circuit 141.

On the other hand, the timing pulse generator 118 receives the output of the control signal generation circuit 115 and the output of the mask oscillator 16, and generates a read instruction address generation circuit 138, a read instruction signal generation circuit 139, and a deinterleave circuit 14.
0, error correction circuit 156, error correction circuit 141, D
/A converter 142.143, thousand clincher 144.14
5, a timing pulse corresponding to the sampling frequency is outputted.

Error correction i [When the error cannot be corrected completely in the circuit 156, the error correction circuit 141 corrects it, and when the correction 11- is not required, the correction IF is not performed, and The PCM code is supplied to the D/A converter 142, and the PCM code for the right audio is supplied to the D/A converter 142.
/A converter 143. The output of the D/'A converter 142 is supplied to low-pass filters 146-1 to 146-3 via a deglitcher], 44, and
,/The output of the A converter 143 is supplied to low-pass filters 1.47-1 to 147-3 via a degrin filter 145. Here, low pass filter 14.6-1~1
46-3. 147-1 to 147-3 are frequency characteristic settings corresponding to the sampling frequency; 7.

The output of the control (roll signal generation circuit 115) is output from the decoder 1.
48, and the output of the decoder 148 is supplied to a switch circuit S'l that selects one of the outputs of the low-pass filters 146-1 to 146-3 and the output of the low-pass filters 147-1 to 147-3. is supplied to a selector switch circuit S'2 for selecting one of the low-pass filters 146-] to
Select the output of 146-3 and apply the low-pass filter 147-
Select output from 1 to 147-3.

! , IJ change switch circuits S', S2 are supplied to gain ++ (variable Humph γ amplifiers 149 and 150, respectively) whose gains are changed by the code output of the decoder 148 in accordance with the sampling frequency identification code, and are amplified. Moreover, it is supplied to the output terminals r-OL and OR of the left and right channels.

Further, the D/A converters 142 and 143 receive the output of the control signal generation circuit l15, and when the output of the control signal generation circuit 115 corresponds to the sampling frequency of 32kHz, the PCM? 0″ for the bottom 2 hints of i match
The output of the non-transmission bit setter is supplied.

On the other hand, the non-transmission focus setter 151.152 is Conotrol 4'N'! ; When the output of the control signal generating circuit 115 in response to the output of the generating circuit 115 is an output corresponding to a sampling frequency of 32 kHz, when error correction is performed in the error correction circuit 11-circuit 156, the PCM code signal Ri
This is a summer setting device to set the 2nd focus to "O".

(Operation of the invention) In one embodiment of the present invention configured as shown in 1- below, 1
PCM0 with the number of words in the frame Nu as 87-bits:
The operation will be explained assuming that the combined track is <12 tongs as described above.

The recording system will now be explained.

During recording, the key switch 15 instructs the sampling frequency and sub-code, and the system control circuit 14! , lJ family switch circuit 51.
A switching signal corresponding to the sampling frequency is output to S2, and the switching circuit St.

S2 is switched depending on the sampling frequency.

Therefore, even if the sampling frequency is changed, aliasing noise will not occur. The system control circuit 14 also outputs a gain threshold corresponding to the sampling frequency to the buffer amplifiers 5 and 6, and switches Eq+t of the Henff amplifier 5.6 in accordance with the sampling frequency. Therefore, the low-pass filter 3-1.3-2.3
The difference in loss between -3! , r: I-pass filter 4-1.
Difference in loss between 4-2.4-3 1/I! will be compensated.

- a mask oscillator 1 which receives a control signal determined corresponding to the sampling frequency from the control circuit 14;
6 generates an output with a frequency corresponding to the sampling frequency, and receives this oscillation output and a control signal from the system control circuit 14. Generates a tape running reference signal.

This tape running reference signal is amplified by an amplifier 26 and then supplied to a magnetic head 40-18 to be recorded on the magnetic tape.

Also, when recording, playback/recording switch 28-1
．． 28-2 has been switched to the contact position shown in FIG. 1(b). Control +, j'S from system control circuit 14:
The tape reference circuit 102 receives the oscillation output from the master oscillator 16 and outputs a frequency corresponding to the sampling frequency, and receives the control signal from the system control circuit 14 to generate a speed reference voltage. vessel 15
3 outputs a speed reference voltage corresponding to the sampling frequency. Further, the output of the pulse generator 154 is supplied to the comparator circuit 41 via the reproducing/recording switch 28-2 and also to the frequency-voltage converter 155.

At the beginning of the night, the magnetic tape 46 is not running, so there is no output voltage from one of the comparator circuits 41 and the frequency-voltage converter 155, and the output from the servo amplifier 42 is at its maximum.
The gear stan motor 44 is driven at maximum torque, and the magnetic tape 46 is caused to run. From this first run, the pulse generator 154 generates an output pulse, and the pulse -t!
The output of the pulse generator 154 is supplied to a comparison circuit 41 and compared in phase with the output of the tape running reference signal generation circuit 102, and the output frequency of the pulse generator 154 is converted to voltage by a frequency-voltage converter 155 and supplied to the servo amplifier 42. The output of the speed reference voltage generator 153 (difference with Ichikawa) and the output of the phase comparator 41 are added and amplified by the servo amplifier 42, and the servo motor 44 operates magnetically at a running speed corresponding to the sampling frequency. Tape 46 will now be driven.

The left and right channel analog audio signals supplied to the input terminals INL and INR are amplified by the buffer amplifier 1.2 and low-pass filters 3-1 to 3-3.4-1.
~4-3, and the high range is limited in accordance with the sampling frequency. Low pass filter 3-1 to 3-3
, and the outputs of the low-pass filters 4-1 to 4-3, one output is selected by the changeover switch circuits S1 and S2 in accordance with the sampling frequency, and amplified by the buffer amplifier 7.8. In this case the buffer amplifier 7
．． The gain of 8 corresponds to the sampling frequency, and the difference in loss between the low pass filters 3-1 to 3-3 and the difference in loss of 1 to 4 between the low pass filters 4-1 to 4-3 are compensated for. Ru.

The output of the buffer amplifier 56 is supplied to a sample-and-hold circuit 7.8, where it is sampled and held with a sampling pulse of a frequency designated by the key switch 15. The outputs of the sample-and-hold circuits 7.8 are converted by the A/D converters 9 and 10 separately for PCMf''F and stored in the memory circuit 13.Memory circuit 1
The PCM code stored in 3 is a predetermined 11" (P check word generation circuit 11, Q check word generation circuit 12 according to the order).
The P test word and the Q test word are loaded into the memory circuit 13 and stored in the storage circuit 13. When the number of non-transmission bits of PCM code is specified by Kisui-Sochi 15, it is non-transmission and 71."o" control circuit 23,? 4 receives an instruction of the number of hints not to be transmitted from the control circuit 14 and controls the non-transmission focus to "o" in accordance with the instruction. The control circuits 23, 24 respectively generate the P check word and '1.' of the Q check word. The PCM code stored in the memory circuit 13 is incremented. The P test word and the Q test word read from the storage circuit 13 are supplied to the T multiplexer 25, and supplied to the register #j and units 3o-1 to 30-12. Sane, records KB30-13 and U 30-14 records M30-15 and 3O-II
(Supplied to.

On the other hand, the sibling frequency detection code generator 19 outputs an identification code corresponding to the sampling frequency in response to a control signal corresponding to the sampling frequency specified by the key switch 15 from the system control circuit 14, and outputs an identification code corresponding to the sampling frequency. is supplied to an error correction 11' and a code generation circuit 21, an error correction code is added thereto, and the signal is supplied to a selector 22. Further, the sub-code generation circuit 20 is connected to the system control circuit 1.
4 receives a control signal designated by a key switch 15 to generate a sub-code, and the sub-signal is supplied to a selector 22. The identification code and sub-code to which the error correction code is added and supplied to the selector 22 are selected by the selector 22 and stored in the storage circuit 13, and are read out from the storage circuit 13. The subcode is supplied to a demultiplexer 25, and the demultiplexer 25 supplies it to a recording section 30-17.

A frame synchronization code and a CRC code are added to the codes supplied to the recording units 3o-1 to 30-17, and predetermined modulation is performed by modulators 34-1 to 34-17. In Table 1, 2W is the PCM code for the left channel analog signal, W is the PCM code for the right channel analog signal, P is the P test word, Q is the Q test word, B is the sampling frequency identification code, S has a sub-code of 71 mi.

On the other hand, the timing pulse generator 17 receives the control signal from the system control circuit 14 and the oscillation output of the mask oscillator 16 and generates various timing pulses corresponding to the sampling frequency. ．． P check word generation circuit 11. Q check word generation circuit 12, Jq write address generation circuit and read address generation circuit of memory circuit 13, multiplexer 25, CRC code generation circuits 31-1 to 31-17
.

Frame synchronization code generation circuits 32-1 to 32-17. Selectors 33-1 to 33-17. Modulators 34-1 to 34-1
7. Sampling frequency identification code generation circuit 19, sub-waiting generation circuit 20, error correction code generation circuit 21. Since the signal is supplied to the selector 22 and the sampler pulse is also supplied to the sample-and-hold circuits 7 and 8, signal processing is performed at a signal processing speed according to the designated sampling frequency.

Here, even if the designation of the sampling frequency by the key switch 15 is changed, the magnetic tape 46 is driven at a running speed corresponding to the newly designated sampling frequency. Also, low-pass filters 3-1 to 3-4,
Low pass filters 4-1 to 4-4, buffer amplifier 5.
The gain of 6 is switched in accordance with the newly designated sampling frequency, and the sample-and-hold circuit 7.8 samples and holds the output of the buffer amplifier 5.6 using the sampling pulse of the newly designated frequency. Furthermore, the magnetic head 40-18 provides a tape running base proportional to the newly specified sampling frequency.
The signal 15i is recorded on the tape 46. On the other hand, the A/D converter 9 and the lO,P test word generation circuit 11. Q check word generation circuit 12, write address generation circuit and read address generation circuit of recording circuit 13, multiplexer 25, CRC code generation circuits 31-1 to 31-1? ,
Frame synchronization code generation circuits 31-1 to 32-7, selectors 33-1 to 33-17. Modulators 34-1 to 34-17
, the sampling frequency identification code generation 1n path 19, the sub-code generation circuit 21, and the selector 22 are operated by various timing pulses corresponding to the newly designated sampling frequency output from the timing pulse generator 17. Since there is no change in the recording format associated with the first table number, and there is also no change in the minimum recording wavelength, there is no problem with recording and reproduction.

In addition, in the case of the record shown in Table 1], when the sampling frequency is fsl = 48 kHz, the PCM code for 1 m5ec is stored in the l frame, and fs
When 2=44.1kHz, 1 frame L is 160/1
The pCM code for 47m5ec is fs3 = 32kHz
2 (7), one frame has 1. ．． PC for 5m5ec
11g of M codes will be stored.

Next, the operation of the ll generation system will be explained.

When switching to playback, that is, when IIf play is instructed by the key switch 15, a playback instruction is given to the system control circuit 14. Playback recording switch, 2chi 28-1~
28-3 is 1) switched from the playback example, that is, the contact position shown in FIG. 1(b), by the output of the system 1 and control circuit 14 in synchronization with the live instruction. On the other hand, key switch 15
The reproduction instruction output is supplied to the control circuit 116 to issue a previous digit instruction. At this point, the magnetic tape 46 has not yet been driven.

From the control circuit 116 to which the 111 raw instruction was given, a reproduction instruction pulse is sent to OR circuits 115-9 to 115-11.115.
-22, and at the same time the identification code corresponding to the sampling 171 wave number 44.1kHz is displayed for a predetermined period (tl).
, is forcibly supplied to the switch circuit 115-15. The former reproduction instruction pulse causes counters 115-1 to 115 to
-3.115-17. The latch circuit 115-8 is
The rising detection circuit 114-4 of the latter identification code
The detection output of the counter 114-1-
114,3 is reset (step a of FIG. 5).

Further, the latter identification code is outputted as an output of the control signal generation circuit 115 via the switch circuit 115-15.

This output is supplied to the tape running reference signal generation circuit 102 in place of the control signal of the system control circuit 14, and is also supplied to the speed reference voltage generator 153 using the reproduction/recording changeover switch 28-
1, and is then supplied to the mask oscillator 16 in place of the control signal of the system control circuit 14. As a result, the mask oscillator 16 oscillates at a frequency corresponding to the sampling frequency corresponding to the sampling frequency identification code. The tape running reference signal generation circuit 102 receives the output of the control signal generation circuit 115 and the oscillation output of the mask oscillator 16, and generates an output with a frequency corresponding to the sampling frequency, and receives the output of the control signal generation circuit 115 and generates a speed reference signal. Generator 153 generates a voltage output corresponding to the sampling frequency. However, the capstan motor 44 is stopped and the tape running reference signal reproducing circuit 101 does not generate any output. This is a state in which the signal from the pulse generator 154 during recording is replaced by the output of the reference signal reproducing circuit lot, and the capstan motor 44 is driven to rotate at the maximum torque as in the case of starting recording, and the magnetic tape 46 is rotated. starts running. As the capstan motor 43 is rotationally driven, the tape running reference signal reproducing circuit 101 amplifies the output detected by the magnetic head 50-18 and outputs 1) the output signal 1. generates output. The output of the tape running reference signal reproducing circuit lO1 is output from the switch 28-2.
via the comparator circuit 41 and the frequency-voltage converter 15
5. As a result, the capstan motor has a phase cycle of the output of the tape running reference signal generation circuit 102, and the difference between the output voltage of the speed reference voltage generator 153 and the output of the frequency-voltage converter 155 always settles to zero. The capstan motor 44 is always rotated at a rotation speed corresponding to the controlled sampling frequency. Also, when the control signals r, -' and the output of the generator 115 generate outputs of other sampling frequency identification codes, the capstan motor 441 rotates at the rotational speed corresponding to the contents of the sampling frequency identification codes, and the magnetic The tape 46 runs at a cutting speed IW corresponding to the sampling @ wave number.

Therefore, following step a, the tape 46 is driven at a speed corresponding to the period t1 sampling frequency fs2 = 44.1 kHz (step b). Magnetic head 50-1? The detected output is amplified by an amplifier 104, the output of the first signal is equalized by a waveform equalization circuit 105 in response to the content of the identification code with a sampling frequency of 44.1kHz, and the waveform is shaped by a waveform shaping circuit 106. . Here, equalizer amplifier 105-1 is amplifier 1
The pulse slimming circuit 105-2 smoothes the frequency characteristic of the required frequency occupied band of the signal supplied from the equalizer amplifier 105-1 to the required width. 1 of the signal supplied from the amplifier 104, which is a narrowing circuit.
Output value of 12 band and equalizer amplifier 105-1! ) The pulse width of 〉/pulling frequency changes if the pull frequency is different, so the frequency characteristics of the equalizer amplifier and the delay time of the delay circuit configuring the pulse slimming circuit 105-2 are sampled by the control signal from the control signal generation circuit 115. It is varied according to the content of the same wave number identification code.

The integration circuit 105-3 is provided because the characteristics of recorded poems on magnetic tape exhibit differential characteristics, and the purpose is to perform pulse slimming and then integrate to compensate for the differential characteristics. In addition, the waveform shaping circuit includes a DC regeneration circuit 106-1.
5q is 1 of the output signal of the integrating circuit 105-3.
This is to perform so-called DC level reproduction by comparing the DC levels of the 1: half wave and the negative half wave.

In the waveform shaping circuit 106, the output of the waveform equalization circuit 105 is waveform-shaped by comparison with the DC reproduction circuit 106-1, so that even if there is a fluctuation in the DC level, the waveform is reliably shaped.

Bit synchronization detection circuit LO from the output of waveform shaping circuit 106
7. A bit synchronization signal and a frame synchronization signal are detected by the frame synchronization detection circuit 108. The bit synchronization signal is detected by a frequency divider 107 that divides the edge of the output of the waveform shaping circuit 106 and the output of the VCO 107-3 as shown in FIG.
It is detected by comparing the phase with the signal edge created from -4.

Note that the free-running frequencies of C01 and C07-3 are switched by the sampling frequency identification code.

A bit synchronization signal and a frame synchronization signal are provided,
The output of the waveform shaping circuit 106 is demodulated by a demodulator 109. This demodulated output is a sampling frequency identification code and a sub code, and is subjected to error correction in an error correction circuit 112, supplied to a serial/parallel converter 113-1, converted to parallel data, and then converted to parallel data by a data detection circuit 113.
-2 to 1.13-3. Assuming that the demodulated sampling frequency identification code corresponds to a sampling frequency of 44.1kHz, an output is generated at the terminal Gll of the data detection circuit 113-2, and the counter 1
14-1 counts it at least once and generates an output α. The control circuit 1]6 that received the output α receives data at a sampling frequency of 63 fs2 = 44.1kHz: +
In step c), the control circuit 116 detects the tape running reference signal generating circuit 102 for a predetermined period (t2) after receiving the output α.
And the switch is opened to output the code corresponding to the sampling frequency of 44.1kHz to the speed reference voltage generator 153.
11.5-15. As a result, the speed of the magnetic tape 46 is maintained for a predetermined period (t2'), Fs2 = 4
4. The tape running speed is fixed at a speed corresponding to IkHz (step d). Counter 1 within this predetermined period (t2)
When counter 15-1 counts discriminative errors with a sampling frequency of 44.1 kHz, counter 11.5-1 generates an output. With this output of the counter 115-1, the changeover switch circuit 115-5 is set to 1, and the output from the terminal G]2 of the data detection circuit 113-2, that is, the identification code of the sampling frequency of 44.1 kHz, is output from the launch circuit 11.
5-8.

On the other hand, the output of the force counter 115-1 is the OR circuit 115-10.
, I l 5-+1 via counter 115-2, ]
, 15-3 and at the same time, OR circuit 11
5-12 to a delay circuit 115-13. Delay circuit 115-131o In response to this, OR circuit 11
The control circuit 116 generates at its output a signal that is delayed by a predetermined interval from the signal supplied from the signal supplied from the circuit 115-12. Notifies the state that the detection codes of N and N are detected (step e).The output of the output circuit 115-13 is 1 bit, which is also supplied to the rich circuit 11. The output from G12 is transferred to the latch circuit 1.15-8.At the same time, the output from the delay circuit 115-13 is applied to the switch circuit 115-1.
4, 115-15 is determined by 9) and the launch output of the Usochi circuit 115-8, that is, the sampling frequency 4
4. An identification code of IkHz is supplied to the tape running main signal generating circuit 102 and the speed reference voltage 153 in place of the output from the control circuit 116, and the magnetic tape running speed is set to sampling frequency isolation fs2 = 44.1 kHz. It is controlled to a degree corresponding to ('step, puf).

On the other hand, the error detection output from the error correction circuit 112 is passed through the OR circuit 115-19 to the low flip 2 amplifier 115.
-20 is combined, low flip-flop +15-2
The output of 0 is counted by the counter 115-21 and Fs2
= 44.1k) The number of corrections of the identification code of the sampling frequency of lz is monitored (step g). When the error detection output is detected M times, the counter 1.15-21 generates an output (step h), the output of the counter 115-2+ is supplied to the control circuit 116, and automatic regeneration is stopped 1-
At the same time, the output of the counter 115-21 is supplied to the automatic stop display circuit 117, and the automatic stop display circuit 117 is displayed (step i). 5-22 Differential circuit 115-23
The signal is supplied to the launch circuit 115-8 via the latch circuit 115-8, and the latch circuit 115-8 is set. On the other hand, when there is no error detected by the error detection circuit 112 in step h, or until reaching M times, the running speed of the magnetic tape is controlled to 44.1 kl (corresponding to the sampling frequency of z). Ru.

Note that -1- is a case where an identification code with a sampling frequency of 44.1 kHz is detected by the magnetic sensor 5'0-17. To the magnetic field 71"50-17, when the identification mark of sample 1 non-circular wave number 44.1kHz is detected, the sampling frequency is 32 from step C.
If the identification code of ktlz is detected, that is, the output of the counter 114-3 is detected, step C2), and if the identification code of the numbering station wave number 3'2kHz is detected, step C2 is detected. Then step d2, e
2, f2, g2. h2,l is executed. This is the same as step d, e, f, g, h, and j. Also, in step C2, the sampling frequency is set to 32 kllz
When the identification code>JI fl'gin is not detected at least once, or when the identification code with sampling frequency 44.1k)lz is not detected N times in step I, proceed to step C2. , or ST〉・pue
Then, in step bl), set the running speed of the magnetic tape to a speed corresponding to the sampling frequency of 48 kHz for a predetermined period (tl).
tl)/pulling frequency 48 k) When the identification code of Iz is detected at least once (Step 2 C1),
When the identification code of lz is not detected once within a predetermined period (tl), or when the identification code of lz is not detected once within a predetermined period (tl), If the identification code of sampling frequency fi48kHz is not issued within the period (t2), step C1
, or following step e1, the control circuit 116 outputs a code corresponding to the sampling frequency 32k)lz as an output signal of the control signal generating circuit 115 for a predetermined period (b2), within a predetermined period (tl). When a detection code of sampling frequency 32k)lz is detected at least once [step]), step d2 is subsequently executed. When the identification code -j- with a sampling frequency of 32 kHz is not detected even once in step j, or when the predetermined period (
If an identification code with a sampling frequency of 32 kHz is not detected N times within t2), step k is executed. That is, the code corresponding to the sampling frequency of 32 kHz supplied from the control circuit 116 is detected by the pattern detection circuit 115-16 and counted by the counter 115-17. When the total k (+/f of the counter 115-17 is "°2"), that is, when the expected sampling frequency identification code is not detected even after repeating the same operation twice, step i is executed, and the counter 115-17 is When the count value is ``2°'', μ) and step 6 is executed.

As described in 1- above, the running speed of the magnetic tape 46 is controlled to a speed corresponding to the content of the sampling frequency identification code, that is, the sampling frequency detected by the magnetic spatula F50-17.

Since the output of the control signal generation circuit 115 is insufficiently supplied to the waveform equalization circuit 105, bit synchronization detection circuit 107, master oscillator 16, and timing pulse generation circuit 118, the frequency characteristics of the waveform equalization circuit 105, ) - The free-running 4 wave number of -3 of VCOI O7 of the synchronous detection circuit 107, the oscillation frequency of the master oscillator 16, and the timing pulse output from the timing pulse generation circuit 118 are switched in accordance with the sampling frequency.

Further, the output of the demodulator 109 is supplied to a sub-code decoder 119 and a CRC detection circuit 120 together with a bit synchronization signal and a frame synchronization signal, and demodulation 'IIj109
The sub-code being output is decoded by a sub-code decoder 119, and the decoded output is placed in a sub-code register 122. Also, errors in the sub-code are detected by the CRC detection circuit 120.
The pointer set there is supplied to the CRC pointer register 121. CRC pointer 121
sends control number 48 to the sub-code register 122, and when a pointer exists in the CRC pointer register 121, the sub-code register 1 before the pointer is set is sent to the sub-code register 122.
Output from 22. Also, the CRC pointer register 121
When the pointer does not exist in the subcode register 122, the subcode checked by the CRC detection circuit 120 is outputted from the subcode register 122. Also, from the CRC pointer register 121, error correction I
A control signal is also sent to the F circuit 112, and when there is no pointer in the CRC Voinote register 121, a control signal that does not cause the error correction circuit 112 to perform an error correction operation is sent, and when a pointer is present, an error correction 1 is sent.
Error correction IT- to the circuit 112.

Sends control signals to perform operations.

The timing pulse generation circuit 111 receives the hit synchronization signal detected by the bit synchronization detection circuit 107 and the frame synchronization signal detected by the frame synchronization detection circuit 108, and generates various timings corresponding to the bit synchronization signal detected by the bit detection circuit 107. A pulse is output, and the frame synchronization detection circuit 108, the adjuster 109, and the identification code detection circuit 11
0, the error correction circuit 112, the code discrimination circuit 113, and the control signal generation circuit 115 are the bit synchronization detection circuit 10.
It is activated in response to the bee and l-synchronization signals detected at 7.

On the other hand, the code detected by the magnetic head 50-16 is amplified by an amplifier 126-18, and the code detected by the magnetic head 50-16 is amplified by an amplifier 126-18.
-18, and the output of the waveform equalization circuit 127-If (is waveform-shaped by the waveform shaping circuit 128-18. The output of the waveform shaping circuit 128-18 is equalized by the bit synchronization detection circuit 1
29-16. A bit synchronization signal and a frame synchronization signal are detected in the frame synchronization detection circuit 130-16, and the demodulator 1
It is demodulated at 31-18. The output of demodulator 131-1fi is placed in register 134-16. In addition, the output of the waveform shaping circuit 128-Ift is checked for errors in a CRC detection circuit 133-IB for each frame, and if an error is detected as a result of the CRC check, a pointer is set and the pointer is placed in the register 134-18. Output. The pointer is stored in the register 134-1ft along with the PCM code that has been CRC checked.The value set in 34-18 is stored in the storage circuit 135-18 according to the address specification of the write address generation circuit 136-16, and the write address The write address generation timing signal of the generation circuit 136-16 is sent to the write destination instruction circuit 137-18.
When a read instruction is issued from the read address generation circuit 138 and the write address generation circuit 136-18
If there is a conflict with a write instruction from the above, the write will take priority.

Also, the pin I detected by the bit synchronization detection circuit 129-18
- From the timing pulse generation circuit 132-IB that receives the frame synchronization signal detected by the synchronization signal and frame synchronization detection circuit 130-18, a human synchronization detection circuit 129-
Various timing pulses corresponding to the bit synchronization signal detected in 16 are out of output, and the frame synchronization detection circuit 130-1
8. Revenge, iI! I unit 131-18, CRC detection circuit 1
33-1ft, registers 134-16 are operated in response to a bit synchronization signal, and write address generation circuit 1
Address signals 36-18 are output.

Furthermore, the functions of the reproducing units 125-1 to 125-15 are similar to those of the reproducing unit 125-16.

The read instruction signal generation circuit 139 receives the oscillation output of the mask oscillator 16 according to the content of the sampling frequency identification code, and supplies a read instruction signal to the read address generation circuit pl, 138.

Read address generation circuit 1 receiving read instruction signal
Read from 38'71:Response is memory circuit 135-1
~l 35-16, and storage circuits 135-1 to 1
The data stored in 35-IEi is read out and written to the taint-leave circuit 140. Deinterleaving [I′+
] The data written to the differential-leave path 140 is error-corrected by the error correction circuit 156, and then sent to the differential leave path 140.
Deinterleaved at 0 and read out. When the deinterleaved PCM data cannot be corrected by the error correction circuit 156, it undergoes error correction by the error correction fL circuit 14+. When an error is disputed or the error can be corrected, the PCM code of the left channel audio is directly supplied to the D/A converter 142 and converted to an analog signal, and the PCM code of the right channel audio is sent to the D/A converter 142. 143 and is converted into an analog signal.

The analog signal output from the D/A converter 142 is supplied to a deglitcher 144, and the analog signal output from the D/A converter 143 is supplied to a deglitcher 145 to remove glyphs. The outputs of the filters 146-1 to 146-3 are supplied to the low-pass filters 146-1 to 146-3, and the output of the daglicher 145 is supplied to the low-pass filters 146-1 to 146-3.
1-147-3. Low pass filter 146
One of the outputs of -1-146-3 is selected by the selector switch circuit Sl', amplified by the buffer amplifier 149, and supplied to the output terminal OL, where the left channel sound it! is reproduced. A signal is output. Low pass filter 147
One of the outputs -1 to 147-3 is selected by the changeover switch circuit S2', amplified by the buffer amplifier 150, and supplied to the output terminal OR, where the reproduced right channel audio signal is output.

On the other hand, the output of the control signal generation circuit 115 is supplied to the decoder 148 and decoded, and the decoded output causes the changeover switch circuit 81'.

92' is switched to control the gain of buffer amplifiers 149,150. That is, filters 146-1 to 14
6-3.147-1 to 147-3 are switched corresponding to the sampling 1'' wave number of the PCM code recorded on the magnetic tape, and the D/A converters 142 and 143
The high-frequency components of the analog signal converted by are removed in accordance with the sampling frequency, and the buffer amplifiers 149
The gain of 150 is also switched corresponding to the sampling frequency, and the low pass filters 146-1 to 146
-3 loss difference and low pass filter 147-1-
147-3 loss difference is compensated.

Control signal V) Timing pulse generation circuit 1 receiving the output of the generation circuit 115 and the output of the mask oscillator 16
18 generates various timing pulses corresponding to the sampling frequency and outputs the read finger iI (address generation circuit 1).
38, read instruction signal generation circuit 139, deinterleave circuit 140, error correction circuit 156, D,/A converter 142, 143, deglincher 144, 145, error correction circuit 141.
Signal processing is performed at a signal processing speed according to the sampling frequency of the PCM code recorded in the PCM code.

Moreover, the output of the control signal generation circuit 115 is "o
"Set circuit 151.152, D/A converter 142.1
43- If a non-transmission hint is determined in advance according to the sampling frequency, the bit corresponding to the non-transmission bit is set at 0°.

If the non-transmission bit is not determined in advance according to the sampling frequency, the control 4311 circuit 124 reads the code representing the number of non-transmission points sent as a sub-code, and the control circuit 124 outputs °O°', .

circuits 151, 152 and D/A converters 142, 14
A control signal (not shown) is sent to No. 3 to set the corresponding non-transmission bit to 0'.

1 - As explained above, according to the present invention, the magnetic recording medium Hiragi! ! By configuring the IIJ speed to be variable, the running speed of the magnetic recording medium and signal processing can be adjusted according to the sampling frequency during recording without changing the number of tracks recorded on the magnetic recording medium or the number of words per trunk constituting a frame. In addition to controlling the processing speed of the system, sampling frequency information corresponding to the sampling frequency is recorded on the magnetic recording medium, and during playback, the running speed of the magnetic recording medium is adjusted according to the sampling frequency information recorded on the magnetic recording medium. In addition, in order to control the processing speed of the signal processing system, it is not necessary to provide multiple pairs of signal processing systems that are concerned with differences in sampling frequencies, and the minimum recording wavelength can be made almost the same, resulting in good double-capacity transmission capability.

Since both systems use the same verity check system, the error correction ability can be made almost the same regardless of the sampling frequency.

In addition, the aliasing noise is eliminated in ν) by switching the passband of the input amplified analog signal (tlf range) and switching the passband of the 1)/A-converted analog signal in response to the -17-embedding frequency.

Table 1

[Brief explanation of drawings]

FIG. 1 ta+, FIG. 1 (b), and FIG. 1 (C) are block diagrams showing one embodiment of the present invention, and FIG.
is the i-line system, and Fig. 1 (bl and Fig. 1(c) is I1
The first generation system is small. FIG. 2 is a schematic diagram of an equalization circuit and a waveform shaping circuit according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a synchronization detection circuit according to an embodiment of the present invention. Figure 1 is one implementation of the present invention! /ll t/C puter
:f 13 Circuit, detection count kakunta, and control (i ''+) Bootsque diagram of the raw circuit.
flowchart. 1.2.149] 5o...no-nofu 7 amplification,
:3-1~:4-3.7I-1~4-, 111('N
-1 to 1) -3 and 147-+ to 147-: + ・
1-1-・Kusufino 1-ta, 7 and 8...the/puruan 1-rl--nod 1・times 1 old, 0 sun, 9 and +o
- A/D converter, 11 and I2-...1) and Q
inspection! 7-t'5'a rebirth IJl'l, 1u, l:
(5-+~135-+6-・, iL circuit,] 4. System control circuit, 1G. Master master and shaker, 17.111
+ 118.132-+~132-16...Timing pulse generation circuit, 18--Tape running yarn j4i signal generation circuit, 19--The/pulling frequency identification code generation circuit, 20--Generation circuit with sub. 2]...Error correction code generation circuit, 22.33-1 to 3.3-17...Selector, 25.-Demultiplexer, 26.35-1 to 3
5-+6-recording amplifier, 28-1 o 6 yo 28-2...
+IG raw recording switch, 30- +~30-17・
・Recording section, 31-1 to 3]-16 ・CaC code generation circuit, 32-+ to 32-・17 . . . Hummus synchronization code generation circuit, 34-1 to 3 7 . . Modulator, 40-1 ~40
-18 and 50-1 to 50-+8・Magnetism, de, 41
--Comparison episode ``6.712-Servo 1111 Chapter I device, /
I4...Capstan motor, 45...Gyanostor/
, Jol... To the cape running nol 1 (M month r'') small circuit, 102... The tape running reference signal is the generation circuit, 105
．． 127-+ to 127-16..., waveform equalization circuit, 1
06, +28-1~128-+6-waveform shaping opening/closing, 1
07, ] ] 29-+ ~ 129-16・hi, 1・synchronous construction circuit, 1()8, +3(1-+ ~130-16・)V
-Music synchronization detection 11j N ll'H1109, 13] -1
~] 3]-16-・1u tone rJ, l ] El ・1
i'& yJi No. Yokoide circuit, 113...attached 1j lp
1 circuit by H, l11-・Detection number counter, 115...
Konotrono j + I, TI5 Umu small circuit, 116 ・
Control circuit, 117 ・Self! l of e-coin] [, presentation circuit,
136-1 to 136-+6- Write/Tons generation circuit, +38-'+t)'' seepage 7 [・Vsuzut)
k 11j1 path, 139...readout finger 4 kujin bow cattle 1''11 path, 119...eye/tally 7゛ circuit, 14
2 and 0: + 43-1] / A Transformer, +53・Series +
W reference voltage generation a, +54...Pulse generator V-t, 1
55・Frequency λ-1d pressure converter, 156-・-Error 1-
11' 1lir old. 1.1. 〆[Exit 11] (1 person trio stock company + 1 agent patent attorney Suna f-i) Husband procedural amendment 1. Display of the case 1982 Patent Application No. 178987 2 Name of the invention Magnetic recording and reproducing device 3 Person making the amendment Relationship to the case Patent applicant Address 2-17-5 Shibuya, Shibuya-ku, Tokyo Name (359)
)) Rio Co., Ltd. Representative: Ishizaka-Yoshi 4, Agent Address: 512 Kyodo Building (Shin-Aoyama), 5-9-15 Minami-Aoyama, Minato-ku, Tokyo 107 Den 49B-1587
On his own initiative. 6. Target of correction −□″゛＼ ゛＼Drawing t'9C, 70, 60 7. Contents of correction Figure 1 (in Figure 1) and Figure 4 of the drawing will be revised as attached.

Claims (1)

[Claims] Double the amount by 1 pg OM? : In a magnetic recording/reproducing device that converts the code into a + sign and records it on a magnetic recording medium, detects the recorded POM code, and generates rQ as an analog signal, the number of tracks recorded on the magnetic recording medium by I'tL -V, When recording without changing the layout of the frames and the number of words per frame, the sample frequency yx'Y (c
Accordingly, the passage range (1) of the human-powered analog signal is switched, and the running speed of the magnetic recording medium and the m>-3 processing speed IW of the signal processing system are controlled, and the magnetic 1. Sampling frequency information corresponding to the sampling link frequency and running speed reference information of the magnetic recording medium are recorded on the magnetic recording medium, and during one playback, the running speed of the magnetic recording medium υ) is determined according to the sampling frequency information recorded on the magnetic recording medium. 1: In addition to controlling the signal processing speed of the signal processing system, /'A
IJi ++Analog I1. 1) A magnetic reproducing device that is characterized by being designed to closely match the passband of the bow.