JPS6070553A - Magnetic recording and reproducing system - Google Patents

Abstract

PURPOSE:To detect a bit synchronizing signal surely by controlling the automatic travelling oscillation frequency of a voltage control oscillator in a bit synchronization detecting circuit in accordance with sampling frequency information. CONSTITUTION:The bit synchronization detecting circuit 107 consists of an edge extracting circuit 107-5 extracting the edge part of a signal from a frequency divider 107-4 after receiving an output from a waveform shaping circuit 106, a phase comparator 107-1 comparing the phase of the edge of the circuit 106 with that of the edge of the circuit 107-5, an error amplifier 107-2, the voltage control oscillator VCO107-3 controlled at its automatic travelling frequency by the contents of a sampling frequency detecting code and controlled at its oscillation frequency by an output of the error amplifier 107-2, and a PLL circuit composed of a frequency dividing circuit 107-4. Since the automatic travelling oscillation frequency of the PLL is controlled so as to be switched by the sampling frequency as shown above, a bit synchronizing signal can be surely detected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic recording/reproducing apparatus equipped with a fixed head and capable of processing PCM signals encoded at different sampling frequencies using the same signal processing system.

Sampling when an input signal is sampled in a magnetic recording and reproducing device that is equipped with a plurality of fixed heads and records and reproduces a PCM signal obtained by converting an audio signal.

There are various frequencies, and there is no standard sampling frequency.

PCM samples sampled at different frequencies
It would be extremely advantageous if the signals could be processed by the same transmission system and signal processing system.

(Object of the Invention) The present invention has been made in view of the above, and an object of the present invention is to provide an AI magnetic recording/reproducing device that can be processed by the same signal processing system regardless of differences in sampling frequency.

(Structure of the Invention) The present invention provides a magnetic recording and reproducing apparatus that converts an analog signal into a PCM code and records it on a magnetic recording medium, detects the recorded PCM code, and reproduces the analog signal. During recording, the running speed of the magnetic recording medium and the signal processing speed of the signal processing system are controlled according to the sampling frequency without changing the number of tracks, the track arrangement that makes up the frame, and the number of words per track. Sampling frequency information corresponding to the sampling frequency and running speed reference information of the magnetic recording medium are recorded on the recording medium, and during reproduction, &j5 is detected from the recording medium according to the sampling frequency information recorded on the magnetic medium. The present invention is characterized in that the free-running oscillation frequency of the voltage-controlled oscillator of the bit synchronization detection circuit that detects the synchronization signal, the running speed of the magnetic recording medium, and the signal processing speed of the signal processing system are controlled.

The present invention will be explained below with reference to Examples.

FIGS. 1(a), 1(a), and 1(c) are block diagrams showing the configuration of an embodiment of the present invention. FIG. 1(a) shows the recording system, FIG. ) indicate the reproduction system, and since the magnetic tape drive system is the same, only the reproduction system is shown.

In one embodiment of the present invention, a case will be explained in which two-channel analog audio signals are converted into PCM codes and recorded and reproduced.

First, the recording system will be explained. Input terminal INL, INH
The left and right channel analog audio signals supplied to the left and right channels are respectively supplied to buffer amplifiers 1 and 2, and the output of the buffer amplifier 1 is passed through low-pass filters 3-1 to 3-3 to prevent aliasing noise. It is supplied to The low-pass filters 3-1 to 3-3 have sampling frequencies fsl, fs2. , fs3 (for example 48k
Hz, 44.1kHz, 32kHz), its passband characteristics are set accordingly. Similarly, the output of the bass amplifier 2 is similarly filtered through low-pass filters 4-1 to 4-4-.
It is supplied to 3. The low-pass filters 4-1 to 4-3 have the same configuration as the low-pass filters 3-1 to 3-3.

The outputs of the low-pass filters 3-1 to 3-3 are supplied to a changeover switch circuit Sl that is switched by a switching signal corresponding to the sampling frequency, and the outputs of the low-pass filters 3-1.3-2.3-3 are 1 in output
select one and supply it to the gain B (variable buffer amplifier 5,
The output of the buffer amplifier 5 is fed to a sample and hold circuit 7. Similarly, low pass filters 4-1 to 4
The output of -3 is supplied to a changeover switch circuit S2 which is switched by a switching signal corresponding to the sampling frequency, and is supplied to a low-pass filter 4-1.4 corresponding to the sampling frequency.
-2.4-3 is selected and supplied to a variable gain buffer amplifier 6, and the output of the buffer amplifier 6 is supplied to a sample and hold circuit 8.

The gains of buffer amplifiers 5 and 6 are switched and controlled in accordance with the sampling frequency.

The outputs of the sample and hold circuits 7.8 are each separately supplied to an A/D converter 9.10. The outputs of the A/D converters 9 and 10 are supplied to the memory circuit 13 and stored therein. The data stored in the storage circuit 13 is sent in a predetermined order to the P test word generator 11 and the Q test word generator 12, which calculate and generate P test words and Q test words. The test word is supplied to the storage circuit 13 and stored. The PCM codes are then interleaved by changing the reading order.

Here, an address generation circuit for transferring data from the storage circuit 13 to the P check word generator 11 and Q check word generator 12 and an address generation circuit for transferring data from the P check word generator 11 and Q check word generator 12 to the storage circuit 13 are used. The address generation circuit and the write address generation circuit and read address generation circuit of the memory circuit 13 are omitted.

On the other hand, 19 receives a control signal output from the system control circuit 14 corresponding to the sampling frequency and displays an identification code as sampling frequency information corresponding to the sampling frequency, for example, for fsl -48kHz, "
01” (7), ° for fs2 = 44.1Hz
'10'', for fs3 = 32 kHz"
A sampling frequency identification code generator I!jJM outputs an identification code of 11", and 20 is a system control circuit 14.
A sub-code, for example, P
This sub-code generating circuit outputs a code corresponding to a music number corresponding to a CM code, a code indicating the number of bits of a PCM code, and a code corresponding to time, etc.

The output of the sampling frequency identification code generation circuit 19 is supplied to an error correction code generation circuit 21 that generates an error correction code and adds it to the identification code.
The signal is supplied to the memory circuit 13 and then selectively supplied to the memory circuit 13 for storage.

The data read from the storage circuit 13 is supplied to the demultiplexer 25 and distributed to the recording sections 30-1 to 30-17. In this embodiment, the case where the magnetic head has 18 tracks is shown. Recording magnetic head 40-
1 to 40-18, and the reproducing magnetic head to 50-1 to 40-18.
50-18 and magnetic helads with the same suffix correspond.

The interleaved PCM codes output from the demultiplexer 25 are stored in the recording sections 30-1 to 30-12, the P check word is stored in the recording sections 30-13 and 30-14, and the Q check word is stored in the #i section 30-1. 15. In 30-16, the sampling frequency identification code and sub-code are recorded in the recording unit 30-1.
The six records M30-1, which are respectively supplied to the input terminals 7 and 7, receive the output from the multiplexer 25 and generate a CRC code.
An RC code generation circuit 31-1, a frame synchronization coincidence generation circuit 32-1 that generates a frame synchronization code. Selector 33-
1. Modulator 34-1 that performs modulation for recording, and recording amplifier.

35-1, the frame period synchronization code generation circuit 32
The output of -1, the output of the multiplexer 25, and the output of the CRC code generation circuit 31-1 are supplied to the selector 33-1, outputted sequentially, and supplied to the modulator 34-1 for modulation. The output of the modulator 34-1 is supplied to a recording amplifier 35-1, and the output of the amplifier 34-1 is supplied to a magnetic head 40-1. The recording units 30-2 to 30-17 are configured similarly to the recording unit 30-1, and the outputs of the recording units 30-2 to 30-17 are supplied to magnetic heads 40-2 to 40-17, respectively. It is.

Therefore, signals obtained by modulating the synchronization code, interleaved PCM code, and CRC code are transmitted to the magnetic heads 40-1 to 40-1.
40-12, and a signal modulated with the sync code, P check word and CNC code is sent to the magnetic field 40-12.
．． 40-14, and the signal modulated with the synchronization code, the Q check word, and the CRCo match is sent to the magnetic head 40-15.
, 40-18, and a signal modulated with the synchronization code, sampling frequency identification code, subcode, and CRC code is supplied to the magnetic head 40-17.

The signals supplied to the magnetic head 40-18 will be described later.

The system control circuit 14 uses the sampling frequency designation signal supplied from the key switch 15 to send a switching signal determined corresponding to the sampling frequency to the changeover switch circuit S.
1. S2 and the buffer amplifier 5 as a gain switching signal.
．． Supply to 6. Systemization 118 circuit 14 sends a control signal determined corresponding to the sampling frequency to mask oscillator 1.
6. Timing pulse generator 17, tape running reference signal generator 18° sampling frequency identification code generation circuit 19
, is supplied to a speed reference voltage generator 153 via a tape running reference signal generator 102 and a reproduction/recording changeover switch 28-1, which will be described later.

Further, the system control circuit 14 supplies a sub-code generation signal based on the sub-code designation signal supplied from the key switch 15.

The mask oscillator 16 that receives the control signal oscillates at a frequency corresponding to the sampling frequency. The timing pulse generator 17 receives the output of the master oscillator 16 and the control signal from the system control circuit 14 and outputs an output at a designated sampling frequency fsl, fs2, or fs3 to the sample-and-halt circuits 7 and 8. With,
A predetermined timing pulse 15 times higher than the sampling frequency is applied to A/D converters 9 and 10. P test word generation circuit 11, Q test word generation circuit 121, and memory circuit 13
old address generator and read address generator, multiplexer 25, and CRC code generation circuit 31-1
~31-1? , frame synchronization code generation circuit 32-1~
32-17. Selectors 33-1 to 33-17, modulator 3
4-1 to 34-1? The signal is supplied to a sampling frequency identification code generation circuit 19, a sub code generation circuit 20, an error correction code generation circuit 21, and a selector 22. - Control signal from system control circuit 14 and mask oscillator 1
The tape running reference signal generating circuit 18 that receives the output from the tape running reference signal 11 outputs a tape running reference signal 11 having a frequency proportional to the sampling frequency, and supplies the tape running reference signal to the recording amplifier 26. The output of the recording amplifier 26 is sent to the magnetic head 40-1.
It is supplied to 8.

23 and 24 are non-transmission bit control circuits that set non-transmission bits to "0", for example, A/D converters 9 and 1.
For example, when the output of 0 is 16 pins, when transmitting 14 bits, the lower 2 bits of the output of A/D converters 9 and 10 are deleted, and the lower 2 bits of the output of A/D converters 9 and 10 are 0゛′ at the bit corresponding to
It is controlled by the output of the system control circuit 14 which receives a signal indicating the number of beats per word from the key switch 15.

Next, the running system of the magnetic tape 46 will be explained (first
(See figure (b)). A tape running reference signal generating circuit 102 which generates a tape running reference signal by receiving a control signal from the system control circuit 14 and the oscillation output of the mask oscillator 16 supplies the tape running reference signal to a comparison circuit 41, and the output of the comparing circuit 41 is fed to a servo amplifier. 42. The output of the servo amplifier 42 is supplied to a drive circuit 43, and the output of the drive circuit 43 is a carburetor.

The output of the drive circuit 43 drives the capstan motor 44 . 45 is a capstan. A pulse generator 154 is mechanically connected to the capstan motor 44, and the output of the pulse generator 154 is connected to the II) live recording selector switch 28-2.
It is supplied to the comparator circuit 41 via. In addition, the output of the pulse generator 154 is connected to the playback/recording switch 28-2.
is supplied to the frequency-'pressure converter 155 via
The output of the frequency-voltage converter 4+1155 and the output voltage of the speed reference voltage generator 153 are supplied to the servo amplifier 42, and the output voltage of the frequency-voltage converter 4+1155 and the output voltage of the speed reference voltage generator 153 are supplied to the servo amplifier 42 so that both voltages match and the phases of the two inputs of the comparator circuit 41 match. Controls the capstan motor 44.

Note that the reproduction/recording changeover switches other than the aforementioned reproduction/recording changeover switches 28-1 and 28-2 are omitted.

Next, the reproduction system will be explained. Magnetic head 50-18
The detected signal is a tape running reference signal with a frequency proportional to the sampling frequency and is supplied to the amplifier lOO. The output of the amplifier lOO is supplied to the tape running reference signal reproducing circuit 101, and the tape running path type signal reproducing circuit 10
The output of No. 1 is supplied to the comparator circuit 41 via the reproducing/recording switch 28-2. On the other hand, the output from the control signal generation circuit 115, which will be described later, is supplied to the tape running reference generation circuit 102 instead of the output from the system control circuit 14, and the output from the control signal generation circuit 115 is ++j raw recording off ( +7 inches 28-1 to the speed reference voltage generator 153.

103 is a sampling frequency identification code and sub code demodulation device. The signal detected by the magnetic head 5017 is supplied to the amplifier 104. The signal detected by the magnetic head 50-17 includes a sampling frequency identification code, a sub-code, and the like. The output of the amplifier 104 is supplied to a waveform equalization circuit 105, and the output of the waveform equalization circuit 105 is supplied to a waveform shaping circuit 106. The output of the waveform shaping circuit 106 is output from the bit synchronization detection circuit 107.

- It is used in the synchronization detection circuit 108 and the demodulator 109.

FIG. 2 shows an example of the waveform equalization circuit 105 and the waveform shaping circuit 106. The waveform equalization circuit 105 is an equalizer amplifier 105 that flattens the frequency within the magnetic tape signal transmission band by changing the frequency characteristics while maintaining the linear phase according to the signal from the control signal generation circuit 115, that is, the content of the sampling frequency identification code. -1 and the contents of the sampling frequency identification code, the delay time of the delay circuit is set to narrow the pulse width of the output of the equalizer amplifier 105-1 to the required width. Pulse slimming circuit i 05-2. Pulse slimming circuit 105-2
On the other hand, the waveform shaping circuit 106 includes a DC regeneration circuit 10 for generating DC 1 from the output signal of the waveform equalization circuit 105.
6-1 and a voltage comparison circuit 106 that compares the output of the waveform equalization circuit 105 and the output of the DC regeneration circuit 106-1. −
It consists of 2.

FIG. 3 shows the bit synchronization detection circuit 107. The bit synchronization detection circuit 107 receives the output of the waveform shaping circuit 106 and includes an edge extraction circuit 107-5 that extracts the edge part of the signal produced from the output of the branching device 107-4 when an edge part of the output occurs, and a waveform shaping circuit 107. The edge of the output of the circuit 106 and the frequency divider 107-4 extracted by the edge extraction circuit 107-5
A phase comparison circuit 107-1 for comparing the phase with the edge of the signal generated from the output of the signal. an error amplifier 107-2 that amplifies the phase comparison output of the phase comparison circuit 107-1; a voltage-controlled oscillator whose free-running frequency is controlled by the content of the sampling frequency detection code and whose oscillation frequency is controlled by the output of the error amplifier 107-2; (VCO)107-3, VCO107
PL consisting of a frequency dividing circuit 107-4 that divides the output of -3.
It consists of an L circuit.

The output of the demodulator 109 and the output of the bit synchronization detection circuit 107 are supplied to a sampling frequency identification code detection circuit 110, which detects the sampling frequency identification code.

The output of the identification code detection circuit 110 is sent to the error correction circuit 112.
It is supplied to.

Corrects errors in sampling frequency detection codes. The output of the error correction circuit 112 is supplied to a code discrimination circuit 113 that discriminates the sampling frequency identification code, and the output of the code discrimination circuit 113 is a detection count that detects whether the code corresponding to the sampling frequency detection code has been output at least once. It is supplied to a counter 114 and a control signal generating circuit 115 that detects whether the signal has been output eight times or more and generates an output corresponding to the content of the sampling frequency detection code. The output of the control signal generation circuit 115 is the waveform equalization circuit 105, 127-1 to 127-16. Bit synchronization detection circuit 107.129-1 to 129-18. A control circuit 116, a master oscillator 16, a decoder 148, which will be described later.
D/A converter 142.143 “0°° set 151.1
52 and the timing pulse generation circuit 118. However, D/Af converter 142.143t-Jl-
There is also a method in which the "O" sites 151 and 152 receive the control number 41 from the control circuit 124.

FIG. 4 shows a code discrimination circuit 113 and a detection same number counter 11.
4 and a block diagram of the control signal generation circuit 115.

The code determination circuit 113 includes serial/parallel converters 113-1 . Serial/parallel converter 113-1
From the output of the sampling frequency fcl, fc2,
It consists of data detection circuits 113-2 to 113-4 that respectively determine sampling frequency identification codes corresponding to fc3. Data detection circuits 113-2 to 113-4
are sampling frequency identification codes “01” and “1”, respectively.
0”, “11” (7) High potential side to terminal Gll side, sampling frequency identification code “01”, “10”, “1”
1'' is output from the terminal GI2 side.

The detection number counter 114 is connected to the data detection circuit 113, -2.
, 113-3. A counter 114-1 that counts the output of each terminal Gll side of 113-4 at least once.
, 114-2. 114-3, a counter which receives data forcibly instructing the tape speed outputted from the control circuit 116 and detects the rise and fall of the data;

Counters 114-1 to 114-4 are configured to reset and load the counters 114-1 to 114-3.
The outputs of 114-3 are each supplied to controller 116.

The control signal generation circuit 115 is the data detection circuit 11
Each terminal Gl of 3-2, 113-3, 113-4
N-ary counter 115-1-1 that calculates the output on the l side
15-3 and N-ary counters 115-1 to 115-3 are N
J changeover switch circuits 115-5 to 115-7, which are switched by the output when counting, and the recycle switch circuit 11.
5-5 to 115-7, and a latch circuit 115-8 that latches the outputs of the data detection circuits 113-2 to 113-4 on the terminal 012 side. Control signal generation circuit 115 also. OR circuits 115-9 to 115-1 receiving reproduction instruction pulses from control circuit 116
The OR circuit 115-8 is further supplied with the outputs of counters 115-2 and 115-3, and the OR circuits 115-10 are further supplied with counters 115-1 and 115. -3 output is supplied, and the OR circuit 115-11 is further supplied with the counter 115-3.
The outputs of 1 and 115-2 are supplied, and the outputs of OR circuits 115-9 to 115-11 are supplied as signals to respective counters 15-1 to 115-3 to generate outputs. Reset counters that have not been set. The outputs of the counters 115-1 to 115-3 are supplied to the OR circuit 11FI-12, and the output of the OR circuit 115-12 is supplied to the delay circuits 115-13 to 116, and also to the latch circuit 115-8 as a latch pulse. At the same time, it is supplied as a signal switching signal to switch circuits 115-14 and 115-15, and outputs the output of the output circuit 115-8 as the output of the generating circuit 115, which receives the control signal via the switch circuit 115-14. . Control circuit 116
Data for forcibly instructing the tape speed outputted from is supplied to the pattern detection circuit 115-I6, and set in the pattern detection circuit 115-16 to detect a pattern such as fs3.
= 32 k) The pattern for lz is detected, and the output of the pattern detection circuit 115-18 is in the state of the counter 115.
-17 and outputs the count twice to the controller 11.
6 and automatic stop display circuit 117. The reproduction instruction pulse from the control circuit 116 is differentiated by the quantity division circuit 115-18, and the counter 115-17 is reset.

The error detection output from the error correction circuit 112 is sent to the low flip-flop circuit 115- via the OR circuit 115-19.
20 as a clock pulse, and the LoFlimp circuit 1
The output of 15-20 is supplied to an M-ary counter 115-21 that counts the number of errors. The output of the counter 115-21 that has counted the number of errors M times is the OR circuit 115-
22, the output of the OR circuit 115-22 is differentiated by a differentiating circuit 115-23, and this differentiated output is used as the launch circuit 11.
Reset 5-8.

On the other hand, a signal generated every frame, similar to the frame periodic output detected by the frame synchronization detection circuit 108, is supplied to the low flip-flop circuit 115-20 as a recent signal t), and the state count is reset every frame. do. Similar to the frame synchronization output, the signals generated for each frame are simultaneously supplied to the AND circuit 115-24, and the output of the AND circuit 115-25 is the differential circuit L l 5-2.
5, the differential output resets the counter 115-21, and the output of the counter 115-21 is reset for each frame. On the other hand, the flop circuit 115-
The output of 20 is inverted and supplied to an AND circuit 115-24, which inhibits resetting of the counter 115-21 by a signal generated every frame when an error is detected.

Output of demodulator 109, output of hit synchronization detection circuit 107 (hereinafter referred to as focus synchronization signal), and frame synchronization detection circuit 1
08 (hereinafter referred to as a frame period signal) is supplied to a sub-code decoder 119 and a CRC detection circuit 120, which detects the sub-code from the output of the demodulator 109, and sends the sub-code to a sub-code register 122. supply to. The CRC detection circuit 120 detects an error in the sub-code, and when an error is detected, supplies a pointer indicating an error to the CRC pointer register 121.
The output of the CRC pointer 121 that stores the pointer is supplied to the sub-code register 122, and if there is no pointer in the CRC pointer register, the sub-code register sends the error-checked sub-code to the control circuit 124 and display circuit 123, and the pointer is If so, the sub-code in which no error was detected before the pointer was raised is sent to the control circuit 124 and the display circuit 123. The output of the sub-code register 122 is supplied to a display circuit 123 and a control circuit 124, and the display circuit 123 displays the contents of the sub-code stored in the sub-code register 122, and controls according to the contents of the sub-code. The circuit 124 is controlled, and the output of the control circuit 124 is used to select, for example, a song number.

Further, the timing pulse generation circuit 111 receives the bit synchronization signal detected by the bit period detection circuit 107 and the frame period signal detected by the frame period detection circuit 108, and operates the frame synchronization detection circuit 108 and the demodulator 109. ,
Identification code detection circuit 110, error correction circuit 112, code discrimination circuit 113, control signal generation circuit 115
A timing pulse corresponding to the output of the pin I/synchronization detection circuit 107 is supplied to each of the pin I and synchronization detection circuits 107.

Further, the outputs detected by the magnetic helads 50-1 to 50-18 are separately supplied to the reproducing units 125-1 to 125-18, respectively.

The reproduction section 125-18 includes an amplifier 126-18 and an amplifier 126-16 that amplify the detection output from the magnetic head 50-16.
a waveform equalization circuit 127-16 that equalizes the output of the waveform equalization circuit 127-I8, and a waveform circuit 128-1 that shapes the output of the waveform equalization circuit 127-I8.
8. A bit synchronization detection circuit 129-16 and a frame synchronization detection circuit 130-1 that respectively detect a bit synchronization signal and a frame period signal from the output of the waveform shaping circuit 128-18.
8. Timing pulses are generated from the demodulator 131-16 that demodulates the output of the waveform shaping circuit 128-1[1, the bit synchronization signal detected by the bit synchronization detection circuit 129-16, and the frame synchronization signal detected by the frame synchronization signal detection circuit 130-IEI. A timing pulse generation circuit 132 that generates
-16, which are similar to the code demodulator 103. The output of the waveform shaping circuit 12B-16 is supplied to the CRC detection circuit 133-1ft. On the other hand, demodulator 1
The demodulated output of 31-18 is supplied to the register 134-I8, and the register 104-16 is connected to the CRC detection circuit 13.
3-18, the error-checked data is temporarily stored, and the pointer output from the CRC detection circuit 133-IEI is stored as a pair with the data, and the data and pointer are sent to the storage circuit 135-18. The output of the register 134-18 is sequentially stored in the storage circuit 136-16 at addresses specified by the write address generation circuit 136-16. The reproduction unit 125-18 also includes a write priority instructing circuit that receives the generated address of the old address generation path 136-18 and controls a read address generation circuit 138 (described later) to give priority to writing to the storage circuit 136-18. We are prepared. The timing pulse generation circuit 132-16 is the frame period detection circuit 130-
18. Demodulator 131-1ft, cRc detection circuit 133-
18. Registers 134-16. A bit synchronization detection circuit 129 is provided for each of the interpolation address generation circuits 13B-18.
A timing pulse corresponding to the frequency of the bit synchronization signal detected at -16 is supplied.

Reproduction units 125-1 to l 25-15 are reproduction units 125-1
6, and has the same configuration as playback section 12-1 to 125-1.
2 receives the detection outputs of the magnetic radars 50-1 to 50-12, respectively, and sends the PC to the memory circuits 135-1 to 135-12.
M codes are stored, and the reproducing units 125-13 to 125-18 receive the detection outputs of the magnetic heads 50-13 to 50-18,
P test word data and Q test word data are stored in storage circuits 135-13 to 135-IEi, respectively.

A read instruction signal generation circuit 139 that generates a data read instruction signal and a deinterleave control signal supplies the data read instruction signal to a read address generation circuit 138, and the read address generation circuit 138 operates at a period corresponding to the sampling frequency. The read address is supplied to the memory circuits 135-1 to 135-18. The data read from the memory circuits 135-1-135-16 is DE.

The data supplied to the interleaving circuit 140 and written to the detouring circuit 140 are error correction circuit 11-circuit 15.
6 is taken in in a predetermined order, and subjected to error weighting, is dither-leaved by a dither-leave circuit 140, and is supplied to an error-measuring circuit 141.

On the other hand, the timing pulse generator l18 receives the output of the control signal generation circuit 115 and the output of the mask oscillator 16, and determines that the read finger 71<the address generation circuit 138,
Read instruction signal generation circuit 139. Deinterleaving circuit 140, error correction circuit 156, error correction circuit 141
, D/A converter 142.143, deglitcher 144.
145, respectively, output timing pulses corresponding to the sampling frequency.

±A situation i in which the error correction circuit 156 cannot correct the error;
In this case, the error correction circuit 141 corrects it, and when no correction is required, it is not corrected.The PCM code for the left audio output from the error correction circuit 141 is supplied to the D/A converter 142, and the PCM code for the right audio is If the D/A converter 14
It is supplied to 3. The output of the D/A converter 142 is passed through a deglincher 144 to low-pass filters 146-1 to 146-1.
46-3, and the output of the D/A converter 143 is passed through a deglitcher 145 to a low-pass filter 147-3.
1 to 147-3. Here, the frequency characteristics of the low-pass filters 146-1 to 146-3 and 147-1 to 147-3 are set corresponding to the sampling frequency.

The output of the control signal generation circuit 115 is sent to the decoder 14
8, and the output of the decoder 148 is connected to the FJJ switching circuit S'18 which selects one of the outputs of the low-pass filters 146-1 to 146-3 and the output of the low-pass filters 147-1 to 147-3. It is supplied to a selector switch circuit S'2 for selecting one of the low-pass filters 146-1 to 146-1 corresponding to the sampling frequency identification code.
46-3 and low-pass filter 147-1.
Select the output of ~147-3.

! , lJ switching circuits S', S'2 have a gain f1J I'f whose gain is switched according to the sampling frequency identification code by the decoded output of the decoder 148.
After being supplied to different buffer amplifiers 149 and 150 for amplification, the output terminals OL and OR of the left and right channels are supplied.
Both I and S are combined.

Further, the D/A converters 142 and 143 receive the output of the control signal generation circuit 115, and the output of the control signal generation circuit 115 has a sampling frequency of 32k)lz.
When the output corresponds to PCM0, the lower 2 bits of
The output of the non-transmission bit setter, which is set to 0, is supplied.

On the other hand, the non-transmission bit setters 151 and 152 receive the output of the control signal generation circuit 115, and the output of the control signal generation circuit 115 has a sampling frequency of 32 k).
When the output corresponds to lz, the lower two bits of the PCM code are 0° during error correction in the error correction circuit 156.
This is a setting device to make it so.

(Operation of the Invention) In one embodiment of the present invention constructed as described above, the operation will be explained assuming that the number of words Nw of one frame is 8 words and the number of PCM code tracks is 12 as described above.

First, the recording system will be explained.

During recording, the key switch 15 instructs the sampling frequency and sub-code, and the system control circuit 14 uses the changeover switch circuit s I ,
A J signal corresponding to the sampling frequency is output to S2, and the switching switch circuit SI, S2 has νJ corresponding to the sampling frequency. Therefore, even if the sampling frequency is changed, aliasing noise r↑ will not occur. The system control circuit 14 also includes a buffer amplifier 5
．． A gain switching signal corresponding to the sampling frequency is outputted to 6, and the gains of buffer amplifiers 5 and 6 are switched according to the sampling frequency. Therefore, the loss difference between the low-pass filters 3-1.3-2.3-3 is 1,'4
, the loss difference W between the low-pass filters 4-1.4-2.4-3 is compensated.

On the other hand, a mask oscillator 16 receives a control signal determined corresponding to the sampling frequency from the system control circuit 14.
The signal generator 18 generates an output with a frequency corresponding to the sampling frequency, and receives this oscillation output and a control signal from the system control circuit 14. Generates a reference signal.

This tape running reference signal is amplified by the amplifier 26 and then supplied to the magnetic head 40-18 to be recorded on the magnetic tape.

On the other hand, when recording, the playback/recording switch 28-1
．． 28-2 has been switched to the contact position shown in FIG. outputs a frequency corresponding to the sampling frequency, and the speed reference voltage generator 153, which receives a control signal from the system control W circuit 14, outputs a speed reference voltage corresponding to the sampling frequency. Further, the output of the pulse generator 15.4 is supplied to the comparator circuit 41 via the Iq raw recording switch 28-2, and is also supplied to the frequency-voltage converter 155. Since the magnetic tape 46 is not running, the comparator circuit 41
There is no human power or frequency-IF pressure converter 155 output voltage, and the output of the servo amplifier 42 is maximum,
The capstan motor 44 is driven at maximum torque, and the magnetic tape 46 is caused to travel. This running causes the pulse generator 154 to generate an output pulse, and the output of the pulse generator 154 is supplied to the comparator circuit 41 and compared in phase with the output of the tape running reference signal generating circuit 102.

Then, the output frequency of the pulse generator 154 is converted into a voltage by the frequency-voltage converter 155, and the output frequency is converted to a voltage by the servo amplifier 4.
2, the difference voltage with the output voltage of the speed reference voltage generator 153 and the output of the phase comparator 41 are added and amplified by the servo amplifier 42, and the servo motor 44 drives the magnetic tape at a running speed corresponding to the sampling frequency. 46 will be driven.

On the other hand, the left and right channel ANAMIG audio signals supplied to the input terminals INL and INR are amplified by the buffer amplifier 1.2 and low-pass filters 3-1 to 3-3.4-1.
~4-3, and a high frequency a-no-1 limit is performed corresponding to the sampling frequency. Low pass filter 3-1~3
-3 and the outputs of the low-pass filters 4.-1 to 4-3, one output is selected by the digital switch circuit 31 and S2 in accordance with the sampling frequency, and amplified by the buffer amplifier 7.8. . In this case, the gain of the buffer amplifier 7.8 corresponds to the sampling frequency, and the difference in loss between low-pass filters 3-1 to 3-3 and the difference in loss between low-pass filters 4-1 to 4-3 are compensated for. be done.

The output of the buffer amplifier 5.6 is supplied to a sample and hold circuit 7.8, where it is sampled and held using a sampling pulse of a frequency specified by the key switch 15. The outputs of sample ant-hold circuits 7 and 8 are converted into PCM codes by A/D converters 9 and 1O, respectively, and stored in storage circuit 13. Memory circuit 13
The PCM codes stored in the PCM codes are taken into the P check word generation circuit 11 and the Q check word generation circuit 12 in a predetermined order, and the P check words and the Q check words are loaded and stored in the storage circuit 13. When the key switch 15 specifies the number of non-transmission bits of the PCM code, the non-transmission hit is set to 0°.The control circuits 23 and 24 receive the instruction of the number of bits not to be transmitted from the control circuit 14 and set the non-transmission focus accordingly. Control to 0''. These control circuits 23 and 24 control the non-transmission bit to °°0'' to generate the P check word and the Q check word, respectively, to operate the P check gate 18 and the Q check word, and also operate the PCM code non-transmission bit. is controlled to °0"'.

The PCM codes stored in the storage circuit L3 are interleaved and read out, supplied to the demultiplexer 25, and then supplied to the recording units 30-1 to 30-12. Memory circuit 13
The P test words +: and Q test words read from the P test word +: and Q test word are supplied to the demultiplexer 25, and then supplied to the recording sections 30-13 and 30-14, the recording sections 30-15 and 3O-I8.

On the other hand, the sibling frequency detection code generator 19 receives a control signal corresponding to the sampling frequency designated by the key switch 15 from the system control circuit 14, and outputs an identification code corresponding to the sample 1 non' frequency.
This identification code l is supplied to the error tr1F code generation circuit 21, and the error tr1F code is added and supplied to the selector 22. Further, the sub-sign generation circuit 20 receives #1 from the system control circuit 14 designated by the key switch 15.
11 signal, generates a sub-code, and supplies the sub-signal C to the selector 22. The identification code and sub-code with the error correction code supplied to the selector 22 are selected by the selector 22 and stored in the storage circuit 13, and the error correction code jE'r:J read out from the notation tα circuit 13
The identification code and sub-code C to which the code has been added are supplied to a demultiplexer 25, and supplied by the demultiplexer 25 to a recording section 30-17.

The code 1 supplied to the recording units 30-1 to 30-17 is added to the frame synchronization code and the CRC code, and a predetermined value is obtained. In Table 1, W is the PCM code for the left channel analog signal, W is the PCM code for the right channel analog signal, P is the P test word, Q is the Q test word, B is the sampling frequency identification code, S indicates a sub-sign.

On the other hand, the timing pulse generator 17 receives the control signal from the system control circuit 14 and the oscillation output of the mask oscillator 16, and generates various timing pulses corresponding to the sampling frequency. , p check word generation circuit 11. Q check word generation circuit 12, write address generation circuit and read address generation circuit of memory circuit 13, multiplexer 25. CRC code generation circuits 31-1 to 31-17, frame period code generation circuits 32-1 to 32-1? , selectors 33-1 to 33-17. Modulators 34-1 to 34-17
．． Since the sampled frequency identification code generation circuit 19, the sub-code generation circuit 20, the error correction code generation circuit 21, and the selector 22 are supplied with the sampling pulse, and the sample-and-hold circuits 7 and 8 are supplied with the sampling link pulse, the designated sampling Signal processing is performed at a signal processing speed according to one link frequency.

Here, even if the designation of the sampling frequency by the key switch 15 is changed, the magnetic tape 46 is driven at a running speed corresponding to the newly designated sampling frequency. Also low, <Sfilter 3-1 to 3-4
, low-pass filters 4-1 to 4-4, buffer amplifier 5
．． The gain of 6 is changed to νJ corresponding to the newly specified sampling frequency, and the sample-and-hold circuit 7.8 samples and holds the output of the Zufa amplifier 5.6 with a sampling pulse of the newly specified frequency. To do so. Furthermore, a tape running reference signal 15 proportional to the newly specified sampling frequency is recorded on the magnetic tape 46 from the magnetic node 4O-18i. On the other hand, A/D converters 9 and 10, P check word generation circuit 11. Q check word generation circuit 12゜write address generation circuit and read address generation circuit of recording circuit 13, multiplexer 25, CRC general generation circuit 31-1
~31-17. Frame synchronization code generation circuit 31-1~
32-7, selectors 33-1 to 33-17. Modulator 34
-1 to 34-17° The sampling frequency identification code generation circuit 19, the sub-code generation circuit 21, and the selector 22 are operated by various timing pulses output from the timing pulse generator 17 and corresponding to the newly designated sampling frequency. Therefore, there is no change in the recording former node shown in Table 1, and there is no change in the minimum recording wavelength, so there is no problem in recording and reproduction.

In addition, in the case of the recording format shown in Table 1, when the sampling frequency is fsl = 48 kHz, 1 m5ec worth of PCM codes is stored in one frame, and fs2 =
44.1kl (160/14 for 7 frames in z)
The PCM code for 7 m5ec is fs3 = 32
kH2), PCM for 1.5m5ec is required for 17rem.
The code will be stored.

Next, the operation of the trf generation system will be explained.

When switching to playback, that is, when +If raw is instructed by the key switch 15, the system control circuit 14 outputs +
Instructions are given to lr students. Playback/recording switch 28-
1 to 28-3 are system control circuits 1 in synchronization with playback instructions.
By the output of key switch 4, the contact position is changed from the playback example, that is, the contact position shown in FIG.
The reproduction instruction output No. 5 is supplied to the control circuit 116, and a reproduction instruction is issued. At this point, the magnetic tape 46 has not yet been driven.

From the control circuit 116 to which the rU raw instruction has been given, a reproduction instruction pulse is sent to OR circuits 115-9 to 115-I+, 115-.
22 and at the same time the sampling frequency 1a44
．． An identification code corresponding to 1 kHz is forcibly supplied to the switch circuit 115-15 for a predetermined period (tl). The counter 115-1-115-3 is activated by the former reproduction instruction pulse.
．． 115-17. The latch circuit 115-8 is reset, the latter identification code is detected by the rising edge detection circuit 114-4, and the detection output causes the counter l 14-1-114
．． -3 is reset (stave 2 a in FIG. 5). Further, the latter identification code is outputted as an output of the control signal generation circuit 115 via the switch circuit 115-15.

This output is supplied to the tape running reference signal generation circuit 102 in place of the control signal of the system control circuit 14, and is also supplied to the speed reference voltage generator 153 for reproduction and recording! /J change switch 28
-1, and simultaneously supplied to the mask oscillator 16 in place of the control signal of the system control circuit 14. As a result, the mask oscillator 16 corresponds to the sampling frequency identification code.

oscillates at a frequency corresponding to the mixing frequency. Tape running reference signal generating circuit 1 receiving the output of the control signal generating circuit 115 and the oscillation output of the mask oscillator 16
02 generates an output with a frequency corresponding to the sampling frequency, and the speed reference voltage generator 153 which receives the output of the control signal generating circuit 115 generates an output with a voltage corresponding to the sampling frequency. However, the capstan motor 44 is in the stopped FL state, and the tape running reference signal reproducing circuit lot is not generating any output. This means that the signal from the pulse generator 154 during recording is transmitted to the reference signal reproducing circuit 101.
In this state, the capstan motor 44 is rotated at the maximum torque and the magnetic tape 46' starts running as in the case of starting recording. When the capstan motor 43 is rotationally driven, the tape running reference signal reproduction circuit 101 amplifies and reproduces the output detected by the magnetic herad 50-18 to generate an output.The output of the tape running reference signal reproduction circuit 101 is supplied to the comparator circuit 41 and the frequency-voltage converter f55 via the switch 28-2.As a result, the capstan motor has a phase period with respect to the output of the tape running reference signal generation circuit 102 and a phase period with respect to the output of the speed reference voltage generator 153. The capstan motor 44 is always rotated at a rotation speed corresponding to the controlled sampling frequency so that the difference between the output voltage and the output of the frequency-voltage converter 155 always converges to zero. Even when an output of another sampling frequency identification code is generated, the capstan motor 44 rotates at a rotational speed corresponding to the content of the sampling frequency identification code, and the magnetic tape 46 runs at a running speed corresponding to the sampling frequency. .

Therefore, following step a, the magnetic tape 46 is driven at a speed corresponding to the period t1 sampling frequency fs2 =44.1 kHz (step b). The output detected by the magnetic helad 50-17 is amplified by an amplifier 104, and the amplified output is equalized by a waveform equalization circuit 105 in response to the content of the identification code with a sampling frequency of 114.1 kllz, and is then converted to a waveform shaping circuit. At 106, the waveform is shaped. Here, equalizer amplifier 105-1 is amplifier 1
This circuit flattens the frequency characteristics of the required frequency occupied band of the signal supplied from the pulse slimming circuit 1.
05-2 is a circuit that narrows the pulse width of the signal supplied from the equalizer amplifier 105-1 to the required width. The required occupied band of the signal supplied from the amplifier 104 and the pulse of the output signal of the equalizer amplifier 105-1 Since the width changes depending on the sampling frequency, the frequency characteristics of the equalizer amplifier and the pulse slimming circuit 105-2 are controlled by the control signal from the control signal generation circuit 115.
The delay time of the delay circuit constituting the circuit is varied according to the content of the sampling frequency identification code. Also, the integrating circuit 10
5-3 is provided because the characteristics of the magnetic tape during recording exhibit differential characteristics, and the purpose is to compensate for the differential characteristics by integrating after pulse slimming. The reason why the DC regeneration circuit 106-1 is provided in the waveform shaping circuit is to perform so-called DC level regeneration by comparing the DC levels of the iE half wave and the negative half wave of the output signal of the integrating circuit 105-3. It is.

In the waveform shaping circuit 106, the output of the waveform equalization circuit 105 is waveform-shaped by comparison with the DC reproduction circuit 106-1, so that even if there is a fluctuation in the DC level, the waveform is reliably shaped.

Bit synchronization detection circuit 10 from the output of waveform shaping circuit 106
7. A bit synchronization signal and a frame synchronization signal are detected by the frame synchronization detection circuit 108. The bit synchronization signal is detected by a frequency divider 1 which divides the edge of the output of the waveform shaping circuit 106 and the output of the vcot 07-3 as shown in FIG.
07-4 is detected by comparing the phase with the signal edge created from 07-4. Note that the free running frequency of the VCO 107-3 is changed by pJ depending on the sampling frequency identification code.

A demodulator 109 demodulates the output of the waveform shaping circuit 106 by supplying the bit-to-tato synchronization signal and the frame synchronization signal. This demodulated output is a sampling frequency identification code and a sub-code, and is subjected to error correction in an error correction circuit 112, supplied to a serial/parallel converter 113-1, converted into parallel data, and then converted into parallel data by a data detection circuit 113-2. ~113-3. Assuming that the demodulated sampling frequency identification code corresponds to a sampling frequency of 44.1 kHz, an output is generated at the terminal Gll of the data detection circuit 113-2, and the counter 114-1 outputs it at least once. counts and generates an output α. The control circuit 116 that has received the output α detects data with a sampling frequency fs2 = 44.1 kHz at least once within a predetermined period (eyes), and proceeds to step c.
), the control circuit 116 applies the sampling frequency 44. .
1k) The output of the code corresponding to lz is sent to the switch circuit 115.
-15. As a result, the speed of the magnetic tape 46 is as follows for a predetermined period (t2), Fs2 = 44.1kHz
is fixed at the tape running speed corresponding to z (step d
). When the counter 115-1 counts the identification code of sampling frequency 44.1kllz within this predetermined period (t2), the counter 115-1 generates an output. This output of the counter 115-1 causes the selector switch circuit 1 to
15-5 is! , IJ is changed and the data detection circuit 113-
The output from the terminal G12 of No. 2, that is, the identification code with a pull frequency of 44.1 kHz, is supplied to the latch circuit 115-8.

On the other hand, the output of the counters 115-1 is the OR circuit 115-10.
, 115-11 via counter 115-2.1
At the same time as resetting 15-3, OR circuit 115-
12 to delay circuits 115-13. In response to this, the delay circuit 115-13 outputs an OR circuit 115-1.
The control circuit 116, which generates at its output a signal that is delayed by a predetermined period of time from the signal supplied from the control circuit 115-2, includes a delay circuit 115-2.
13 output signals are provided and the sampling frequency is 44.1
Notifies the state that the detection code of kllz has been detected N times (
Step e). The output of the delay circuit 115-13 is also supplied to the data detection circuit 113-2, which is also supplied to the launch circuit 115-8.
The output from terminal G12 is latched in latch circuit 115-8. At the same time, the output of the delay circuit 1'15-13 causes the switch circuit 115-14, l l 5-1
5 is switched so that the launch output of the latch circuit 115-8, that is, the identification code with a sampling frequency of 44.1 kHz, is used as the tape running reference signal generator circuit 102 and speed reference signal instead of the output from the control circuit 116. 153, and the magnetic tape running speed is set to the sampling frequency fs2.
= 44.1 kHz (step f) On the other hand, the error detection output from the error correction circuit 11.2 is sent to the low flip-flop and the low flip-flop through the OR circuit 115-18.
15-20, low flip-flop 115-2
The output of 0 is counted by the counter 115-21 and Fs2
The number of corrections of the identification code with a sampling frequency of =44.1 kHz is monitored (step g). When the error detection output is detected M times, the counter 115-21 generates an output (step h), the output of the counter 115-21 is supplied to the control circuit 116, automatic regeneration is stopped, and at the same time the output of the counter 115-21 is is automatic stop display circuit 1
17 and an automatic endogenous stop is displayed (step i). At the same time, the output of counter 115-21 is OR circuit 1
15-22. The signal is supplied to the latch circuit 115-8 via the differentiating circuit 115-23, and the latch circuit 115-8 is reset. On the other hand, in step h, the error detection circuit 1
When there is no error detection of 12 or until reaching M times, steps fh are repeated and the running speed of the magnetic tape is 44.
．． The speed is controlled to correspond to a sampling frequency of 1 kHz.

Note that -1- is a case where an identification code with a sampling frequency of 44.1 kHz is detected by the magnetic head 50-17. If the identification code with a sampling frequency of 44.1 kHz is not detected by the magnetic herad 50-17, it is determined from step C that the identification code with a sampling frequency of 32 kHz is detected, that is, the output of the counter 114-3 is detected.Step C2), the sampling frequency 32
When the kHz identification code is detected, step C2 is followed by steps d2, e2, f2, g2, h2, i.
is executed. This is step d.

It is the same as e, f', g, h, and i. Also step C2
When the identification code with sampling frequency 32kllz is not detected at least once in step e, or when the identification code with sampling frequency 44.kllz is not detected in step e. 'If the 1 kHz identification code is not detected N times, following step C2 or following step e, the step is to set the running speed of the magnetic tape to the speed corresponding to the sampling frequency of 48 kHz for a predetermined period (tl); step b1), the sampling frequency 48 within a predetermined period (tl) in step CI.
When the kHz identification code is detected at least once (step C1), successive steps di, el, fl,
gl, i is executed. In step CI, an identification code with a sampling frequency of 48kHz is passed for a predetermined period (tl
), or when the sampling frequency is 948k within the predetermined period (t2) in step e1.
If the Hz identification code is not detected N times, step C
1, or following step el, the control circuit 116
outputs a code corresponding to a sampling frequency of 32 kHz as an output signal of the control signal generation circuit 115 for a predetermined period (Ll) (step b2), and a detection code of a sampling frequency of 32 kHz is detected at least once within the predetermined period (tl). At the time (step j), step d2 is subsequently executed. When an identification code with a sampling frequency of 32 kHz is not detected even once in step j, or when a predetermined period of time (t
2) If the identification code with a sampling frequency of 32 kHz is not detected N times within 2), step k is executed. That is, the code corresponding to the sampling frequency of 132 kHz supplied from the control circuit 116 is the pattern detection circuit 1.
It is detected by 15-18 and counted by counter 115-17. If the count value of the counter 115-17 is "2pa", that is, even if the same operation is repeated twice, the sampling frequency a a
When the expected ff11 code is not detected, step i is executed, and when the count value of the counter 115-17 is less than 2'2', 1 and step 6 are executed.

As described in [2] below, the running speed of the magnetic tape 46 is controlled to a speed corresponding to the content of the sampling frequency identification code, that is, the sampling frequency detected by the magnetic helad 50-17.

The output of the control signal generation circuit 115 is the waveform equalization circuit 105, the bit synchronization detection circuit 107, and the mast evening oscillator 1.
6. Since it is supplied to the timing pulse generation circuit 118, the frequency characteristics of the waveform equalization circuit 105, the -3 free running frequency of the VCO 107 of the bit synchronous detection circuit 107, the oscillation frequency of the mask oscillator 16, and the timing pulse generation circuit 118 The timing pulses output from the oscillator are switched in accordance with the sampling frequency.

Further, the output of the demodulator 109 is supplied to a sub-code decoder 119 and a CRC detection circuit 120 together with a bit synchronization signal and a frame synchronization signal, and the sub-code being output from the demodulator 109 is decoded by the sub-code decoder 119, and the decoded output is is placed in the sub-code register 122. Also, an error in the sub-code ↓) is detected by the CRC detection circuit 120, and the pointer detected there is supplied to the CRC pointer register 121. The CRC pointer 121 sends a control signal to the sub-code register 122 to read the CRC
When a pointer exists in the pointer register 121, it is output from the sub-code register 122 before the pointer is set. Further, when the pointer does not exist in the CRC pointer register 121, the sub code checked by the CRC detection circuit 120 is outputted from the sub code register 122. Also, from the CRC pointer register 121, the error correction circuit 1
A control signal is also sent to the CRC pointer register 121, and when there is no pointer in the CRC pointer register 121, an error correction signal is sent to the CRC pointer register 121.
A control signal that does not cause the circuit 112 to perform an error correction operation is sent, and when a pointer exists, a control signal that causes the error correction circuit 11.2 to perform an error correction operation is sent.

The timing pulse generation circuit Ill, which receives the bit periodic signal detected by the bit synchronization detection circuit 107 and the frame synchronization signal detected by the frame synchronization detection circuit 108, generates various timings corresponding to the bit periodic signal detected by the bit detection circuit 107. A pulse is output, and the frame synchronization detection circuit 10B, demodulator 109. Identification code detection circuit 110
, the error correction IF circuit 112, the ↑ number discrimination circuit 113, and the control signal generation circuit 115 are the bit period detection circuit 1.
It is operated in response to the bit period signal detected at step 07.

On the other hand, the code detected by the magnetic head 50-16 is amplified by the amplifier 126-16, and the waveform equalization circuit 127
-18, and the output of the waveform equalization circuit 127-18 is waveform-shaped by a waveform shaping circuit 128-18. The output of the waveform shaping circuit 1281B is sent to the bit synchronization detection circuit 129.
-1ft, a bit synchronization signal and a frame period signal are detected by the frame synchronization detection circuit 130-18, and the demodulator 1
It is demodulated at 31-18. The output of demodulator 131-18 is placed in register 134-16. In addition, the output of the waveform shaping circuit 128-18 is sent to the CRC detection circuit 13 for each frame.
At 3-18: A check is performed, and if an error is detected as a result of the CRC check, a pointer is set and outputted to the register 134-18.The pointer is sent to the register 134-16 as a CRC check. The value set in the register 134-18 to be stored together with the checked PCM code is stored in the storage circuit 135-IEI according to the address designation of the write address generation circuit 136-113. The timing signal is provided by the write priority instruction circuit 137-
16 and when receiving a read instruction from the read address generation circuit 138 and the write address generation circuit 136.
If there is a conflict with the write instruction from -16, the write is given priority.

Further, the bit synchronization detection circuit 12.9 receives the bit synchronization signal detected by the bit synchronization detection circuit 129-IEi and the frame synchronization signal detected by the frame synchronization detection circuit 130-16 from the timing pulse generation circuit 132-18.
Various timing pulses corresponding to the bit synchronization signal detected in -16 are output, and the frame synchronization detection circuit 130-
Iff, demodulators 131-111, CRC detection circuit 1
33-IIl, the register 134-18 is operated in response to the bit cycle signal, and the old address generation circuit 1
36-I6 address signal is output.

Furthermore, the functions of the reproducing units 125-1 to 125-15 are similar to those of the reproducing unit 125-18. .

The read instruction signal generation circuit 139 receives the oscillation output of the mask oscillator 16 according to the content of the sampling frequency identification code, and supplies a read instruction signal to the read address generation circuit 138.

Read address generation circuit 1 receiving read instruction signal
38, the read address is stored in the memory circuits 135-1 to 135-1.
35-16 and storage circuits 135-1-135
-16 storage data is read out and written to the dinning leave circuit 140. The data written to the deinterleave circuit 140 is error-corrected by the error correction circuit 156, dinterleaved by the dinterleaf circuit 140, and then read out. When the dinterleaved PCM data cannot be corrected by the error correction circuit 156, it undergoes error correction in the error correction path 141. When there is no error or when the error can be corrected, the PCM code of the left channel audio is directly supplied to the D/A converter 142 and converted to an analog signal, and the PCM code of the right channel audio is sent to the D/A converter 143. and converted into an analog signal.

The analog signal output from the D/A converter 142 is supplied to a deglitcher 144, the analog signal output from the D/A converter 143 is supplied to a deglitcher 145 to remove glitches, and the output of the deglitcher 144 is supplied to a low-pass filter 146-. 1 to 146-3, and the output of the deglitch filter 45 is supplied to low-pass filters 147-1-147.
-3 is supplied. Low pass filter 146-1 to 14
One of the outputs 6-3 is selected by the changeover switch circuit SP, amplified by the buffer amplifier 149, and supplied to the output terminal OL, so that the reproduced left channel audio signal is output. Low pass filter 147-1 to 147-3
One of the outputs is selected by the switching circuit S2', amplified by the buffer amplifier 150, and sent to the output terminal O.
R, and the reproduced right channel audio signal is output.

On the other hand, the output of the control signal generation circuit 115 is supplied to the decoder 148 and decoded, and the changeover switch circuits Sl' and S2' are switched by this decoded output.
The gains of buffer amplifiers 149 and 150 are controlled, i.e. filters 146-1 to 146-3, 147-
1 to 147-3 are switched in accordance with the sampling frequency of the PCM code recorded on the magnetic tape, and the high frequency components of the analog signals converted by the D/A converters 142 and 143 are switched to the sampling frequency. The gain of the buffer amplifiers 149 and 150 will also be switched correspondingly to the sampling frequency, and the difference in loss of the low-pass filters 146-1 to 146-3 and the difference in the loss of the low-pass filters 147-1 to 147-3 will be reduced accordingly. The difference in losses will be compensated.

Timing pulse generation circuit 11 receives the output of control signal generation circuit 115 and the output of mask oscillator 16
8 is a read instruction address generation circuit 138 which generates various timing pulses corresponding to the sampling frequency;
Read instruction signal generation circuit 139, din-leave circuit 140, error correction circuit 156, D/A converter 142.
143, deglitchers 144, 145, and error correction circuit 141, the signal is processed at a signal processing speed according to the sampling frequency of the PCM code recorded on the magnetic tape 46.

Also, the output of the control signal generation circuit 115 is °“0°
"Set circuit 151.152, D/A converter 142.1
43, and if non-transmission bits are determined in advance according to the sampling frequency, the bits corresponding to the non-transmission bits are reset to "0"'.

If the non-transmission focus is not determined in advance according to the sampling frequency, the control circuit 124 reads the code representing the number of non-transmission bits sent as a sub-code, and the control circuit 124 outputs the code to the °°O'' set circuit 151, 152 and /A converter 142 and 143 (not shown) sends a CI signal to set the corresponding non-transmission bit to "0".
”.

As explained above, according to the present invention, the moving speed of the magnetic recording medium is configured to be variable, and the tracker for recording on the magnetic recording medium,
number of tigers that make up the frame.

Controls the running speed of the magnetic recording medium and the processing speed of the signal processing system according to the sampling frequency during recording, and records sampling frequency information corresponding to the sampling frequency on the magnetic recording medium without changing the number of words per word. During playback, the running speed of the magnetic recording medium is adjusted according to the sampling frequency information recorded on the magnetic recording medium.

In order to control the processing speed of the signal processing system and the signal processing system, there is no need to provide multiple pairs of signal processing systems regardless of differences in streaming/bringing frequencies, and the minimum recording wavelength can be made almost the same, allowing good signal transmission.

Furthermore, since the same parity check system is used, the error correction capability can be made almost the same regardless of the sampling frequency.

Further, since the vCO free-running oscillation frequency of the PLL constituting the bit synchronization detection circuit is switched and controlled by the sampling frequency, the bit synchronization signal Ij can be reliably detected even if the sampling frequency is changed significantly.

No.1 Clothes

[Brief explanation of drawings]

FIG. 1(a), FIG. 1(b) and FIG. 1(C) are professional diagrams showing one embodiment of the present invention, and FIG. 1(a) shows a recording system. (1)) and FIG. 1(c) show the regeneration system. FIG. 2 is a plot diagram of an equalization circuit and a waveform shaping circuit in one embodiment of the present invention. FIG. 3 is a schematic diagram of a bit synchronization detection circuit according to an embodiment of the present invention. FIG. 4 is a block diagram of a code discrimination circuit, a detection number counter, and a control signal generation circuit in one embodiment of the present invention. FIG. 5 is a flowchart for explaining the operation of one embodiment of the present invention. 1.2.149 and 150...buffer amplifier, 3-
1~3-3.4-+~4-3,146-+~146-3
and 147-+ to 147-3...-one pass filter, 7 and 8...sample and hold circuit, 9 and 10...A/D converter, 11 and 12...P
and Q check word generation circuit, 13.1.35-1 to 1
35-+6...1 circuit, 14... System control circuit, 16... Mask oscillator, 17.111, 118
．． 132-+ to 132-16... Timing pulse generation circuit, 18... Tape running reference signal generation circuit, 19
...Sampling frequency identification code generation circuit, 20...
- Sano code generation circuit, 21...Error correction code generation circuit, 22.33-1 to 33-17...Selector, 2
5... Demultiplexer, 26.35-1 to 35-1
6... Recording amplifier, 28-1 and 28-2... Playback ML recording switch, H, 30-1 to 30-17... Recording section, 31-1 to 31-16... CNA code Generation circuit, 32-+ to 32-17...Hummu synchronization code generation circuit, 34-1 to 34-17...Modulator, 40-1 to 4
0-+s and 50-1 to 50-+s...Magnetic head, 41...Comparison circuit, 42...Servo amplifier, 44
...Cab stano motor, 45...Capstan,
101...Tape running reference signal reproducing circuit, 102...
・Raw circuit for tape running reference signal, 105.127-+
~127-16 ... Waveform equalization circuit, 106.128
-+~128-+6... Waveform shaping circuit, 107.12
9-+ to 129-16...bit same JυJ detection circuit,
108.130-+ to 130-16... Frame synchronization construction circuit, 109.131-r-131-IG... Demodulator, 110... Identification stroke 3 detection circuit, 113...
r'f'j discrimination circuit, 114... detection number counter,
115... Kotto I Nord 11. Bow generation circuit, 116
...Control circuit, 117...Automatic stop large lj < times W
11, I 36- r ~ 13 G-+ t; ...
1'J entry 7' L-less generation circuit, 138...+r
139... 4+j generation circuit for read instruction, 140... Ditter leave circuit, 142 and 143... D/A converter, ]
53... Speed reference mixed pressure button generator, 154... Pulse generator, 155... Frequency-mixed pressure transformer, 156...
・Error correction circuit. Patent 1i 11 Person Trio Co., Ltd. Agent Patent Attorney Hakuo Sunahoshi Procedural Amendment November 2, 1980 Commissioner of the Patent Office Mr. Kazuo Wakasugi 1, Indication of Case 1982 Patent Application No. 178990 2, Name of Invention Magnetic Recording and reproducing device 3, relationship with the amended person case Patent applicant address 2-17-5 Shibuya, Shibuya-ku, Tokyo Name (359)
) ) Rio Co., Ltd. Representative Ishizaka Yoshi 4, Agent 107 Telephone 498-1587 Address 5-9-15-7 Minami-Aoyama, Minato-ku, Tokyo Contents of amendment Figure 1 (a), Figure 1 of the drawing (b), Figure 1 (C), Figure 2, Figure 3, Figure 4, and Figure 5 will be corrected as attached (the contents have not changed and were drawn on tracing paper). Procedural amendment dated October 1980 Mr. Manabu Shiga, Commissioner of the Patent Office1, Indication of the case, Patent Application No. 178990 filed in 19822, Name of the invention, magnetic recording and reproducing device3, Person making the amendment Relationship with the case Patent applicant address: 2-17-5 Shibuya, Shibuya-ku, Tokyo Name (359)
) Rio Co., Ltd. Representative Ishizaka Yoshi 4, Agent Address: 5-9-15 Minami-Aoyama, Minato-ku, Tokyo 107-498-1587 Address: 6, Drawing subject to amendment', Contents of amendment Figure 1 of the drawing (b) and Figure 4 are corrected as attached.
vinegar. that's all

Claims (1)

[Claims] Convert the 7-step signal into a POM code and record it on a magnetic dC recording medium, detect the recorded POM code, and convert it into an analog signal.
The magnetic recording and reproducing device used for recording magnetic recording can perform magnetic recording according to the recording sampling frequency without changing the number of tracks recorded on the magnetic recording medium, the track arrangement and number of words per unit that make up the frame. In addition to controlling the running speed of the medium and the No. 13 processing speed of the signal processing system,
The force that recorded the sampling frequency information and the speed reference information recorded on the magnetic recording medium and the sampling frequency information recorded on one magnetic recording medium after reproduction; the data detected from the magnetic recording medium. The free-running oscillation frequency of the voltage controlled oscillator of the bit synchronization detection circuit for detecting the bit and Z synchronization signals of the magnetic recording medium, the running speed of the magnetic recording medium, and the signal processing speed of the signal processing system are controlled. Recording and playback device.