JPS6070555A - Magnetic recording and reproducing system - Google Patents

Abstract

PURPOSE:To stabilize a reproducing function moreover by controlling the travelling speed of a magnetic recording medium and the signal processing speed of a signal processing system in accordance with detected sampling frequency information until the number of errors of the sampling frequency exceeds a prescribed number of times. CONSTITUTION:Error detection outputs from an error correcting circuit 112 are supplied to an OR circuit 115-19 and a flip-flop 115-20 and counted by a counter 115-21, and if the error detection outputs are detected M times, the output of the counter 115-21 is supplied to a control circuit 116 and automatic reproducing is stopped. When no error is detected, the travelling speed of the magnetic tape is controlled at a speed corresponding to the sampling frequency until the error detection outputs reach M times. Since the travelling speed of the magnetic tape is controlled in accordance with the sampling frequency information until the number of errors of the detected sampling frequency information exceeds the prescribed times, the sampling frequency information can be surely detected and the reproducing function is stabilized.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic recording/reproducing apparatus equipped with a fixed head and capable of processing PCM signals encoded at different sampling frequencies using the same signal processing system.

In magnetic recording and reproducing devices that are equipped with multiple fixed heads and record and reproduce PCM signals converted from audio signals, there are various sampling frequencies when sampling human signals, and there is no standardization of sampling frequencies. do not have.

It would be very advantageous if the PCM signal sampled and encoded at the same frequency was processed by the same transmission system and signal processing system.

(Object of the Invention) The present invention has been made in view of the above, and an object of the present invention is to provide a magnetic recording/reproducing device that can process data using the same 14-inch processing system regardless of the difference in sampling frequency.

(Structure of the Invention) The present invention provides a magnetic recording and reproducing apparatus that converts an analog signal into a PCM code and records it on a magnetic recording medium, detects the recorded PCM code, and reproduces the analog signal, the number of tracks recorded on the magnetic recording medium. , without changing the track arrangement that makes up the frame and the number of words per track.
During recording, the running speed of the magnetic recording medium and the signal processing speed of the Shinso processing system are controlled according to the sampling frequency, and the magnetic recording medium is provided with sampling frequency information corresponding to the sampling frequency and running speed reference information of the magnetic recording medium. , and detects that the sampling frequency information detected from the magnetic recording medium during playback is the same a predetermined number of times, and if the detected sampling frequency information exceeds the predetermined number of times. The present invention is characterized in that the running speed of the magnetic recording medium and the signal processing speed of the signal processing system are controlled unless there is an error or other sampling frequency information is detected a predetermined number of times.

Hereinafter, the present invention 1 will be explained with reference to Examples.

Figures 1 (b) and (c) are block diagrams showing the configuration of an embodiment of the present invention. The magnetic tape drive systems are the same, and only the II production system is 71<shi.

In one embodiment of the present invention, a case will be explained in which two-channel analog audio signals are converted into PCM codes and recorded and reproduced.

First, the recording system will be explained. Input terminal INL, INH
The left and right channel analog audio signals supplied to the left and right channels are respectively supplied to buffer amplifiers 1 and 2, and the output of the buffer amplifier 1 is supplied to low-pass filters 3-1 to 3-3 for preventing aliasing noise. be. Low-pass filters 3-1 to 3-3 have sampling frequencies fsl, fs2, and fs3 (for example, 48 k), respectively.
The passband characteristics are set corresponding to Iz, 44.1k) and lz, 32kHz). Similarly, the output of the buffer amplifier 2 is similarly filtered through low-pass filters 4-1 to 4-4-.
It is supplied to 3. The low-pass filters 4-1 to 4-3 have the same configuration as the low-pass filters 3-1 to 3-3.

The outputs of low-pass filters 3-1 to 3-3 correspond to the sampling frequency! /J (+) is supplied to the switch circuit S1, which is switched by the + signal, and the sampling frequency IU
Low pass filter 3-1.3-2.3- corresponding to fi
One of the outputs of the buffer 1 amplifier 5 is selected and supplied to the sofa amplifier 5 with a gain Ij (variable), and the output of the buffer 1 amplifier 5 is supplied to the sample and hold circuit 7.Similarly, the output of the buffer 1 amplifier 5 is supplied to the sample and hold circuit 7. The output of ~4-3 is switched by a switching signal corresponding to the sampling frequency!/J 44 is supplied to the switch circuit S2, and is being outputted from the low-pass filter 4-1.4-2.4-3 in accordance with the sampling frequency. 1
One is selected and supplied to a sofa amplifier 6 with a gain of oJ, and the output of the buffer amplifier 6 is supplied to a sample and hold circuit 8.

The gains of buffer amplifiers 5 and 6 are switched and controlled in accordance with the sampling frequency.

The outputs of the sample and hold circuits 7.8 are each separately supplied to an A/D converter 9.10. The outputs of the A/D converters 9 and 10 are supplied to the memory circuit 13 and stored therein. The data stored in the storage circuit 13 is sent in a predetermined order to the P test word generator 11 and the Q test word generator 12, which calculate and generate P test words and Q test words. The test word is supplied to the storage circuit 13 and stored. The PCM codes are then interleaved by changing the reading order.

Here, an address generation circuit for transferring data from the storage circuit 13 to the P check word generator 11 and Q check word generator 12, and an address generation circuit for transferring data from the P check word generator 11 and Q check word generator 12 to the storage circuit 13 are used. The address generation circuit and the read address generation circuit and the read address generation circuit of the memory circuit 13 are omitted.

On the other hand, 19 receives a control signal output from the system control circuit 14 corresponding to the sampling frequency, and displays an identification code as sampling frequency information corresponding to the sampling frequency, for example, for fsl -48kHz, '
This is a sampling frequency identification code generation circuit that outputs an identification code of 10° for fs2 = 44.1H2 and 11 for fs3 = 32 kHz, and 20 is the system control circuit 14
A sub-code, for example, P
This sub-code generating circuit outputs a code corresponding to a music number corresponding to a CM code, a code indicating the number of bits of a PCM code, and a code corresponding to time, etc.

The output of the sampling frequency identification code generation circuit 19 is supplied to an error correction code generation circuit 21 that generates an error correction code and adds it to the identification code, and the output of the error correction code generation circuit 21 and the output of the sub code generation circuit 20 are supplied to the selector 22
The signal is supplied to the memory circuit 13 and then selectively supplied to the memory circuit 13 for storage.

The data read from the Ti circuit 13 is supplied to a demultiplexer 25, and then distributed and supplied to the recording sections 30-1 to 30-17. This embodiment shows a case where the magnetic head has 18 tracks.

The recording magnetic heads are designated as 40-1 to 40-18, and the read magnetic heads are designated as 50-1 to 50-18, and magnetic heads with the same suffix correspond to each other.

The interleaved PCM codes output from the demultiplexer 25 are stored in the recording units 30-1 to 30-12, the P check word is stored in the recording units 30-13 and 30-14, and the Q check word is stored in the recording unit 30-1'. 5, 30-18, the sampling frequency identification code and sub-code are recorded in the recording unit 30-
17 respectively.

The recording unit 30-1 includes a CRC code generation circuit 31-1 that receives the output from the multiplexer 25 and generates a CRC code;
A frame synchronization code generation circuit 32-1 that generates a frame synchronization code, a selector 33-1. It is equipped with a modulator 34-1 that performs modulation for recording, and a recording amplifier 35-1, and the output of the frame synchronization code generation circuit 32-1, the output of the multiplexer 25, and the output of the CRC code generation circuit 31-1 are It is supplied to the selector 33-1 and outputted sequentially to the modulator 34.
-1 and modulate it. The output of the modulator 34-1 is supplied to a recording amplifier 35-1, and the output of the amplifier 34-1 is supplied to a magnetic head 40-1. Recording section 30-2 to 30
-17 has the same structure as the recording section 30-1, and the outputs of the recording sections 30-2 to 30-17 are supplied to magnetic heads 40-2 to 40-17, respectively.

Therefore, signals obtained by modulating the synchronization code, interleaved PCM code, and CRC code are transmitted to the magnetic heads 40-1 to 40-1.
40-12, and a signal modulated with the synchronization code, P check word, and CRC code is sent to the magnetic heads 40-13,
40-14 and modulated the synchronization code, Q check word and CRC code is a magnetic herad 40-15.4.
A signal modulated with a synchronization code, a sampling frequency identification code, a sub code, and a CRC code is supplied to the magnetic head 4'0-17.

The signals supplied to the magnetic head 40-18 will be described later.

Based on the sampling frequency designation signal supplied from the key switch 15, the system control circuit 14 transmits a switching signal determined corresponding to the sampling frequency to the switching circuit Sl.
, S2 and the eight-pass amplifier 5 as a gain switching signal.
．． Supply to 6. The system control circuit 14 transmits a control signal determined corresponding to the sampling frequency to a mask oscillator 16,
A speed reference voltage generator 15 via a timing pulse generator 17, a tape running reference signal generator 18, a sampling frequency identification code generation circuit 19, a tape running reference signal generator 102, which will be described later, and a play/record changeover switch 28-1.
Supply to 3.

Further, the system control circuit 14 supplies a sub-code generation signal based on the sub-code designation signal supplied from the key switch 15.

The mask oscillator 16 that receives the control signal oscillates at a frequency corresponding to the sampling frequency. Timing pulse generator 17 is an output of mask oscillator 16.

The sample-and-hold circuits 7 and 8 receive the output of the specified sampling frequency fsl, fs2, or fs3 in response to the power and the control signal from the system control circuit 14.
At the same time, a predetermined timing pulse corresponding to the sampling frequency is output to the A/D converter 9 and lo, P.
Test word generation circuit 11 and Q test word generation circuit 1
2. Write address generator and read address generator of memory circuit 13, multiplexer 25, CRC code generation circuits 31-1 to 31-17, frame synchronization code generation circuits 32-1 to 32-17. Selector 33-1 to 3
3-17, the modulators 34-1 to 34-17 are supplied to the sampling frequency identification code generation circuit 19, sub-code generation circuit 20, error correction circuit, gamma call generation circuit 21, and selector 22.

Control signal from system control circuit 14 and mask oscillator 1
The tape running reference signal generating circuit 18 that receives the output from the tape running reference signal generating circuit 18 outputs a tape running reference signal having a frequency proportional to the sampling frequency, and supplies the tape running reference signal to the recording amplifier 26. The output of the recording amplifier 26 is sent to the magnetic head 40-18.
It is supplied to

23 and 24 are non-transmission hit control circuits that set the non-transmission bits to "0"; for example, when the outputs of the A/D converters 9 and 10 are 16 bits, 14
When transmitting the signal I, the lower two bits of the outputs of A/D converters 9 and 10 are deleted, and the outputs of A/D converters 9 and 1 are
At the bit corresponding to the output of the lower two bits of 0, “
0°', and the key switch 1
It is controlled by the output of the system control circuit 14 which receives the word recitation bit number instruction signal from 5.

Next, the running system of the magnetic tape 46 will be explained (first
(See figure (b)). A tape running reference signal generating circuit 102 which generates a tape running reference signal by receiving a control signal from the system control circuit 14 and an oscillation output of the mask oscillator 16 supplies the tape running reference signal to a comparator circuit 41, and the output of the comparator circuit 41 is sent to a servo amplifier 42. It is supplied to The output of the servo amplifier 42 is supplied to a drive circuit 43, the output of the drive circuit 43 is supplied to a capstan motor 44, and the output of the drive circuit 43 drives the capstan motor 44. 45 is a capstan. A pulse generator 154 is mechanically connected to the capstan motor 44, and the output of the pulse generator 154 (7) is supplied to the comparator circuit 41 via the 11) live recording changeover switch 2.8-2. Further, the output of the pulse generator 154 is supplied to the frequency-voltage converter 155 via the playback/recording switch 28-2, and the output of the frequency-voltage converter 155 and the output voltage of the speed reference voltage generator 153 are supplied to the servo amplifier. 42, and the capstan motor 44 is controlled by the servo amplifier 42 so that both voltages match and the phases of the two inputs of the comparator circuit 41 match.

In addition, the Ilf raw recording switch is the above-mentioned playback recording!
, IJ Switches other than 28-1 and 28-2 are omitted.

Next, the reproduction system will be explained. Magnetic Herad 50-18
The detected signal is a tape running reference signal with a frequency proportional to the sampling frequency and is supplied to the amplifier lOO. The output of the amplifier 100 is supplied to a tape running reference signal reproducing circuit 101.
The output of 1 is supplied to the comparator circuit 41 via the ++j raw record switch 28-2. On the other hand, the control Cff mentioned later
- The output from the tape run reference generation circuit 102 is used instead of the output from the system control circuit 14.
The output from the control signal generation circuit 115 is supplied to the speed reference voltage generator 153 via the reproduction/recording changeover switch 28-1.

103 is a sampling frequency identification code and sub code demodulation device. The signal detected by the magnetic head 50-17 is supplied to the amplifier 104. The signal detected by the magnetic head 50-17 includes a sampling frequency identification code, a sub-code, and the like. The output of the amplifier 104 is supplied to a waveform equalization circuit 105, and the output of the waveform equalization circuit 105 is supplied to a waveform shaping circuit 106. The output of the waveform shaping circuit 106 is supplied to a bin I/synchronization detection circuit 107, a frame period detection circuit 108, and a demodulator 109.

FIG. 2 shows an example of the waveform equalization circuit 105 and the waveform shaping circuit 106. The waveform equalization circuit 105 is an equalizer amplifier that flattens the frequency within the 1″f range of magnetic tape signal transmission by changing the frequency characteristics while maintaining the linear phase according to the signal from the control signal generation circuit 115, that is, the content of the sampling frequency identification code. 105-1 and
The delay time of the delay circuit is set based on the content of the sampling frequency identification code, and the pulses 1llri of the output of the equalizer amplifier 105-1 are sandwiched to the required width. Pulse slimming circuit 105-2, pulse slimming circuit 1
It consists of an integrating circuit 105-3 that integrates the output of 05-2. On the other hand, the waveform shaping circuit 106 is the waveform equalization circuit 1
Comparison circuit 1 for DC 1 company which compares the output of the DC 1 company main circuit 106-1 and the waveform equalization circuit 105 and the output of the DC regeneration circuit 106-1 for DC regeneration from the output signal of 05.
It consists of 06-2.

FIG. 3 shows the bit period detection circuit 107. The bit period detection circuit 107 receives the output of the waveform shaping circuit 106 and divides the frequency when an edge portion of the output occurs.
An edge extraction circuit 107-5 that extracts the edge part of the signal created from the output of the waveform shaping circuit 106 and a frequency divider 107 extracted by the edge extraction circuit 107-5.
-4, an error amplifier 107-2, which amplifies the phase comparison output of the phase comparison circuit 107-1. The free-running frequency is controlled by the contents of the sampling frequency detection code, and the oscillation frequency is controlled by the output of the +bf difference amplifier 107-2.
, a frequency dividing circuit 107- that divides the output of the VCO 107-3.
It consists of 4 PLLH paths.

The output of the demodulator 109 and the output of the bit synchronization detection circuit 107 are supplied to a sampling frequency identification code detection circuit 110, which detects the sampling frequency identification code.

The output of the identification code detection circuit 110 is sent to the error correction circuit 112.
The signal is supplied to the circuit for error correction of the sampling frequency detection code. The output of the error correction circuit 112 is supplied to a code discrimination circuit 113 that discriminates the sampling frequency identification code, and the output of the code discrimination circuit 113 detects whether a code corresponding to the sampling frequency detection code has been output at least once every -. It is supplied to the detection number counter 114 and the control signal generation circuit 115 which detects whether N times -(- is outputted) and generates an output corresponding to the content of the sampling frequency detection code.The output of the control signal generation circuit 115 is Waveform equalization circuit 105, 127-1
~127-16, Bit synchronization detection circuit 107.129-
1-129-16. , control circuit 116, master oscillator 1
8, a decoder 148, an I)/A converter 142, which will be described later.
14.3'0' set 1.5 L, 152 and timing pulse generation circuit 118 are supplied. However, D/
A converter 142.143 and "O"-t = nits 15
．． 152 may also receive a control signal from the control circuit 124.

FIG. 4 shows the code discrimination circuit 113 and the detection number counter 11.
4 and a block diagram of the control signal generation circuit 115.

The code discrimination circuit 113 includes serial/parallel converters 113-1 . From the output of the serial/parallel converter 113-1, the sampling frequencies fcl, fc2,
It consists of data detection circuits 113-2 to 113-4 that respectively determine sampling frequency identification codes corresponding to fc3. Data detection circuits 113-2 to 113-4
are sampling frequency identification codes “O1゛°,” respectively.
10'", 11" high potential side to terminal Gll side, sampling frequency laa different code "01", "'10", "11"
are output to the terminal G12 side.

The detection number counter 114 is connected to the data detection circuit 113-2.
a counter 114-1 that counts the output of each terminal Gll side of 113-3 and 113-4 at least once;
l l 4-2. 114-3. A counter 114-1-114- detects the rising edge of the data outputted from the control circuit 116 and forcibly instructing the tape speed.
The outputs of the counters 114-1 to 114-3 each including a rising detection circuit 114-4 that resets the value of 3 are supplied to the controller 116.

The control signal generation circuit 115 is the data detection circuit 11
3-2.113-3.113-4 respective terminal Gl
N-ary counter 115-1 to 1 that counts the output on the l side
15-3 and N-ary counters 115-1 to 115-3 are N
The switching circuits 115-5 to 115-7 are switched by the output when counting, and the switching switch Jul path 1
A latch circuit 115-8 is provided for latching the output of the terminal G12 side of the data detection circuits 113-2 to 113-4 output via the data detection circuits 15-5 to 115-7. The control signal generation circuit 115 also includes OR circuits 115-9 to 115- which receive reproduction instruction pulses from the control circuit 116.
II, 115-22, OR circuit 115-9
The outputs of counters 115-2 and 115-3 are further supplied to the OR circuit 115-10, and the outputs of counters 115-1 and 115-3 are further supplied to the OR circuit 115-11. In addition, counter 115
-1 and 115-2 are supplied, and the outputs of OR circuits 115-8 to 115-11 are sent to sensors I and I respectively by counters 115-INl and 5-3.
1d to reset counters that are not generating output. The outputs of the counters 115-1 to 115-3 are supplied to the OR circuit 115-12.
The output of 2 is supplied to the delay circuit 115-13, and the output of the delay circuit 11
The output of 5-13 is supplied to the controller 116 and the latch circuit 1.15-8 as a latch pulse, and is also supplied to the switch circuits 115-14 and 115-15 as a switching signal to the launch circuit 115-8. The output of the control signal -J is sent via the switch circuit 115-14.
- Output as the output of the generation circuit 115. Control circuit 11
Data for forcibly instructing the tape speed output from 6 is supplied to a pattern detection circuit 115-I6, and the pattern detection circuit 115-1 is set to 1 to detect a pattern such as f.
The pattern for s3 = 32 kHz is detected, and the output of the pattern detection circuit 115-16 is the state power counter 1.
15-IT to provide a two-time count output to the controller 116 and automatic stop display circuit 117. Reproduction finger 1 < pulse from control circuit 116 is differentiating circuit 115
The counter 115-17 is reset with the output differentiated by -18.

The error detection output from the error stop circuit 112 is sent to the low flip-flop circuit 115- through the OR circuit 115-19.
20 as a clock pulse.

The output of the low flip circuit 1.15-20 is supplied to an M-ary counter 115-21 that counts the number of errors. The output of the counter 115-2.1 that has counted the number of errors M times is supplied to the OR circuit 115-22.
-22 output is differentiated by a differentiating circuit 115-23, and the latch circuit 115-8 is reset by this differentiated output.

On the other hand, a signal generated for each frame in the same way as the frame synchronization output detected by the frame synchronization detection circuit lO8 is supplied to the low flip-flop circuit 115-20 as a reset signal, and the state count is reset for each frame. Similar to the frame synchronization output, the signals generated for each frame are simultaneously supplied to the AND circuit 115-24, the output of the AND circuit 115-25 is differentiated by the differentiating circuit 115-25, and the counter 115-21 is reset with the differentiated output. death,
The output of the counter 115-21 is reset for each frame. - The output of the flip-flop circuit 115-20 is inverted and fed to an AND circuit 115-24, which counters 115-21 with a signal generated every frame when an error is detected. Prohibits resetting.

Output of demodulator 09, output of hinh synchronization detection circuit 107 (hereinafter referred to as bit period signal), and frame synchronization detection circuit 1
The output of 08 (hereinafter referred to as a frame period signal) is supplied to a sub-code decoder 119 and a CRC detection circuit 120, which detects a sub-code from the output of the demodulator 109, and supplies the sub-code to a sub-code register 122. The CRC detection circuit 120 detects an error in the sub-code and
A pointer indicating an error is supplied to the CRC pointer register 121 to jr, and the CRC pointer register 12
1 stores the pointer. The output of the CRC pointer 121 is supplied to the sub-code register 122, and if there is no pointer in the CRC pointer register, the sub-code register stores the error-checked sub-code to the control circuit 124 and display circuit 123.
If there is a pointer, it is sent to the sub-code total control circuit 124 and display circuit 123 where no error was detected before the pointer was set. The output of the sub-sign register 122 is supplied to a display path 123 and a control circuit 124,
The contents of the sub-code stored in the sub-code register 122 are displayed on a display circuit 123, a control circuit 124 is controlled according to the contents of the sub-code, and the output of the control circuit 124 is used to select, for example, a song number.

Further, the timing pulse generation circuit 111 detects the bit synchronization signal detected by the bit synchronization detection circuit 107 and the frame synchronization detection circuit 108.

The frame synchronization detection circuit 10 receives the frame synchronization signal.
8. A bit synchronization detection circuit 1 is provided in each of the demodulator 109, the identification code detection circuit 110, the error correction circuit 112, the code discrimination circuit 113, and the control I/roll signal generation circuit 115.
In response to the output of 07, t timing pulses are supplied.

Further, the outputs detected by the magnetic outputs 50-1 to 50-18 are separately supplied to the reproducing units 125-1 to 125-18, respectively.

The reproducing unit 125-18 includes a magnetic head 50-an amplifier 126 for amplifying the detection output of the IS, an IEI amplifier 126-1
a waveform equalization circuit 127-16 that equalizes the output of the waveform equalization circuit 127-16, and a waveform circuit 128- that shapes the output of the waveform equalization circuit 127-16.
16. A bit synchronization detection circuit 129-18 and a frame synchronization detection circuit 130- detect a bit synchronization signal and a frame period signal from the output of the waveform shaping circuit 128-16, respectively.
16. Demodulator 131-16 that demodulates the output of the waveform shaping circuit 128-18, Biy,) Synchronization detection circuit 129-If
A timing pulse generation circuit 1 that generates a timing pulse from the bit synchronization signal detected by f and the frame synchronization signal detected by the frame synchronization signal detection circuit 130-16.
32-IB, these are code demodulator 103
It is similar to The output of the waveform shaping circuit 128-18 is CR
It is supplied to the C detection circuit 133-18. On the other hand, the demodulated output of the iM modulator 131-18 is supplied to the register 134-1[i, and the register 104-16 temporarily stores the data that has been error-checked by the CRC detection circuit 133-18, and also performs CRC detection. A storage circuit 135-1 stores the pointer output from the circuit 133-18 in pairs with its data.
Send data and pointer to 8. The output of the register 134-16 is sequentially stored in the memory circuit 136-18 at the address specified by the write address generation circuit 1'36-18. The reproducing unit 125-1fi also includes a write priority instructing circuit that receives the address generated by the write address generating circuit 136-18 and controls the read address generating circuit 138 (described later) to give priority to writing to the memory circuits 136 to 16. ing. Timing pulse generation circuit 132-II (frame period detection circuit 1
30-18. Demodulator 131-18, CRC detection circuit 13
3-16. Timing pulses corresponding to the frequency of the bit synchronization signal detected by the bit period detection circuit 129-18 are supplied to the registers 134-1[1 and -5 write address generation circuits 136-Ill, respectively.

tlr student section 125-1 to 125-15 are playback gl! 12
5-18, and has the same configuration as playback section 12-1 to 12-1.
25-j2 are magnetic heads 50-1 to 50-12, respectively.
In response to the detection output of the memory circuits 135-1 to 135-12
The PGM code is stored in the playback unit 125-13-125-
In response to the detection outputs of the Iff harassment heads 50-13 to 50-18, P test word data and Q test word data are stored in storage circuits 135-13 to 135-18, respectively.

A read instruction signal generation circuit 139 that generates a data read instruction signal and a din-leave control signal supplies the data read instruction signal to a read address generation circuit 138, and the read address generation circuit 138 reads data at a cycle corresponding to the sampling frequency. The address is supplied to memory circuits 135-1 to 135-IS. The data read from the memory circuits 135-1 to l35-IEt is supplied to the de1 interleaving circuit 140, and the data written to the de1 interleaving circuit 140 is supplied to the error correction iE.
The signals are taken into the circuit 156 in a predetermined order, subjected to error correction, dinterleaved by the deinterleaving circuit 140, and then supplied to the error correction circuit 141.

On the other hand, the timing pulse generator 11B is output from the control signal generation circuit 115! J and the output of the master oscillator 16, a read instruction address generation circuit 138, a read finger/1-1 signal generation circuit 139. Deinterleaving circuit 140, error correction circuit 156, error correction circuit 1
41, D/A converter 142, 143, deglitcher 14
A timing pulse corresponding to the sampling frequency is output at 4.145, respectively.

In the error correction circuit 1, when the error cannot be corrected completely by the circuit 156, the error correction circuit 141 corrects it, and when no correction is required, no correction is made, and the PCM for the left audio of the output of the error correction circuit 141 is corrected. The code is supplied to the D/A converter 142, and the PCM code for the right audio is supplied to the D/A converter 14.
It is supplied to 3. The output of the D/A converter 142 is passed through a degrincher 144 to low-pass filters 146-1 to 146-1.
146-3, and the output of the D/A converter 143 is sent to the ronox filter 14 via the degrinnaya 145.
7-1 to 147-3. Here, low-pass filters 146-1 to 146-3, 147-1 to 147-
3 has its frequency characteristics set in accordance with the sampling frequency.

The output of the control signal generation circuit 115 is sent to the decoder 14
8, and the output of the decoder 148 is connected to a selector switch circuit S'l that selects one of the outputs of the low-pass filters 146-1 to '146-3 and the low-pass filter 1.
47-1 to 147-3, and is supplied to a uJ switching circuit S'2 that selects one of the outputs of 47-1 to 147-3, and low-pass filters 146-1 to 146-l are supplied to the uJ switching circuit S'2, which selects one of the outputs of 47-1 to 147-3.
Select the output of 46-3 and apply the low-pass filter 147-
Select output from 1 to 147-3.

νJ 4−+The outputs of the switch circuits S' and S'2 are supplied with a gain Et (variable/Hetuffer amplifiers 149 and 150, respectively) whose gain is switched according to the sampling frequency identification code by the decoded output of the decoder 148. The signal is supplied, amplified, and then supplied to the output terminals OL and OR of the left and right channels.

In addition, the D/A converters 142 and 143 receive the output of the control signal generation circuit 115 and receive the output of the control signal generation circuit l15 at a sampling frequency of 32kHz.
The output of the non-transmission bit setter is supplied, which sets the lower two hits of the PCM code to 0'' when the output corresponds to .

On the other hand, the first transmission bit setters 151 and 152 receive the output of the control signal generation circuit 115 and set the output of the control signal generation circuit 115 to the sampling frequency 32.
When the output corresponds to kHz, this is a setting device for making the first two pitches of P'CMf and i equal to 0 when correcting an error in the error circuit 156.

(Operation of the Invention) In one embodiment of the present invention configured as described above, the operation will be explained by setting the number of words Nw of the frame to 8 words I and the PCM code track to 12 tracks as described above.
do.

First, the recording system will be explained.

At the time of recording, the sampling frequency instruction and sub-code instruction are set to H by the key switch 15, and the system control circuit 14! /J8 switch circuit 31, S
2. Compatible with sampling frequency! , lJ signal is output and the changeover switch circuits Sl and S2 correspond to the sampling frequency! , IJ J + erare.

Ru. Therefore, even if the sampling frequency is changed, aliasing noise will not occur. System control circuit 14
Also, the buffer amplifier 5.6 has a gain corresponding to the sampling frequency? +! The switching signal is output to the buffer amplifier 5.
．． The gain of 6 is switched according to the sampling frequency. Therefore, the low-pass filter 3-1.3-2.3
．． -3, the difference in loss between low-pass filters 4-1.
The difference in loss between 4-2.4-3 will be compensated.

On the other hand, a mask oscillator 16 receives a control signal determined corresponding to the sampling frequency from the system control circuit 14.
generates an output with a frequency corresponding to the sampling frequency, and upon receiving this oscillation output and a control signal from the system control circuit 14, the tape running reference signal generator 18 generates a tape running reference signal with a frequency proportional to the sampling frequency. do.

This tape running signal fI'2'q is amplified by the semi-transparent amplifier 26, and then supplied to the magnetic head 40-18 and recorded on the magnetic tape.

On the other hand, when recording, the playback/recording switch 28-1
．． 28-2 is switched to the contact position shown in FIG. The speed reference voltage generator 153, which receives the control signal from the system control circuit 14, outputs a speed reference voltage corresponding to the sampling frequency.

Further, the output of the pulse generator 154 is supplied to the comparator circuit 41 via the reproducing/recording switch 28-2 and also to the frequency-voltage converter 155. Initially, the magnetic tape 46 is not running, so there is no human power or output voltage from the frequency-voltage converter 155 on one side of the comparator circuit 41, the output of the servo amplifier 42 is maximum, and the capstan motor 44 is driven at maximum torque. The magnetic tape 46 is then run. Due to this running, the pulse generator 15
4 generates an output pulse, and the output of the pulse generator 154 is supplied to the comparison circuit 41 and compared in phase with the output of the tape running reference signal generation circuit 102.
The output frequency of 4 is converted into a voltage by a frequency-voltage converter 155 and supplied to the servo amplifier 42, and the difference voltage with respect to the output voltage of the speed reference voltage generator 153 and the output of the phase comparator 41 are added. The signal is amplified by the servo amplifier 42, and the servo motor 44 drives the magnetic tape 46 at a running speed corresponding to the sampling frequency.

On the other hand, the left and right channel analog audio signals supplied to the input terminals INL and INR are amplified by buffer amplifiers 1 and 2, and low-pass filters 3-1 to 3-3.4-1
~4-3, and the high range is limited in accordance with the sampling frequency. Low pass filter 3-1 to 3-3
, and the outputs of the low-pass filters 4-1 to 4-3, one output of each is selected by the switching circuits S1 and S2 in accordance with the sampling frequency, and is amplified by the buffer amplifier 7.8. In this case, the gain of the buffer amplifier 7.8 corresponds to the sampling frequency,
The difference in loss between low-pass filters 3-1 to 3-3 and the difference in loss between low-pass filters 4-1 to 4-3 are compensated.

The output of the buffer amplifier 5.6 is supplied to a sample and hold circuit 7.8 where it is sampled and held using a sampling pulse of a frequency designated by the key switch 15. The outputs of the sample-and-hold circuits 7.8 are converted into PCM codes by A/J converters 9 and 10, respectively, and stored in the data circuit 13. Memory circuit 1
The PCM codes stored in PCM codes 11 . The Q test word generation circuit 12 is loaded with the P test word and the Q test word after calculation, and is stored in the storage circuit 13. When the number of non-transmission bits of the PCM code is specified by the key switch 15, the non-transmission bit is "o°". This control circuit 23.24
controls the non-transmission bit to 0° in the generation of the P check word and the Q check word, respectively, and calculates the P check Q-1 and Q check words, and the PCM? The non-transmission bit in case a is controlled to 0'''.

The PCM code stored in the circuit 13 is interleaved, read out, and supplied to the demultiplexer 25.
It is supplied to recording units 30-1 to 30-12. Memory circuit 1
The P check word and the Q check word read out from No. 3 are supplied to the demultiplexer 25, and then supplied to the recording sections 30-13 and 30-14, the recording sections 30-158 and 3O-+8.

On the other hand, the sibling frequency detection code generator 19 receives a control signal corresponding to the sampling frequency specified by the key switch 15 from the system control circuit 14 and outputs an identification code corresponding to the sampling frequency, and this identification code is an error signal. The signal is supplied to a correction code generation circuit 21, an error correction code is added thereto, and the signal is supplied to a selector 22. Further, the sub-code generating circuit 20 receives a control signal specified by the key switch 15 from the system control circuit 14, generates a sub-code, and the sub-signal is supplied to the selector 22.

The identification code and sub-code with the error correction code added to them supplied to the selector 22 are selected by the selector 22 and stored in the storage circuit 13, and are added with the error correction code read out from the storage circuit 13. and the sub-code are supplied to the demultiplexer 25, and supplied by the demultiplexer 25 to the recording section 30-17.

A frame synchronization code and a CRC code are added to the codes supplied to the recording units 30-1 to 30-17, and a predetermined value is obtained. 1st
In the table, W is the PCM code for the left channel analog signal, W is the PCM code for the right channel analog signal, P is the P test word, Q is the Q test word, B is the sampling frequency identification code, and S is the PCM code for the right channel analog signal. In addition, the timing pulse generator 17 receives the control signal from the system control circuit 14 and the oscillation output of the mask oscillator 16 and generates various timing pulses corresponding to the sampling frequency. D converter 9 and lo, P check word generation circuit 11
, Q check word generation circuit 12, fortune-telling address generation circuit and readout address generation circuit of the memory circuit 13, multiplexer 25, and CRC code generation circuits 31-1 to 31.
-17, frame l, synchronization code generation circuit 32-1 to 32-
17. Selectors 33-1 to 33-17, modulator 34-1
~34-17, Sampling frequency identification code generation circuit 1
9. Sub code generation circuit 20, error correction code generation circuit 2
1. Since the sample link pulse is supplied to the selector 22 and the sample-and-hold circuits 7 and 8, signal processing is performed at a signal processing speed according to the designated sampling frequency.

Here, even if the designation of the sampling frequency by the key switch 15 is changed, the magnetic tape 46 is driven at a running speed corresponding to the newly designated sampling frequency. Also, low-pass filters 3-1 to 3-4,
Low pass filters 4-1 to 4-4, buffer amplifier 5.
The gain of 6 corresponds to the newly specified sampling frequency! Sample and hold circuit instead of ilJ 7.
8 samples and holds the output of the buffer amplifier 5.6 using a sampling pulse of a newly designated frequency. Furthermore, a tape running reference signal 15 proportional to the newly specified sampling frequency is recorded on the magnetic tape 46 by the magnetic head 40-18. On the other hand, A
/D converters 9 and 10. P check word generation circuit 11.
Q check word generation circuit 12, write address generation circuit and read address generation circuit of recording circuit 13, multiplexer 25, CRC code generation circuits 31-1 to 31-
, +7, frame synchronization code generation circuits 31-1 to 32-
7. Selectors 33-1 to 33-17. Modulator 34-1~
3'4-1? , sampling frequency identification code generation circuit 1
9. The sub-code generation circuit 21 and the selector 22 are operated by various timing pulses corresponding to the newly specified sampling frequency output from the timing pulse generator 17, so the sub-code generation circuit 21 and the selector 22 are set to the recording format shown in Table 1. Since there is no change and there is no change in the minimum recording wavelength, there is no problem with recording and reproduction.

In addition, in the case of the recording format shown in Table 1, when the sampling frequency is fsl = 48 kHz, l rasec worth of PCM codes are stored in l frame, and fs
2-160/14 for 175-m at 44.1kHz
The PCM code for 7m5ec is fs3 = 32k)
In the case of IZ, one frame stores PCM codes for 1.5m5ec.

Next, the operation of the ++r generation system will be explained.

When switching to +rf playback, that is, when instructing playback using the key switch 15, +l is sent to the system control circuit 14.
r student instructions are given. Ill raw recording switch 28
-1 to 28-3 are switched from the playback example, that is, the contact positions shown in FIG.
The reproduction instruction output No. 5 is supplied to the control circuit 116, and a reproduction instruction is issued. At this point, the magnetic tape 46 has not yet been driven.

From the control circuit 116 to which the reproduction instruction was issued, the reproduction instruction pulse is output to the OR circuits 115-9 to 115-11°115-2.
2 and at the same time sampling frequency 44.1
An identification code corresponding to kHz is forcibly supplied to the switch circuit 115-15 for a predetermined period (tl). The former reproduction instruction pulse causes the counters 115-1 to 115-3, 1 to
15-17. The latch circuit 115-8 is reset,
The latter identification sign is detected by the rising-1 edge detection circuit 114-4, and the detection output is used to control the counter 114-1-114.
-3 is reset (step a in FIG. 5). Further, the latter identification code is output as the output of the control signal generation circuit 1'15 via the switch circuit 115-15.

This output is supplied to the tape running reference signal generation circuit 102 in place of the control signal of the system control circuit 14, and is also supplied to the speed reference voltage generator 153 via the reproduction/recording changeover switch 28-1.
At the same time, it is supplied to the mask oscillator 16 in place of the control signal of the system control circuit 14. As a result, the mask oscillator 16 oscillates at a frequency corresponding to the Kempling frequency corresponding to the sampling frequency identification code. The tape running reference signal generation circuit 102 receives the output of the control signal generation circuit 115 and the oscillation output of the mask oscillator 16, and generates an output with a frequency corresponding to the sampling frequency, and receives the output of the control signal generation circuit 115 and generates a speed reference signal. Generator 153 generates a voltage output corresponding to the sampling frequency. However, the capstan motor 44 is stopped and rotates +1 while the tape runs ', 1.
The quasi-signal reproducing circuit 101 also does not generate any output. This is a state in which the signal from the pulse generator 154 of recording 11'1 is replaced with the output of the reference signal reproducing circuit lot.
As in the case of starting recording, the capstan motor 44 is driven to rotate at maximum torque, and the AI tape 46 starts running. As the capstan motor 43 is rotationally driven, the tape running reference signal reproducing circuit 101 is activated by the magnetic herad 5.
0-18 amplifies the detected output and generates a reproduced output. The output of tape running reference signal reproducing circuit 101 is supplied to comparator circuit 41 and frequency-voltage converter 155 via switch 28-2. As a result, the capstan motor has a phase period at the output of the tape running reference signal generation circuit 102, and an output voltage and frequency of the speed reference voltage generator 153.
The capstan motor 44 is always driven to rotate at a rotational speed corresponding to the controlled sampling frequency so that the difference with the output of the voltage converter 155 always converges to zero. Furthermore, even if the control signal generator 115 generates an output of a different sampling frequency identification code, the capstan motor 44 rotates at a rotation speed corresponding to the content of the sampling frequency identification code, and the magnetic tape 46 rotates at the sampling frequency identification code. The vehicle travels at a speed corresponding to the vehicle.

Therefore, following step a, the magnetic tape 46 is driven at the running speed of the magnetic tape 46 at a speed corresponding to the period t1 sampling frequency fs2 = 44.1 kHz (step b). The waveform equalization circuit 105 outputs the amplified signal at the sampling frequency @44. The waveform shaping circuit is equalized in response to the contents of the Ikllz identification code.

At 106, the waveform is shaped. Here, the equalizer amplifier 105-1 is a circuit that flattens the frequency characteristics of the required frequency occupied band of the signal supplied from the amplifier 104,
Pulse slimming circuit 105-2 is equalizer amplifier 1
The required occupied band of the signal supplied from the amplifier 104, which is a circuit that narrows the pulse width of the signal supplied from 05-1 to the required width, and the pulse width of the output signal of the equalizer amplifier 105-1 are determined by the sampling frequency. If they are different, the frequency characteristics of the equalizer amplifier and the delay time of the delay circuit constituting the pulse slimming circuit 105-2 are changed using the control signal from the control signal generation circuit 115 in accordance with the contents of the sampling frequency identification code. . The integration circuit 105-3 is provided because the characteristics of the magnetic tape during recording exhibit differential characteristics, and this is to compensate for the differential characteristics by integrating after pulse slimming. In addition, a DC regeneration circuit 1 is added to the waveform shaping circuit.
06-1 is provided in order to perform so-called DC level reproduction by comparing the DC levels of the positive half wave and negative half wave of the output signal of the integrating circuit 105-3.

In the waveform shaping circuit 106, the output of the waveform equalization circuit 105 is waveform-shaped by comparison with the DC reproduction circuit 106-1, so that even if there is a fluctuation in the DC level, the waveform is reliably shaped.

Bit synchronization detection circuit 10 from the output of waveform shaping circuit 106
7. A bit synchronization signal and a frame synchronization signal are detected by the frame synchronization detection circuit 108. Detection of the P and T synchronization signals is performed using a frequency divider 1 which divides the output edge of the waveform shaping circuit 106 and the output of the VCOI O7-3 as shown in FIG.
07-4 is detected by comparing the phase with the signal edge created from 07-4. Note that the free-running frequency of C0107-3 is switched by the sampling frequency identification code.

A bit synchronization signal and a frame period signal are provided,
The output of the waveform shaping circuit 106 is demodulated by a demodulator 109. This demodulated output is a sampling frequency identification code and a sub code, and is sent to an error correction circuit 112 for error correction [F
is supplied to the serial/parallel converter 113-1 to be converted into parallel data, and then sent to the data detection circuit 11.
3-2 to 113-3. Assuming that the demodulated sampling frequency identification code corresponds to a sampling frequency of 44.1kHz, an output is generated at the terminal Gll of the data detection circuit 113-2, and the counter 1
14-1 counts it at least once and generates an output α. The control circuit 116 that received the output α sends data at a sampling frequency fs2 = 44.1kHz for a predetermined period (
Step c)
, the control circuit 116 receives the output α for a predetermined period (
t2), a sampling frequency of 44.1 is applied to the tape running reference signal generation circuit 102 and the speed reference voltage generator 153.
The output of the sign corresponding to kHz is sent to the switch circuit 115-1.
5. - As a result, the speed of the magnetic tape 46 is for a predetermined period (t2), Fs2 = 44.1kll
is fixed at the tape running speed corresponding to z (step d
). When the counter 115-1 counts the identification code of sampling frequency %44.1kHz within this predetermined period (t2), the counter 115-1 generates an output. This output from the counter 115-1 causes the changeover switch circuit 5-5 to switch to output from the terminal G12 of the data detection circuit 113-2, that is, the sampling frequency 44.
The 1 kHz identification code is provided to latch circuit 115-8.

On the other hand, the output of the counter 115-1 is the OR circuit 115-10.
, 115-11 via counter 115-2.1
At the same time as resetting 15-3, OR circuit 115-
12 to delay circuits 115-13. In response to this, the delay circuit 115-13 outputs an OR circuit 11512.
A delay circuit 115-1 is included in the control circuit 116 that generates a signal delayed by a predetermined time from the signal supplied from the control circuit 115-1.
3 output signal is supplied and the sampling frequency is 44.1k.
It notifies that the Hz detection code has been detected N times (step e). The output of delay circuit 115-13 is latch circuit 1
The output from the terminal G12 of the data detection circuit 113-2, which is also supplied to the data detection circuit 15-8, is latched in the latch circuit 115-8. At the same time, the switch circuits 115-'14 and 1515 are switched by the output of the delay circuit 115-13, and the latch output of the latch circuit 115-8, that is, the identification code of the sampling frequency 44.111112 is replaced by the output from the control circuit 116. is supplied to the tape running reference signal generation circuit 102 and the speed reference voltage 153, and the magnetic tape running speed is determined at the sampling frequency fs2 = 4.
The speed is controlled to correspond to 4.1kHz (step f
).

On the other hand, the error detection output from the error correction circuit 112 is transmitted through the OR circuit 1i5-is.
5-20, low flip-flop 115-2
The output of 0 is counted by the counter 115-21 and Fs2
= 44.1kHz sampling frequency identification 9.
The number of corrections for No. 1 is monitored (step g). When the error detection output is detected M times, the counter 115-21 generates an output (step h), the output of the counter 115-21 is supplied to the control circuit 116 to stop automatic regeneration, and at the same time the counter 11'5-21 The output of is supplied to the automatic stop display circuit 117 to display automatic regeneration stop (step i). At the same time, the output of the counter 115-21 is output from the OR circuit 115-22. It is supplied to the Q2CH circuit 115-8 via the differentiation circuit 115-23, and the latch circuit 115-8
will be reset. On the other hand, when no error is detected by the error detection circuit 112 in step h, or until M times are detected, steps fh are repeated to control the running speed of the magnetic tape to a speed corresponding to the sampling frequency of 44.1 kHz.

Note that the above is a case where an identification code with a sampling frequency of 44.1 kHz is detected by the magnetic herad 50-17. If the identification code with a sampling frequency of 44.1 kHz is not detected by the magnetic field 50-17, it is determined from step C whether the identification code with a sampling frequency of 32 kHz is detected or the output of the counter 114-3 is detected (step C2). , sampling frequency 32kHz
When the identification code z is detected, step C2 is followed by steps d2, e2. f2, g2, h2, i are executed. This is similar to steps d, e, f, g, h, i. Further, if the identification code with a sampling frequency of 32 kHz is not detected at least once in step C2, or if the identification code with a sampling frequency of 44.1 kHz is not detected N times in step e, then step Following e, the running speed of the tape is set to a sampling frequency of 48kHz.
Step bl) to set a predetermined period (tl) to the speed corresponding to , el, fl, gl, i are executed. Sampling frequency 48kHz in step CI
When the identification code of 48 kHz is not detected once within the predetermined period (tl), or when the identification code with a sampling frequency of 48 kHz is not detected eight times within the predetermined period (t2) in step el, step CI or step el is performed.
Subsequently, the control circuit 116 generates a sampling frequency of 32k as the output signal of the control signal generation circuit 115.
Step b2) to output the code corresponding to Hz for a predetermined period (tl), and the sampling frequency 3 is output within the predetermined period (tl).
When the 2 kHz detection code is detected at least once (step j), step d2 is subsequently executed. If the identification code with a sampling frequency of 32 kHz is not detected even once in step j, or if the identification code with a sampling frequency of 32 kHz is not detected N times within the predetermined period (t2) in step e2, the process proceeds to step k. is executed. That is, the control circuit 116
The code corresponding to the sampling frequency of 32 kHz supplied from is detected by the pattern detection circuit 115-16,
It is counted by counters 115-17. counter 11
When the count value of 5-17 is 2''', that is, when the expected sampling frequency identification code is not detected even after repeating the turning operation twice, step i is executed and the counter 11
When the count value of 5-1.7 is less than "2", step 6 is executed again.

As described above, the running speed of the magnetic tape 46 is controlled,
Magnetic Herad 50-1? The speed is controlled to correspond to the contents of the sampling frequency identification code detected in the sampling frequency, that is, the sampling frequency.

The output of the control signal generation circuit 115 is transmitted to the waveform equalization circuit 105, the bit synchronization detection circuit 107. Mask oscillator 16
．． Since it is supplied to the timing pulse generation circuit 118, the frequency characteristics of the waveform equalization circuit 105, the -3 free running frequency of the VCO 107 of the PIP/synchronous detection circuit 107, the oscillation frequency of the mask oscillator 16, and the timing pulse generation circuit 118 The timing pulses output from the oscillator are switched in accordance with the sampling frequency.

Further, the output of the demodulator 109 is supplied to a sub-code decoder 119 and a CRC detection circuit 120 together with a bit synchronization signal and a frame synchronization signal, and the sub-code being output from the demodulator 109 is decoded by the sub-code decoder 119, and the decoded output is is placed in the sub-code register 122. Further, errors in the sub-code are detected by the CRC detection circuit 120, and the pointer set there is supplied to the CRC pointer register 121. The CRC pointer 121 sends a control signal to the sub-code register 122, and when a pointer exists in the CRC pointer register 121,
It is output from the sub-code register 122 before the pointer is set. Further, when there is no pointer in the CRC pointer register 121, the sub-code checked by the CRC detection circuit 120 is output from the sub-code register 122. Also CR
From the C pointer register 121, the error correction circuit 112
A control signal is also sent to the error correction circuit 11 when there is no pointer in the CRC pointer register 121.
If a pointer exists, a control signal is sent to the error correction circuit 112 to cause the error correction operation to be performed.

The bit period signal detected by the bit synchronization detection circuit 107 and the frame l detected by the frame period detection circuit 10B,
The timing pulse generation circuit 111 that received the same 111143 "t outputs various timing pulses corresponding to the bit period signal detected by the bit detection circuit 107,
The frame period detection circuit 108, the demodulator 109, the identification code detection circuit 11o, the error correction circuit 112, the code discrimination circuit 113, and the control signal generation circuit 115 operate in response to the bit synchronization signal detected by the bit synchronization detection circuit 107. I am made to do so.

-1 On the other hand, the code detected by the magnetic herad 50-18 is amplified by the amplifier 126-18, and the waveform equalization circuit 1
27-18, and the waveform equalization circuit 127-16
The output is waveform-shaped by the waveform shaping circuit 12B-18. The output of the waveform shaping circuit 428-18 is sent to the beat and synchronization detection circuits 129-16. Frame synchronization detection circuit 130-1
At 6, the bit synchronization signal and frame period signal are detected,
It is demodulated by a demodulator 131-18. Demodulator 131-18
The output of is stored in register 134-16. In addition, the output of the waveform shaping circuit 128-18 is checked for errors in a CRC detection circuit 133-16 for each frame.
I did an RC test. &'i When a result error is detected, a pointer is set and outputted to the register 134-16.

The pointer is in register l34-. Register 134-18 stores the CRC check in 1B along with the PCM code.
The N numerical value of is stored in the storage circuit 135-18 according to the address designation of the write address generation circuit 136-18. Further, the write address generation timing signal of the write address generation circuit 136-16 is supplied to the write priority instruction circuit 137-18, and is used when a read instruction is issued from the read address generation circuit 138 and when a write instruction is issued from the write address generation circuit 13B-18. When there is a conflict, writing takes priority.

Further, the timing pulse generation circuit 132-16 receives the bit synchronization signal detected by the bit synchronization detection circuit 129-IEI and the frame period signal detected by the frame synchronization detection circuit 130-16.
Various timing pulses corresponding to the bit synchronization signal detected in step 18 are output, and the frame synchronization detection circuit 130-1
[1, demodulators 131-113, CRC detection circuit 13
3-16. Register 134-1fi is operated in response to a bit synchronization signal, and write address generation circuit 1
36-IEi address signal is output.

Further, the functions of the regenerating sections 125-1 to 125-15 are similar to those of the regenerating section 125-1fl.

The read instruction signal generation circuit 139 receives the oscillation output of the mask oscillator 16 according to the content of the sampling frequency identification code, and supplies a read instruction signal to the read address generation circuit 13B.

Read address generation circuit 1 receiving read instruction signal
38, the read address is stored in the memory circuits 135-1 to 135-1.
35-18, storage circuit 135-1-135
The stored data of -18 is read out and written to the deinterleaving circuit 140. The data written to the deinterleaving circuit 140 is error-corrected by the error correction circuit 156, deinterleaved by the deinterleaving circuit 140, and then read out. When the deinterleaved PCM data cannot be corrected by the error correction circuit 156, it undergoes error correction by the error correction circuit 141. When there is no error or when the error can be corrected, the PCM code of the left channel sound is directly supplied to the D/A converter 142 and converted to an analog signal, and the PCM code of the right channel sound is sent to the D/A converter 143. and converted into an analog signal.

The analog signal output from the D/A converter 142 is supplied to a deglitcher 144, the analog signal output from the D/A converter 143 is supplied to a deglitcher 145 to remove glitches, and the output of the deglitcher 144 is supplied to a low-pass filter 146-. 1 to 146-3, and the output of the deglitcher 145 is supplied to the low-pass filters 147-1-147.
-3 is supplied. Low pass filter 14.6-1~1
The output of 4B-3 is changed to that 1 by the changeover switch circuit Sl'.
is selected, amplified by the buffer amplifier 149 and supplied to the output terminal OL, and the reproduced left channel audio signal is output. Low pass filter 147-1 to 147
One of the -3 outputs is selected by the ticket switch circuit S2', amplified by the buffer amplifier 150 and supplied to the output terminal OR, and the reproduced right channel audio signal is output.

- The output of the power and control signal generation circuit 115 is supplied to the Tecoator 148 and decoded, and the changeover switch circuits Sl' and S2' are switched by this decoded output.
The gains of buffer amplifiers 149 and 150 are controlled. That is, filter 146-1-146-3.147-1~
147-3 is switched in accordance with the sampling frequency of the PCM code recorded on the magnetic tape, and the high-frequency components of the analog signals converted by the D/A converters 142 and 143 correspond to the sampling frequency. In addition, the gains of buffer amplifiers 149 and 150 are also switched in accordance with the sampling frequency, and the difference in loss between low-pass filters 146-1 to 146-3 and the loss of low-pass filters 147-] to 147-3 are eliminated. The difference in loss is compensated.

Timing pulse generation circuit 11 receives the output of control signal generation circuit 115 and the output of mask oscillator 16
8 is a read instruction address generation circuit 138 which generates various timing pulses corresponding to the sampling frequency;
Read instruction signal generation circuit 139, deinterleave circuit 140, error correction circuit 156.0/A converter 142.
143, deglitchers 144, 145, and error correction circuit 141, the signal is processed at a signal processing speed according to the sampling frequency of the PCM code recorded on the magnetic tape 46.

In addition, the output of the control signal generation circuit 115 is supplied to the "0" set path 151.152 and the D/A converter 142.143, and if the non-transmission bit is determined in advance according to the sampling frequency, it corresponds to the non-transmission bit. Set the bit to “0”.

If the non-transmission bits are not determined in advance according to the sampling frequency, the control circuit 124 reads the code representing the number of non-transmission bits sent as a sub-code, and the control circuit 124 sets the code to ``0'' set circuit 151.152. Then, a control signal (not shown) is sent to the D/A converters 142 and 143, and the corresponding non-transmission bit is set to "0".

As described above, according to the present invention, the moving speed of the magnetic recording medium is configured to be variable, and the recording medium is recorded on the magnetic recording medium.
During recording, the running speed of the magnetic recording medium and the processing speed of the signal processing system are controlled according to the sampling frequency, without changing the number of words per trunk constituting a frame. Corresponding sampling frequency information is recorded, and during playback, the running speed of the magnetic recording medium +6° and the processing speed of the signal processing system are controlled according to the sampling frequency information recorded on the magnetic recording medium. Regardless, there is no need to provide multiple pairs of signal processing systems, and the minimum recording wavelength can be made almost the same, allowing good signal transmission.

Furthermore, since the same parity check system is used, the error correction capability can be made almost the same regardless of the sampling frequency.

In addition, it detects that the sampling frequency information is the same a predetermined number of times, and unless the detected sampling frequency information is incorrect more than the predetermined number of times or unless other sampling frequency information is detected, the magnetism is detected according to the former sampling frequency information. Since the running speed of the recording medium and the signal processing speed of the signal processing system are controlled, the sampling frequency information can be detected reliably, there is no false detection, and the [j+ production process does not become unstable.

Table 1

[Brief explanation of the drawing]

FIG. 1(al), FIG. 1(b) and FIG. 1(C) are block diagrams showing one embodiment of the present invention, and FIG. 1(al indicates a recording system, FIG. 1fb) and FIG. Figure 1 (C) shows the reproduction system. Figure 2 is a diagram of the equalization circuit and waveform shaping circuit in one embodiment of the present invention. 1. A block diagram of the synchronization detection circuit. Fig. 4 shows a block diagram of the code discrimination circuit, the detection number counter, and the detected roll signal generation circuit in one embodiment of the present invention.
diagram. FIG. 5 is a flowchart for explaining the operation of one embodiment of the present invention. 1.2, ]49 and 150.../...No7a amplifier,
3-1~3-3.4-1~4-3,146-+~146
-A and l 47-1 to 147-3...Rono (Swirk, 7 and 8-...Sample anode hold circuit, 9 and 10...A/D converter,] 1. and 1
2...P and Q! check word generation circuit, 13.135
-+~135-+6...Storage circuit, 14...System control l! 8] road, ■ too...mask oscillator, 17.1
11.118.132-1 to 132-16...Timing pulse generation circuit, 18...Tape running base signal generation circuit, 19...Sampling frequency identification code generation circuit, 20...Sub attaching generation circuit , 21...Error correction code generation circuit, 22.33-+~33-17...Selector, 25...Demultiplexer, 26.35-1~
35-16...aQ edge width device, 28-1 and 28-
2...Reproduction/recording switch, 30-1 to 30-17
...Recording section, 31-1 to 31-16...ORO code generation circuit, 32-t to 32-+7...Frame synchronization code generation circuit, 34-1 to 34-I? ...Modulator, 40-
1 to 40-+s and 50-1 to 50-+s...A company air conditioner, 41...Comparison cycle y11.42...Servo 112 width switch, 44...Capstan motor, 45.
...Capstan, 101...Tape running reference signal reproducing circuit, 102...Tape running reference signal generating circuit, 1
05.127-+~127-+6 ・・Waveform equalization circuit,
106.128-+~128-16... Waveform shaping circuit, 107,129-1~129-+s... Bi, 1.
Synchronization detection circuit, 108, 130-+ ~ 127-+6...
・Frame synchronization detection circuit, 109°131-1 to 131
-+6... Demodulator, 110... Identification code detection circuit,
113... No. 41 discrimination circuit, 114... Detection number counter, 115... Control signal F79a raw circuit,
116...Control circuit, 117--Automatic stop fire circuit, 136-+~127-+6--Write fuse generation circuit, 138...-Seepage address generation circuit,
139... Read instruction signal generation circuit, 140...
Differential leave circuit, 142 and 143...D/A
Converter, 153...Speed reference voltage generator, 154...
, pulse generator V-event, 155... frequency-mixture converter, 156... error correction circuit. Patent Applicant Trio Co., Ltd. Agent Patent Attorney Nobuo Sunako Procedural Amendment November 2, 1980 Commissioner of the Patent Office Kazuo Wakasugi 1, Indication of the Case Patent Application No. 178992, 1988 2, Name of the Invention Magnetic Recording and Reproducing Device 3. Relationship with the case of the person making the amendment Patent applicant address: 2-17-5 Shibuya, Shibuya-ku, Tokyo Name (359)
) Trio Co., Ltd. Representative Yoshi Ishizaka 4, Agent 107 Telephone 498-1587 Address 5-9-15 Minami-Aoyama, Minato-ku, Tokyo, Japan 7, Details of the amendment Figure 1 (a), 1 of the drawing Figure (b), Figure 1 (C), Figure 2, Figure 3, Figure 4, and Figure 5 will be corrected as attached (drawn on tracing vapor without content rC changes). Above procedural amendment dated October g, 1930, Commissioner of the Patent Office Shiga, school age 1, Indication of the case, Patent Application No. 178992, filed in 1982, 2, Title of the invention: Magnetic recording and reproducing device 3, Person making the amendment Relationship to the case Patent application Person Address: 2-17-5 Shibuya, Shibuya-ku, Tokyo Name (359)
) Trio Co., Ltd. Representative Yoshi Ishizaka 4, Agent Address 7-9-15 Minami-Aoyama, Minato-ku, Tokyo 107-498-1587 Address: 7, Contents of amendment Figures 1 (b) and 4 of the drawing Correct the diagram as attached. that's all

Claims (1)

[Claims] l) In a magnetic recording/reproducing device that converts analog garbled data into CM codes and records them on a magnetic recording medium, detects the recorded POM code, and reproduces them into an analog/pg signal, the number of tracks and frames to be recorded on the magnetic recording medium are configured. When recording, the running speed of the magnetic recording medium and the signal processing speed of the signal processing system are controlled according to the sampling frequency. Sappling frequency information corresponding to the sampling frequency and running speed reference information of the magnetic recording medium are recorded in the recording medium, and it is detected that the sampling frequency information detected from the magnetic recording medium during reproduction is the same a predetermined number of times; According to the detected sampling frequency information, the running speed of the magnetic recording medium and the signal of the signal processing system are determined as long as the detected sampling frequency is not erroneous by more than a predetermined number of times, or unless other sampling frequency information is detected a predetermined number of times. A magnetic recording/reproducing device characterized in that the processing speed is controlled.