JPH03181072A - Digital signal processor - Google Patents

Abstract

PURPOSE:To perform read after write with a simple constitution by not only stopping the output operation of reproduced data but also outputting the error detection result of reproduced data by a reproduced signal processing circuit. CONSTITUTION:A reproduced signal processing circuit 34 is provided with output stopping means 48, 58, 60, and 64 which stop the output operation of reproduced data DPB and an error detecting means 68 which detects error of reproduced data DPB. At the time of recording, the detection result of the error detecting means 68 is outputted and the output of reproduced data DPB is stopped. In this manner, the reproduced signal processing circuit 34 not only stops the output of reproduced data DPB but also outputs the detection result of the error detecting means 68 at the time of recording. Consequently, it is unnecessary to independently provide signal processing circuits of recording and reproducing systems. Thus, read after write is performed with the simple constitution.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Outline of the invention C. Conventional technology Problems to be solved by the invention E. Means for solving the problems (Figs. 1, 2, and 4) 1. Effects (1. 2 and 4) G Example (Figs. 1 to 4) (Gl) First Example (Gl-1) Structure of Example (G2) Operation of Example (G3) Implementation Effects of Example (G4) Other Embodiments H Effects of the Invention A Field of Industrial Application The present invention relates to a digital signal processing device, and can be applied to, for example, an external storage device of an arithmetic processing device.

B. Summary of the Invention The present invention provides a digital signal processing device that, when recording,
By operating the reproduced signal processing circuit in a state where output of reproduced data is stopped, read-after-write can be performed with a simple configuration.

C. Prior Art Conventionally, some magnetic recording and reproducing apparatuses (hereinafter referred to as digital audio recorders) are capable of recording and reproducing digital audio signals using a rotating drum.

In such a digital audio chip recorder, an analog audio signal is converted into a digital signal and recorded and played back, and at this time, the digital signal is subjected to error detection and correction processing before being played back, which effectively avoids sound quality deterioration. As a result, audio signals can be recorded and reproduced with high density.

D Problems to be Solved by the Invention By the way, if a digital audio chip recorder records serial data instead of digital audio signals, it can be used as an external storage device for an arithmetic processing unit, for example, and can be used as an external storage device with a large storage capacity. You can get the equipment.

In this case, in the external storage device of the arithmetic processing unit, it is necessary to reliably prevent the occurrence of errors during recording and reproducing, so it is necessary to check whether the input data has been reliably recorded or not by reproducing the data while recording. A so-called read-after-write function is required to confirm this.

However, in order to obtain such a door after-write function, it is necessary to separately provide a recording system signal processing circuit and a reproduction system signal processing circuit, which poses a problem in that the overall configuration becomes complicated.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a digital signal processing device that can obtain a read-after-write function with a simple configuration.

E Means for Solving the Problem In order to solve this problem, the present invention uses a memory circuit 13. During recording, the input data DIKc is divided into blocks at a predetermined period and output to the memory circuit 13, and during reproduction, A data input/output circuit 16 reads and outputs the reproduced data DPI stored in the memory circuit 13, and generates an error detection and correction code for the input data I)■e stored in the memory circuit 13 during recording and performs error detection. The correction code is stored in the memory circuit 13.
An error detection and correction circuit 20 detects and corrects errors in the reproduced data D□ stored in the memory circuit 13 during playback and outputs the error detection data D□ to the memory circuit 13 during recording, and an error detection and correction circuit 20 detects and corrects errors in the reproduced data D □, and a recording signal generation circuit 22 that converts the error detection and correction code into a recording signal S□ and outputs it.
, recording heads 26A, 26B that output a recording signal S□0 to the magnetic tape 15 during recording, and recording head 26A.
, 26B, which scan the magnetic tape 15 and output the reproduced signal S□, and the memory circuit 1 which demodulates the reproduced signal SIF and outputs the reproduced data DFll.
The reproduced signal processing circuit 34 includes an output stop means 48, 58, 60, 64 for stopping the output operation of the reproduced data DPI, and an error detection circuit for detecting an error in the reproduced data DPI. It has a detection means 68, and during recording, it outputs the detection result of the error detection means 68 and stops outputting the reproduced data DPI.

During F action recording, the playback signal processing circuit 34 outputs the playback data D.
By stopping the output of the PI and outputting the detection result of the error detection means 68, read-after-write can be performed without separately providing a recording and reproducing system.

G example Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

(G1) First embodiment (Gl-1) Structure of the embodiment In FIG. 1, 1 indicates a data recorder as a whole, which is used as an external storage device of an arithmetic processing device to record data DATA of the arithmetic processing device. Reproduce.

That is, in the data recorder 1, the system control circuit 2 generates control data and sends it to the digital signal processing circuit 4.
By outputting the data to the servo circuit 6, the data recorder 1 is set to a desired operation mode in response to a request from the arithmetic processing unit.

As a result, the servo circuit 6 drives the rotating drum 8 and the magnetic tape at a predetermined speed in the recording/reproducing mode.

Further, during recording, the system control circuit 2 inputs data DATA from an arithmetic processing device (not shown) via the interface circuit 8 and temporarily stores it in the memory circuit 12.
The data is sequentially outputted to the digital signal processing circuit 4 at a predetermined timing, thereby sequentially recording the data DATA on the magnetic tape.

On the other hand, during playback, the system control circuit 2 temporarily stores the playback data DPI output from the digital signal processing circuit 4 in the memory circuit 13, and then stores it in the memory circuit 13 in response to a request from the arithmetic processing unit. The processed data is output to the arithmetic processing unit via the interface circuit 8.

Further, during recording, the system control circuit 2 detects a read-after-write result based on the error detection data SYMN output from the digital signal processing circuit 4, and based on the detection result, the system control circuit 2 outputs the recording data D to the digital signal processing circuit 4.
aEC is re-outputted, and as a result, data D
It is designed to ensure that ATA is recorded.

As shown in FIG. 2, the digital signal processing circuit 4 is composed of a digital signal processing circuit used in a normal digital audio recorder. Instead of the signal 1) mu, recording data D□ input to the data input/output circuit 16 is recorded.

That is, in the digital signal processing circuit 4, the input/output circuit 18 converts the AES/EBU format digital audio signal RX into a predetermined format digital audio signal and outputs it to the digital signal input/output circuit 14. By converting the digital audio signal output from 14 into the AES/EBU format digital audio signal TX and outputting it, the AES/EBU format digital audio signals RX and TX can be recorded and played back. In this case, the operation is stopped based on control data.

The digital signal input/output circuit 14 sequentially counts predetermined clock signals with a built-in counter circuit, thereby
A rotating drum reference signal DREF with an interleave period of 30 [-5 ec] is created.

Furthermore, during recording, the digital audio signal DAIJ input via the input/output circuit 18 or directly is divided into blocks at an interleaving period and stored in the memory circuit 13, whereas during playback, the digital audio signal DAIJ is stored in the memory circuit 13. 13 is sequentially loaded and output, and in this embodiment, the input/output operation of the audio data is stopped based on control data.

The data input/output circuit 16 is connected to the system control circuit 2 during recording.
After blocking the recording data D□ output from the memory interface circuit 10 at an interleaving period,
At this time, the count value of the digital signal input/output circuit 14 is used as address data to record data D□.

It is designed to perform interleaving processing.

As a result, during recording, audio data is stored in block units in the memory circuit 13 when the digital signal processing circuit 4 is used in an audio tape recorder, whereas in this embodiment, the data input/output circuit 16 is stored in the memory circuit 13. The recording data D□ inputted via the audio data is stored instead of the audio data.

On the other hand, at the time of reproduction, the data input/output circuit 16 outputs the reproduction data D By loading, deinterleaving processing is performed.

As a result, during playback, the digital signal processing circuit 4 can sequentially output digital audio signals via the digital signal input/output circuit 14 when the digital signal processing circuit 4 is used in an audio tape recorder. In the embodiment, the reproduced data DPI is sequentially outputted via the data input/output circuit 16.

An error detection and correction circuit (ECC) 20 detects recording data DllI stored in the memory circuit 13 via the memory interface circuit 10 and the data bus DTsus during recording.
Parity codes (i.e., C1 and C2
After generating the parity code), the parity code is stored in the memory circuit 13.

On the other hand, during reproduction, the error detection and correction circuit 20 sequentially loads the reproduction data DP11 stored in the memory circuit 13, performs error detection and error correction on the reproduction data D□, and stores the resultant data in the memory circuit 13. .

In other words, the error detection and correction circuit 20 is configured in advance by the memory circuit 13.
After error-correcting the reproduced data D□ using the 01 code based on the error detection result using the C1 code stored in being done.

This allows the corresponding digital signal processing port! ! For the entire I4, error correction processing is repeated twice to reduce bit errors.

The recording signal generation circuit 22 generates recording data D□ stored in the memory circuit 13 during recording. and its parity codes are sequentially loaded and 8-IO modulated.

Further, the recording signal generation circuit 22 converts the modulation signal into serial data, adds a pilot signal for racking control (ATF), a synchronization signal, etc., and generates a recording signal S□. generate.

At this time, the recording signal generation @lR22 generates the recording signal Sl! at the timing when the recording magnetic heads 26A and 26B scan the magnetic tape based on the rotating drum reference signal DREF and the switching pulse signal SWP. . Output.

Thus, the recording signal S□ is produced using the digital signal processing circuit 4 for the digital audio chip recorder. By generating the data D□, it is possible to record the recording data D□ according to the recording format of the digital audio chip recorder.

On the other hand, during reproduction, the recording signal generation circuit 22 stops generating the recording signal S0C based on the control data.

During recording, the recording/reproducing amplifier circuit 24 amplifies the recording signal S□ and outputs it to the recording magnetic heads 26A and 26B, and also amplifies the reproduction signal 5IIF output from the reproducing magnetic heads 28A and 28B. The recording signal S□ is output to the clock signal extraction circuit 30 during playback. stop the amplification operation.

Here, the magnetic heads 26A to 28B read the magnetic tape at 90°.
Magnetic heads 26A and 26B, which are arranged at angular intervals of 90 degrees on the rotating drum 9 in a wound state and are opposed to each other by 180 degrees, are used for recording.

On the other hand, the remaining magnetic heads 28A and 28B are used for reproduction and are set to run on recording tracks trailing the recording magnetic heads 26A and 26B.

In this way, by sequentially outputting the recording signal S0° to the recording magnetic heads 26A and 26B via the recording/reproducing amplification circuit 24, it is possible to sequentially record the recording data D0°, and further to output the recording signal S0° to the recording magnetic heads 26A and 28B. A reproduced signal S□ immediately after recording can be obtained through the recording.

At this time, as shown in FIG. 3, the servo circuit 6 controls the drum motor to generate the rotating drum reference signal DRE.
F (Fig. 3(A)) and switching pulse signal sw
The rotating drum 9 is rotationally driven so that the rotational drum reference signal DR (FIG. 3(B)) is phase-synchronized.
After supplying the recording signal S□ (FIG. 3(C)) in 1 to 4 cycles of EF, the recording signal S□ is supplied in the following 1 to 4 cycles delayed by one cycle. Regenerated signal 5IF (Figure 3 (D))
(corresponding signals are shown with the same numbers).

The clock signal extraction circuit 30 is connected to the recording/reproducing amplification circuit 24.
A reproduced clock signal is extracted from the reproduced signal SIF obtained via the reproduced signal SIF, and the reproduced clock signal is outputted to the reproduced signal processing circuit 34 together with the reproduced signal SIF.

The reproduced signal processing circuit 34 demodulates the reproduced signal SIF by 10-8 based on the reproduced clock signal, and then outputs the resulting reproduced data DFJ to the memory circuit 13.

That is, as shown in FIG. 4, in the reproduced signal processing circuit 34, the synchronizing signal detection circuit 40 extracts the synchronizing signal from the reproduced signal S0 and outputs it to the 10-8 demodulation circuit 42 and the control circuit 4.
Output to 4.

The 10-8 demodulation circuit 42 demodulates the reproduced signal 5IIF based on the reproduced clock signal to create reproduced data D□.

The address data generation circuit 46 sequentially counts the reproduced data D□ and generates address data for storing the reproduced data D□ in the memory circuit 13 based on the address data included in the reproduced data Dpa. , address data D& generated via the tri-state buffer circuit 48. is output to the address bus ADmus.

On the other hand, the register circuits 50 and 52 are connected to the control circuit 4.
By taking in the playback data D□ based on the control signal output from the tri-state buffer circuit 58. 60 to the data bus DTmus.

The control circuit 44 creates an operation reference signal for the reproduced signal processing circuit 34 based on the reproduced signal SIF, and outputs a write request signal REQ to the memory circuit 13 via the gate circuit 64.

Buffer circuits 48, 58 and 60 receive switching signal SE
By switching the operation mode based on L, the mode is switched to the output mode during playback, whereas the mode is switched to the high impedance mode during recording.

In response to this, the gate circuit 64 outputs a switching signal SEL.
Based on this, the write request signal REQ is output during reproduction, whereas the output of the write request signal REQ is stopped during recording.

As a result, in the memory circuit 13, during reproduction, based on the address data Dam output from the address data generation circuit 44 in response to the write request signal REQ,
The playback data D outputted from the register circuits 50 and 52 is stored in sequence, and when the digital signal processing circuit 4 is used in a digital audio recorder, the playback data D□ can be divided into audio data and sub data. In this embodiment, the reproduction data D of the recorded data Dc is stored separately in the memory circuit 13, and in place of the audio data and sub data.
PI can be stored.

Thus, during playback, since the buses DTsus and ADmus are exclusively used by the playback signal processing circuit 34, the error detection and correction circuit 20 operating for playback, and the data input/output circuit 16, the playback data DP stored in the memory circuit 13 is
In I, after error detection and correction processing is performed by the error detection and correction circuit 20, the data is outputted to the system control circuit 2 via the data input/output circuit 16, thereby reproducing the desired data recorded on the magnetic tape and processing it in the arithmetic processing unit. can be output to.

On the other hand, during recording, the buffer circuits 48, 58 and 60
By switching to the high-impedance mode, the recording signal generation circuit 22, the error detection and correction circuit 20 that performs recording operation, and the data input/output circuit 16 monopolize the buses DTmus and ADIL+, which allows the recording processing system and the reproduction system to Even in the digital signal processing circuit 4, which shares some circuits with the
II can be processed.

Furthermore, at this time, the reproduced signal SPI can be demodulated into the reproduced data D, while generating the recorded signal S□, without providing a separate recording/reproducing system, and the reproduced data DP! If the error 1 is detected in the reproduced signal processing circuit 34, a read-after-write function can be obtained, and a data recorder with a simpler configuration as a whole can be obtained.

That is, the error detection circuit 68 performs error detection on the reproduced data DPM using the CI code and outputs the error detection result to the memory circuit 13 during reproduction, whereas the error detection result without error is obtained during recording. The error detection data SYMN (FIG. 3(E)) whose logic level rises when the error is detected is output to the system control circuit 2.

Thus, in the system control circuit 2, by counting the rise of the logic level of the error detection data SYMN, it is possible to judge whether or not the recorded data Dmtc can be correctly reproduced, thereby obtaining a read-after-write result. I can do it.

Therefore, based on the count result, the recorded data D□,
By re-recording, data can be recorded reliably.

In this embodiment, since the data recorder is configured using the digital signal processing circuit 4 for a digital audio chip recorder, the recorded data DI! , and odor are recorded in the main data area and sub-data area, respectively, which are standardized for digital audio tape recorders.

Furthermore, at this time, since a parity code for error detection and correction was generated in the same way as when recording a digital audio signal, if all data is reproduced without errors by detecting errors with the C1 code, one interface It is possible to obtain error detection data SYMN whose logic level rises 144×2 times in one leave period.

Therefore, if a count value of 288 is obtained in one interleave period, it can be determined that data can be reliably recorded and reproduced.

Further, even if the count value is 288 or less, error-free reproduced data D0 may be obtained from the digital signal processing circuit 4 by repeatedly performing error correction in the error detection and correction circuit 20.

Therefore, in the system control circuit 2, when the count value is less than a predetermined value less than 288, the operation of the entire data recorder is switched to re-record the recorded data D□0, thereby ensuring that the recorded data It is designed to be able to record D□wa.

Thus, the buffer circuits 48, 58 and 60 and the gate circuit 64 constitute an output stop means for stopping the output operation of the reproduced data D□.

(G2) Operation of the embodiment In the above configuration, in the digital signal processing circuit 8, the memory interface circuit 10, the data input/output circuit 16, the digital signal input/output circuit 14, the reproduction signal processing circuit 34, the recording signal generation circuit 22, and the error The detection and correction circuit 20 switches its operation based on the control data stored in the memory circuit 13, and during recording, the detection and correction circuit 20 switches the operation based on the control data stored in the memory circuit 13, and during recording, the memory interface circuit 10, the data input/output circuit 16, and the reproduction signal processing circuit 3.
4. The recording signal generation circuit 22 and the error detection and correction circuit 20 operate in recording mode.

As a result, the recording data DIIC input via the data input/output circuit 16 is divided into blocks at the interleave period, and then interleaved and stored in the memory circuit 13 sequentially in blocks.

A parity code is created for the recording data DIIEc stored in the memory circuit 13 in an error detection and correction circuit 20, and the parity code and the parity code are converted into a recording signal SOC in a recording signal generation circuit 22.

The recording signal S REC is sent to the recording magnetic heads 26A and 2.
6B, so that recording data D□0 can be sequentially recorded.

At this time, a reproduced signal S□ is obtained from the reproducing magnetic heads 28A and 28B that follow the recording magnetic heads 26A and 26B, and the reproduced signal SIF is reproduced by the clock signal extraction circuit 30 and the reproduced signal processing circuit 34. Ru.

At this time, in the reproduced signal processing circuit 34, the bus DTs
Since the output operation of the reproduced data DP11 to us is controlled to stop, the error detection result SYMN of the reproduced data DPI
Only the read-after-write result is output to the system control circuit 2, thereby making it possible to detect the read-after-write result.

(G3) According to the above effects of the embodiment, the output operation of the reproduced data D□ is stopped in the reproduced signal processing circuit 34, and the error detection result of the reproduced data D□ is obtained in the reproduced signal processing circuit 34. As a result, a read-after-write function can be obtained without separately providing a recording/reproducing system, and a data recorder with a correspondingly simpler configuration can be obtained.

(G4) Other Embodiments In the above-described embodiments, the case where the reproduction signal processing circuit simply obtains the error detection result of the reproduction data D□ is described, but the present invention is not limited to this. A counter circuit may be provided and the read-after-write result may be determined by the reproduced signal processing circuit.

Further, in the above-described embodiments, a case has been described in which a data recorder is configured using a digital signal processing circuit for recording and reproducing audio signals, but the present invention is not limited to this, and can be applied to a digital signal processing circuit dedicated to a data recorder. You may.

Further, in the above-described embodiment, a case was described in which the present invention was applied to an external storage device of an arithmetic processing device, but the present invention is not limited to this, but can be widely applied to digital signal processing devices that record and reproduce various data. .

H Effects of the Invention As described above, according to the present invention, by stopping the output operation of the reproduced data in the reproduced signal processing circuit and obtaining the error detection result of the reproduced data, it is possible to eliminate the need for a separate signal processing circuit for the recording/reproducing system. However, a read-after-write function can be obtained, and a digital signal processing device with a simpler configuration can be obtained.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a data recorder according to an embodiment of the present invention, Fig. 2 is a block diagram showing a digital signal processing circuit, Fig. 3 is a signal waveform diagram for explaining its operation, and Fig. 4 is a reproduction FIG. 2 is a block diagram showing a signal processing circuit. 1...Data recorder, 2...System control circuit, 4...Digital signal processing circuit,
12.13...Memory circuit, 16...
Data input/output circuit, 20...Error detection and correction circuit, 22...Record signal generation circuit, 34...
・Reproduction signal processing circuit, 48.5 days, 60...Buffer circuit, 64...Gate circuit, 68...
...Error detection circuit.

Claims (1)

[Scope of Claims] A memory circuit; and a data input/output circuit that blocks input data at a predetermined period and outputs it to the memory circuit during recording, and reads and outputs the playback data stored in the memory circuit during playback. and, when recording, generates an error detection and correction code for the input data stored in the memory circuit, outputs the error detection and correction code to the memory circuit, and when playing back, generates an error detection and correction code for the input data stored in the memory circuit; an error detection and correction circuit that detects and corrects errors in data and outputs the data to the memory circuit; and a recording signal that converts the input data and the error detection and correction code stored in the memory circuit into a recording signal and outputs the same during recording. a generation circuit; a recording head that outputs the recording signal to a magnetic tape during recording; a reproduction head that follows the recording head to scan the magnetic tape and output a reproduction signal; a reproduced signal processing circuit that demodulates and outputs the reproduced data to the memory circuit, the reproduced signal processing circuit comprising: output stopping means that stops outputting the reproduced data;
comprising error detection means for detecting errors in the reproduced data;
A digital signal processing device characterized in that, during recording, the detection result of the error detection means is outputted and the output of the reproduced data is stopped.