JPS62114165A - Digital audio signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To reduce an error data number by sectioning a digitized audio signal into blocks and recording the signal while an address signal and an error detection/correction code are added so as to make the titled device suitable for the case even when number of blocks in a field is not constant. CONSTITUTION:A digital data sent from an A/D converter 6 on a bus line 14 is stored in a RAM 15. The data stored according to a prescribed rule is selected, sent again to a bus, fetched by an error correction circuit, where an error correction code is generated. An address signal representing the timewise relative relation with other block with respect to one data group (block) is sent to an error correction circuit 20 at the same time, where the signal is restored to the original data generating an error correction code together with the data itself and the result is fetched in the RAM 15. Then a data read address from the RAM is designated by a prescribed timing and the corresponding data and error correction code are sent again on the bus 14, the parallel data on the bus 14 is converted into a time series serial data by a parallel/series conversion circuit 23. Further, the data is arranged by a selection circuit 27.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a device for recording and reproducing digitized audio signals using an image signal magnetic recording and reproducing device using a rotary head, and particularly relates to a device for recording and reproducing digitized audio signals. 〇Regarding a digital signal recording method suitable for generating a more reliable error detection and correction code (Prior art) Conventionally, as a method for recording and reproducing digitized audio using a magnetic recording and reproducing device using a rotating head, There is a PCM recorder using a home VTR, and the specifications for this system are shown in the Japan Electronics Machinery Industry Association technical standard CPZ-105' Consumer PCM Encoder/Decoder (established September 1983). Furthermore, there is a rotary head digital audio tape recorder (R-DAT) for recording audio, and this method is as follows:
For example, there is a rotating head system. In either case, the digitized audio signal is grouped into a predetermined number of bits and recorded as one block, and if necessary, synchronization is used as a reference for signal detection for each block. A signal and an error detection and correction circuit are added, and together with these additional signals, one block is configured. When recording on a magnetic tape, a certain number of blocks are grouped together and recorded within a period of so-called one field (corresponding to one scan of a rotating head).

In conjunction with such recording and reproduction of digital signals, interleaving and dinterleaving of digital data are performed in both methods. In other words, digital data that is input in chronological order during recording is stored in memory once, and then read out from memory according to predetermined rules (interleaving), and according to the order in which it is read out, data for each block and then data for each field are formed. , recorded on tape. During reproduction, the audio signals are sequentially stored in the memory according to the order in which they were reproduced, then read out from the memory according to a predetermined rule (dinterleave), and subjected to digital-to-analog conversion to obtain the original audio signal. However, in the above process, due to tape dropouts, noise contamination during playback, etc., the data that should originally be played back is not input to the memory, and the data order may be incorrect when rewriting it to the memory during playback. It is expected that this will happen.

In consideration of this situation, especially in the R-DAT method, an address signal indicating the relative order with other blocks is added to each block, and digital data is recorded at a predetermined address on the memory according to this address signal. The method is to do this. However, in this case, if the address signal specifying the address on the memory is incorrect for some reason, the order of the data will be different from the original, which will likely cause abnormalities in the reproduced sound. R-DAT
In this method, in order to prevent this, the first signal is selected from two signals: the address signal and the additional information signal added to the block.
Furthermore, a second error detection and correction code is generated from the digital data in two adjacent blocks, and this code is recorded in the memory together with the data. By doing so, if
Even if the address signal of a certain block is erroneously reproduced and, as a result, the digital data is stored at a different address in the memory from where it should originally be recorded, the second error detection and correction code detects the error in the address. is detected, data correction processing is performed, and correct data can be reproduced. However, according to this method, the second error detection and correction code is generated from data in two adjacent blocks, so if an error occurs in one block, the error will spread to the data in the adjacent block. Furthermore, since the unit of signal processing is two blocks, the data in one field must always consist of an even number of data blocks. No consideration was given to

[Problem that the invention seeks to solve]

The above-mentioned conventional technology does not take into consideration the problem of recording and reproducing systems in which the number of data blocks in one field does not necessarily match for each field, and thus limits its expansion and application to other systems. There was a problem.

An object of the present invention is to provide a digital signal recording method that can be applied to a recording/reproducing system λ in which the number of data blocks recorded within each field is not constant.

[Means for solving problems]

The above purpose is to add an address signal indicating the relative order of this block and other blocks to one block containing a predetermined number of digitized audio signals, and to use the address signal and the digital signals in the block to This is achieved by generating error detection and correction codes, combining these signals into one block, and recording the block on a recording tape.

[Effect]

One block generated when recording a signal is an address signal indicating the relative order of that block.

It consists of digital data within one block and an error detection and correction circuit generated from the address signal and digital data. By configuring one block in this way, (1) even if a signal error occurs within one block, the error will not spread to other blocks; (2)
Since the code is completed in one block, there is no restriction on the number of blocks recorded in one field, for example, whether it is an odd number or an even number.

[Disaster example]

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows an example of the configuration of a digital audio signal recording and reproducing apparatus according to the present invention.

During recording, two R channels of analog signals are input from the input terminal 1. The input signal is amplified to a predetermined level by an amplifier circuit 2, band-limited by a filter 6, and then sampled by a sample hold circuit 4. The sampled input signals are sequentially input to an A/D converter 6 by a switching circuit 5 and converted into a PCM signal. The PCM signal converted by the A/D converter 6 is written into the RAM 15 through a pass line 148.

Then, the addresses of the RAM2S are controlled by the address generation circuits 17 to 19 and the address switching circuit 16, and the
Arranges CM signals and adds error correction codes. Note that the addition of the error correction code is performed using the error correction circuit 20. After the PCM signals are arranged and the error correction code is added, each data is read out from the RAM 15 in block units, and the parallel data is converted into serial data by the parallel to serial conversion circuit 23 via the pass line 14. On the other hand, the synchronization signal, control signal, and address signal to be added to this data are generated by each generation circuit 24, 25, and 26,
These signals are arranged in time series by the selection circuit 27 and sent to the next modulation circuit 28. In the modulation circuit 28, the digital signal to be recorded on the magnetic tape is modulated according to a predetermined modulation method, and after passing through the switching circuit 29: recorded in Furthermore, at this time, the video signal input from the input terminal 33 of the video circuit 35 is also recorded on a predetermined track of the magnetic tape 32 by the dedicated video head 56.

During playback, the switching circuit 29 is switched to the playback side, the signal is played back by the audio head 31, and the preamplifier 37
After that, the digital signal is sent to the rear barrel by the return hook circuit 38. A synchronizing signal is extracted from this digital signal by a synchronizing signal extraction circuit 40, and this synchronizing signal and a head switching signal 13 generated from a head cylinder are sent to a timing generating circuit 21 as a reference signal for a required timing during reproduction. On the other hand, for signals other than the synchronization signal among the digital signals, serial data is converted into parallel data by the surface difference conversion circuit 59, and the data is sent onto the pass line 14.The data on this pass line is then stored in the RAM 15. 0 and 8, data rearrangement and error correction by the error correction circuit 20 are performed.

The PCM signals rearranged in chronological order through the above processing are sequentially converted into analog signals by the D/A converter 12, and resampled by the sample and hold circuit 11 for each channel.

Analog signals resampled in each channel are output from an output terminal 8 through a filter 10 and an amplifier circuit 9.

Next, an embodiment of the present invention will be described in more detail with reference to FIG. FIG. 2 is a diagram showing in more detail the portion from the pass line 14 to the selection circuit 27 that operates during recording in FIG. A/A on the pass line 14 when recording audio signals.
The digital data sent out from the D converter 6 is first converted to R.
A memory is stored at a predetermined address within the M2S. Once the digital data has been stored in the RAM, the data stored at a designated address is selected according to a predetermined rule and sent out again to the pass line. The data on this pass line is then input to an error correction circuit to generate an error correction code. At this time, as will be described later, for one data group (called a block), which is a collection of digital data, an address signal indicating the temporal relative relationship with other blocks is also simultaneously sent to the error correction circuit. This becomes the original data for generating the error correction code together with the data.

The error correction code thus generated is taken into a predetermined address of the RAM2S sent to the pass line. Next, at a predetermined timing ζ, a data read address from the RAM is specified, and the corresponding digital data and error correction code are sent out onto the pass line again.

These signals are converted from parallel data on the pass line to time-series serial data by a parallel-to-serial conversion circuit 23. Now, let's say that 8 bits is one unit (called one symbol), and this unit is divided into a predetermined number, for example, 28 bits.
When symbols are combined into one block of digital data, an error correction code is generated based on these 28 symbols and the address signal. In this case, if the address signal is also composed of the number of bits that correspond to one symbol, the error correction code, one
No. 1 is an oil error correction code generated for 29 symbols, such as a Reed-Solomon code (R-8 code).
etc. can be used. In this embodiment, for example, 4 symbols of error correction code are generated as the R-8 code (SO5
, 29) uses R-8 code.

Therefore, the timing for generating the error correction code is such that the digital data constituting one block is R
In the case where an error correction code is generated every time it is input to AM,
In some cases, digital data is temporarily stored in RAM until it fills a predetermined capacity, and then an error correction code is generated (encoded) after the digital data reaches the predetermined capacity. It is also applicable in the case of

Now, the 28 symbol data generated in this way and the 4
In addition to the symbol error correction code, 8 bits of synchronization signal, 8 bits of control signal, 8 bits of address signal, and 8 bits of parity signal generated from the control signal and address signal are added, resulting in a total of 36 symbols. That is, one block is formed by a 288-bit signal. Here, the synchronization signal is composed of a specific pattern indicating the beginning of one block, and serves as a time reference when data is taken in during reproduction. The control signal is a signal indicating various information accompanying the audio signal to be recorded, such as a signal indicating the order of the song, the number of quantization bits, the sampling frequency, and the elapsed time from the beginning of the song. Also,
An address signal is a signal that indicates the address on the memory of digital data forming one block. Based on this signal, the reproduced digital data is stored at a predetermined address on the memory, and the subsequent Processing is performed. The next parity signal is a parity signal generated from the previous two symbols, and is generated and added by processing such as simple addition modulo 2, for example. This signal performs error detection and correction of the previous two symbols, ie, the control signal and the address signal, and protects these signals from dropouts and noise.

One block of signals generated as described above is sent to the selection circuit 27 in the order shown in FIG. 3(a), for example.
are arranged chronologically. In the example of FIG. 3(a), an 8-bit synchronization signal 42 is placed at the beginning of one block, followed by each 8-bit control signal 43 . address signal 4
4. A parity signal 45, and further digital data 46 consisting of, for example, 28 symbols each consisting of 8 bits. Finally, the error correction code 4 symbols, or 32 bits, which constitute the R-8 code (33.29) generated from the address signal 44 and digital data 46 are arranged, making a total of 36 bits.
One block consists of 288 symbols. One block configured in this manner is further collected into N blocks, and one field, that is, data within one scan period of the head, is generated and recorded in, for example, 142 or 143 blocks. One field composed of N blocks can be represented as shown in FIG. 3(b).

Furthermore, when the data group constituting one field is shown in symbol units, it becomes as shown in FIG. In Figure 4, the symbols that make up one block are lined up vertically, and in order,
N blocks are gathered in the horizontal direction to form one field.

Here, the four symbols of the error correction code Po+PhP21 P3 are added to each block as explained in FIGS. 2 and 5, and are data generated from the address signal and digital data in each block. When a block-contained code as shown in Figure 4 is used, during recording, the signal sent from the A/D converter is stored in RAM for interleaving, and during playback, the signal is reproduced by a magnetic head and stored in the rear barrel. Signals are sequentially recorded in RAM for de-interleaving, but when allocating signals (digital data) in these RAMs, there is a method in which the address of the data in one field and the address on the memory are the same address. It is taken. Therefore, the memory addresses of the blocks to be interleaved or de-interleaved can be known from the respective block addresses. If there is an error in the interleave address (indicating the address on RAM) signal of a certain block during playback, If this error occurs and this error is not detected by the parity signal generated from the control signal and address signal, the digital data in the block will be stored at a different address than originally intended. However, since this data is decoded including the memory address when decoding the error correction code Po=Pm, such errors can be detected.

For example, in decoding an error correction code PO%Pl, if the address signal of the block containing the error correction code is determined to be an error and is corrected to the correct address, the digital data in the block is stored in the memory. By shifting to the correct address5, it is possible to reduce the number of error data in one field0. [Effects of the Invention] According to the present invention, the error correction code is calculated from the address signal and digital data of each block. Since the error correction code is added to each block, the code is completed in one block, so even if a data error occurs in one block, the error will not spread to other blocks. Moreover, there is an effect that the number of blocks constituting one field can be freely selected regardless of whether it is odd or even.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the digital audio signal recording and reproducing apparatus according to the present invention, FIG. 2 is a block diagram of the vicinity of the pass line in FIG. 1, and FIG. FIG. 4 is a diagram showing signals within one field. 15...RAM 15...Address switching circuit 17...Write address circuit 18...Correction address circuit 19...Read address circuit 20...Error correction circuit 25...Parallel-serial conversion circuit 24... Synchronization signal generation circuit 25... Control signal generation circuit 26... Address signal generation circuit 21... Timing generation circuit 41... Parity generation circuit

Claims (1)

[Claims] 1. In a digital audio signal recording and reproducing device that records and reproduces a digitized audio signal alone or together with an image signal using an image signal magnetic recording and reproducing device using a rotating head, a predetermined number of digitized audio signals are collected. One block is formed, an address signal indicating the relative order with other blocks is added to the block, and errors in these signals are detected or corrected from the address signal and digital signals within the block. A digital audio signal recording and reproducing apparatus, characterized in that it generates an error detection and correction code, and records three signals, the error detection and correction code, an address signal, and an intra-block digital signal, in a completed block.