JPH023139A - Pcm signal regenerating device - Google Patents

Abstract

PURPOSE:To prevent abnormal sound due to erroneous correcting by providing a flag detecting circuit to identify recording starting information by a regenerative signal and an algorithmic control circuit to change the algorithm of the erroneous correcting corresponding to a flag detecting result. CONSTITUTION:Respective bits of information are detected with a flag detecting circuit 14 to identify recording starting information by a regenerative signal, moreover, a parity check is executed by a parity detecting circuit 13, and the reliability of a flag 32 and a block address 33 is checked. Then, according to the control of a RAM address generating circuit 19, a first correcting C1 is executed with a generating correcting circuit 18 by parity 37, next, a second generating correcting C2 is executed by parity 36, and data on a RAM 20 is corrected. Then, a recording starting flag recorded on a track 41 immediately after editing is detected at the circuit 14, an algorithm changing command 24 is transmitted to an algorithmic control circuit 17 inside the circuit 18, and the change of a C2 algorithm is executed so that erroneous correcting may not be executed in the C2 correcting of a C2 impossible area and a C2 imperfect area.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an apparatus for reproducing PCM encoded audio signals, etc., and in particular, the present invention relates to a device for reproducing PCM encoded audio signals, etc. The present invention relates to a PCM signal reproducing device suitable for having a complete format.

[Conventional technology]

Playback a recording medium on which PCM audio signals that are not consecutive in time are recorded (hereinafter, this recording method is called editing, and the temporal boundary points are called editing points) from the middle of a recorded part of a certain PCM audio signal. When doing so, abnormal sounds are likely to occur due to discontinuities in the editing points of the output audio signal. Furthermore, if the recording medium has an incomplete format in which time-series data and error correction are not completed within a certain area, a portion of the data before and after the editing point will be lost due to one edit.

For example, if a non-contained format is used in a device that records PCM audio with a rotating head, audio data within a certain time period is recorded across different tracks and error correction codes are added, so editing is not necessary. When doing
Data beyond the track is lost, and in error correction, error correction codes of different series are mixed between the first half and the second half, making correct error correction impossible.

As a conventional device that improved this problem,
As described in No. 56877, a part of the data lost by the i collection is reproduced by error correction and average value interpolation,
There was a cross-fade in which the pre-edited audio signal was faded out, the edited audio signal was faded in and added together, and the audio signals at the editing points were smoothly connected.

[Problem to be solved by the invention]

In the above conventional technology, when correcting errors near the editing point,
No consideration is given to code errors caused by dropouts, noise, etc. during playback, and there is an extremely high risk of erroneous corrections occurring. For example, if m words (m is the minimum distance of the error correction code minus 1) are lost due to editing and 1m erasure correction is performed, there is a code error of 1 word or more in the other regular data area. In this case, it is not only impossible to detect the error, but also the missing m words are incorrectly corrected to a value different from the original one. If this erroneous data and erroneously corrected data are output as audio signals, abnormal sounds will occur, which will be extremely problematic.

Furthermore, even in the case where there are no code errors, when a word with a distance greater than the minimum distance is lost due to editing, there is a certain probability that an erroneous correction will occur, causing an abnormal sound.

SUMMARY OF THE INVENTION An object of the present invention is to provide a PCM signal reproducing apparatus that can prevent abnormal sounds due to erroneous corrections during reproduction before and after an edit point.

[Means to solve the problem]

Generally, recording start information indicating the start of recording is often added to a recording medium recorded by a PCM signal recording device.

Therefore, in order to achieve the above object, it is sufficient to provide a flag detection circuit for identifying recording start information from a reproduced signal and an algorithm control circuit for changing an error correction algorithm according to the detection result of the flag detection circuit.

Note that if the position where the above recording start information is recorded is recorded with a delay of N (a number of N≧0) after the start of recording, the timing of error correction is the same as the timing of playback from the recording medium. It is assumed that this is performed with a delay of N or more.

Furthermore, if it is determined that there is an error in the portion containing the recording start information, it is assumed that the recording start information exists, and means is provided for changing the error correction algorithm.

[Effect]

In general, erasure correction, which corrects errors in words that are sensitive to error positions, has a low detection ability for erroneous corrections, and there is a very high risk of erroneous corrections if there is a code error in a word other than the erasure word. Furthermore, if a word with a distance greater than the minimum distance is lost due to editing, it becomes impossible to correct the error, and on the contrary, there is a possibility that erroneous correction may occur and normal data may be destroyed.

Therefore, when recording start information is detected by the flag detection circuit at an editing point, error correction is prevented by controlling the algorithm control circuit to change the error correction algorithm such as prohibiting erasure correction or prohibiting error correction. be able to.

In addition, if the recording start information is added a time N after the editing point, by delaying the error correction timing by N or more from the playback timing, the timing of the algorithm change described above can be prevented from being lost due to editing. This makes it possible to match the timing of error correction for a series having data that has been modified.

In addition, even if it is determined that there is an error in the part that contains the recording start information, the error correction algorithm can be changed to prevent the recording start information from being detected due to dropout etc. Even in such cases, it is possible to prevent erroneous corrections.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. This figure is a block diagram mainly showing a reproduction system of a PCM audio signal of a VTR. In the figure, 1 is a magnetic tape, 2 is a rotary head for audio, 3 is a rotary head for video, 4 is a rotary cylinder,
6 is the video input terminal.

7 is a video output terminal, 8 is a playback amplifier, 11 is a data bus, 18 is an error correction circuit, 23 is an audio output terminal, 2
4 is an algorithm change command, and 25 is a head changeover switch.

Further, FIG. 2 shows a recording format of a PCM audio signal on the magnetic tape 1, in which one track is composed of L blocks. Note that in the NTSC system, L=135. In the CCIR method, L=162.

The configuration of one block is shown in FIG. In the same figure, 31
is an 8-bit synchronization signal (hereinafter, 8-bit data is referred to as one symbol) indicating the beginning of a block, and 32 is a recording start flag that is one of recording start information.

A flag with information such as sampling frequency, 33 is a block address (indicated by numbers in Figure 2) indicating the position of a block within one track, and 34 is a parity which is the exclusive OR of flag 32 and block address 33. , 35 are audio PCM data, and 36 and 37 are C2 parity and C1 parity in the Reed-Solomon code.

Table 1 shows the specifications of the flag 32. Information for the flag 32 is selected by the LSB side 3 bits of the block address 33. In Table 1, the frame address is an address that counts up by 1 every two tracks, and is represented by 4 bits. Also, the MSB of the block address
The flag located next is a flag indicating whether or not PCM data 35 is recorded on all one track, and is for asynchronous absorption of the track period and sampling period.

The recording start flag is recorded in the diagonally shaded [recording status] in Table 1, and is recorded at the time of recording start.

recorded over 11-racks. First, the operation during reproduction will be explained using FIG.

A signal reproduced from the magnetic tape 1 by the audio rotary head 2 is amplified to a predetermined level by a reproduction amplifier 8, and waveform equalized by a waveform equalization circuit 9. From the waveform equalized signal, serial demodulation data 2 is generated using the demodulation circuit 10.
6 and a serial clock 27 are generated. A synchronization signal 31 is extracted from the serial demodulated data 26 and the serial clock 27 using the synchronization detection circuit 12, and the beginning of the block is detected. Based on the position of the detected synchronization signal, the address detection protection circuit 15 detects the block address 33, the flag detection circuit 14 detects each piece of information, and the parity detection circuit 13 performs a parity check to check the flag 32 and block address 33. Check reliability. Furthermore, the PCM data 35° C2 parity 36 and C1 parity 37 are stored in the RA
It is stored at a predetermined address in M20. Under the control of the RAM address generation circuit 19, the first error correction (hereinafter referred to as C1 correction) is performed using the error correction circuit 18.
Performed first error correction with parity 37 and then second error correction (
02 correction below) with a data arrangement different from 01 correction.
The data on the RAM 20 is corrected by the parity 36. Finally, under the control of the RAM address generation circuit 19,
The PCM data 35 stored in the RAM 20 is read out in chronological order, converted into an analog signal by the D/A conversion circuit 21, high-frequency cut, amplification, etc. are performed by the audio circuit 22, and the audio signal is output from the audio output terminal 23. is output as

FIG. 4 shows PCM data 35.
This is a map diagram of C2 parity 36 and C1 parity 37, where one vertical row corresponds to one block shown in FIG. 3. Further, the number shown in the upper part of FIG. 4 is the block address 33, and writing is performed from left to right. The code sequence for C1 correction is a sequence that alternately moves two adjacent blocks from top to bottom, and the minimum distance is 5, which is marked with Δ in FIG. The C2 series is a series that goes diagonally downward to the right one symbol at a time from one block, and the minimum distance is 7, which is marked with a circle in FIG. In addition, the actual 5-VH8, VTR (
7) Although the C2 sequence in PCM audio is different from that shown in FIG. 4, the above C2 sequence will be used to simplify the explanation. Also, in the figure, it is assumed that the recorded tracks are different on the left and right sides of the center line 30.

During non-editing, the left and right sides of the boundary line 30 are temporally continuous, and the C2 series is also normal.

On the other hand, when editing is performed at the boundary line 30, the left part indicated by 40 and the right part indicated by 41 in FIG. The C2 correction at 43 (hatched in the figure) is incomplete.

For example, in the area 42 indicated by the downward diagonal line to the left (hereinafter referred to as the C2 impossible area), symbols with a distance greater than the minimum distance have been replaced by editing, so if C2 correction is performed normally, there is a high risk of erroneous correction. Also, the area indicated by the diagonal line downward to the right (
43 (hereinafter referred to as the C2 incomplete region) also has the problem that the probability of incorrect correction increases as code errors occur.

Therefore, the recording start flag (block address=4+n) recorded on the track 41 immediately after editing.

n=o, 1, 2. Flag 3 of the block of...
2) is detected by the flag detection circuit 14, and the algorithm control circuit 17 in the error correction circuit 18
The algorithm change command 24 is sent to the C2 disabled area 4.
The C2 correction algorithm is changed or the C2 correction is stopped so as not to cause erroneous correction in the C2 correction of the C2 and C2 incomplete regions 43.

By the above-described operation, it is possible to prevent incorrect C2 correction due to discontinuity in the C2 series before and after the editing point, and it is possible to prevent abnormal sounds from occurring.

By the way, as mentioned above, the recording start flag is detected for the first time in the block with block address = 4, so the timing of C2 correction of the C2 incomplete area 43 and C2 impossible area 42 is after the block with block address = 4 is reproduced. There is a need to do. Therefore, C2 correction is performed at the timing shown in FIG. Here, it is assumed that the 02 correction is performed one block at a time from left to right in FIG. Further, in FIG. 5, the maximum C2 block address is the block address of the symbol located at the lowest position in the C2 series (the symbol at the position marked 45 in FIG. 4). In other words, the 02 correction of the symbol at the 45th position is performed for 5 blocks or more (5 blocks in FIG. 5) with respect to the reproduction timing.
This can be done with a margin of For example, while playing the block with block address = 5,
By performing C2 correction on the C2 series whose maximum C2 block address is O (44 C2 series in FIG. 4), it becomes possible to match the timing of algorithm change with the timing of C2 correction. Furthermore, when the block address of the reproduced signal reaches 35, the algorithm change command 24 is canceled to return to the normal 02 correction mode.

Note that the postamble and preamble in FIG. 5 are portions in which a certain pattern of signals is recorded as a margin before and after an area recorded over L blocks. (Not shown in FIG. 2) FIG. 6 shows a circuit example of the flag detection circuit 14, in which 50 is a synchronization detection signal, 57 is a synchronization detection signal input terminal, 58 is a serial data input terminal, 59 is a block address input terminal, 60 is an algorithm change command output terminal, 61 is a flag clock, 62 is a flag control pulse, 6
7 is a detection parity input terminal, and 68 is a detection parity. Further, 52 is a shift register for performing 8-bit serial/parallel conversion, 56 is a set/reset flip-flop, 54 is a flag selection circuit, and 64 is an AND.

The operation of the flag detection circuit shown in FIG. 6 will be explained below according to the timing chart shown in FIG.

The synchronization detection circuit 12 generates a synchronization detection signal 50 based on the synchronization signal 31 in the serial data 26 . The timing generation circuit 51 generates a flag clock 61 and a flag control pulse 62 according to the timing shown in FIG. 7 in response to the synchronization detection signal. Also, since serial data is input to the shift register 52 as shown in FIG.
An 8-bit flag signal 32 is latched into the latch 53 by the flag clock 61. block address 33
is changed by the block address detection protection circuit 15 at the timing shown in FIG.
Extract each piece of information. For example, when the LSB side 3 bits of the block address are 4, the recording start flag is added to the recording state in Table 1, so it is extracted by AND64, input to the set terminal of the flip-flop 56, and the algorithm change command is input. Next, when the block address 33 becomes "r34", a reset signal 66 is input from the address decoder 55 to the reset terminal of the flip-flop 56, and the algorithm change command 24 is reset to a low level. do. Note that the reliability of the recording start flag can be increased by generating the flag control pulse 62 only when the detected parity 68 is normal.

FIG. 8 shows a circuit example of an algorithm control circuit, and in FIG. 8, 80 is a NAND.

81 is AND, 82 is E-OR 283 is an algorithm change command input terminal. 85 is an error correction processing circuit 1
The error value 86 obtained by 6 is the 02 signal which becomes high level at the timing of 02 correction.

Normally, since the algorithm change command 24 is at low level, NAND81 is at high level, and the error value is 85.
is input to E-OR82. At the same time, the data corresponding to the error position determined by the error correction processing circuit 16 is input to the RAM 20 (JE-OR 82) via the bus 11, and after being corrected to the correct value, the data is input to the latch 84 and the bus 1
Corrected data is written to the same address of the RAM 20 again via the address 1.

Here, if the algorithm change command 24 and the C2 signal 86 are at high level, NAND80 is at low level and AND81 is always at low level, so error data is no longer corrected. By doing this,
It becomes possible to easily stop the C2 correction in response to the algorithm change command 24. However, it is assumed that the information indicating the C2 correction abnormality is stored in the RAM 20 or the like by another means.

Further, FIG. 9 shows another circuit example of the algorithm control circuit 17. In the error correction circuit shown in FIG. 9, the error correction processing circuit 16 operates according to the program stored in the program ROM 90 to perform predetermined error correction.

When reproducing an edit point, a program change command 24 is input to a branch condition determination circuit 92, a load signal 93 is sent to an address counter, a predetermined address is loaded, the program is branched, and the C2 correction is changed.

By the way, the algorithm change command 24 is activated by the recording start flag of the block whose block address is "4", but if the recording start flag that should have been recorded is not detected due to dropout etc. , the C2 algorithm change timing will be delayed by more than 8 blocks, and there is a risk that erroneous correction will occur during that time.

However, if the expected flag is not detected,
Abnormalities can be detected by a parity check using the parity 34. Therefore, even if it is determined that there is an abnormality as a result of the parity check of the block in which the recording status flag is recorded, it is assumed that the recording start flag is set.
By changing the C2 correction algorithm, it is possible to prevent delays in change timing and prevent erroneous corrections.

FIG. 10 shows an embodiment of the above invention.

This figure shows the embodiment shown in FIG. 1 with a parity control circuit 100 added thereto.

The operation of the parity control circuit 100 will be briefly explained below with reference to the timing chart of FIG.

FIG. 11(A) shows a case where the recording start signal that should have been recorded at block address = "4" could not be detected. In this case, the polarity of the bit at the recording state position in the flag 32 is reversed and reproduced. On the other hand, the parity detection circuit sequentially performs an exclusive OR on each bit of the three symbols of the flag 32, block address 33, and parity 34, when there is no abnormality in the three symbols.

Since parity 34 = flag 32e block address 33 (where e represents exclusive OR), the OR of the three symbols results in all bits being low level, but in the case of FIG. 11(A) above, Since the flag 32 is different from the value at the time of recording, it does not become all low level, so the parity check is determined to be abnormal and the detected parity signal 68 is output.

The parity control circuit 100 detects that the detection parity signal 68 becomes low level when the block address is 4, and sets the algorithm change command B101 to high level. Furthermore, if the recording start flag is normally detected when the block address is 12, then the parity control circuit 1
00 causes the algorithm change instruction BIOI to fall to a low level, while the flag detection circuit 14 causes the algorithm change instruction 24 to rise to a high level.

With the above operations, even if the recording start flag that should have been detected cannot be detected, the C2
The correction algorithm can be changed.

Here, even if the block address is 4 and the parity becomes abnormal during non-editing, the C2 correction algorithm will be changed, but if the parity is obtained normally after the next 8 blocks, the algorithm change command B101 will be canceled. 02 correction is now performed normally, and its influence is very small.

FIG. 12 shows a circuit example of the parity control circuit 100, in which 120 is a parity clock input terminal;
1 is a detection parity input terminal, 122 is an inverter, 12
3 and 124 are AND.

126 is a set/reset flip-flop, 127 is an algorithm change command B output terminal, 128 is a block address input terminal, and 129 is a parity clock. The timings of the parity clock 129 and the detected parity 68 are shown in FIG. 13, and are input from the synchronization detection circuit 12.

The circuit in FIG. 12 is based on the LSB side 3 of the block address 33.
When the bit is “4”, the detection parity 50 is low level (
A set signal is sent to the flip-flop 126 when the signal is at high level (normal condition), and a reset signal is sent to the flip-flop 126 when the signal is at high level (normal condition), thereby generating an algorithm change command B101.

Here, Table 2 shows an example of algorithm change specifications. In the same table, Norm means performing normal error correction, C2
"Era" means to stop C2 correction, and "Era" means to stop erasure correction, which has a high probability of incorrect correction among C2 corrections, and shows five examples of change specifications from ■ to ■.

■ and ■ are methods when the algorithm change command B101 is not used, ■ is a method of stopping the entire 02 correction, and ■ is a method of stopping only the erasure correction. In addition, ■ to ■ are those that use algorithm change command B101,
■ and ■ are algorithm change commands (24 and 1
01) is also a method of stopping C2 (■) or stopping erasure correction (■). (2) is a method in which the erasure correction is stopped when only the algorithm change command B101 is issued, and on the other hand, when the algorithm change command 24 is generated, 02 is always stopped. As shown in FIG. 11(B), the method (2) can minimize the influence of the algorithm change when a parity abnormality occurs during non-editing.

Although not shown in Table 2, even in the case of C2 stop,
In the 2 to 3 blocks on both the left and right ends of the C2 incomplete area in Figure 4, there are relatively few symbols lost due to editing, so C2 correction is performed only on these blocks to increase effective data and improve the sound quality. Improvements can be made.

Note that in the above embodiment, the rotating head allows the audio PCM
A PC, M device using a device for reproducing the signal, but having other incomplete formats, such as a fixed head PCM.
Similar effects can be obtained by implementing the present invention in playback devices, write-once discs, and the like.

Further, although the flag 32 is used in this embodiment as a method for detecting one edit point, other methods can also be used for detection. For example, on a track after recording has started. The preamble pattern shown in Fig. 5 is recorded by changing part or all of it, and the change in the preamble pattern is detected during playback.
You can see the editing points. This method has the advantage of being able to detect editing points more quickly than using a recording start flag, and being resistant to missing flag detection due to dropouts and the like. Furthermore, when implementing the present invention in a VTR, etc., the CTL (CTL) that records a frame period control signal)
- There are methods such as using the VISS and VASS of the rack, or recording editing information on an audio track for recording and reproducing analog audio signals, and using this information during reproduction. These methods have the advantage that editing information can be dubbed after recording the PCM audio signal and video signal.

〔Effect of the invention〕

According to the present invention, in a PCM signal reproducing apparatus having a format in which error correction is not completed within a certain area of a recording medium, it is possible to prevent abnormal sounds due to erroneous correction when reproducing edit points that are not consecutive in time.

Furthermore, when the editing information recorded on the recording medium is played back with a time delay of N (N≧O) with respect to the editing point,
By delaying the timing of error correction by N or more with respect to the reproduction timing, it is possible to prevent a delay in the timing of changing the error correction algorithm for preventing error correction.

Furthermore, when a data error is detected in a block in which one piece of editing information is recorded, it is determined that editing information has been detected, thereby preventing erroneous correction due to a detection error in editing information.

[Brief explanation of the drawing]

1 and 10 are block diagrams of a VTR according to an embodiment of the present invention, FIG. 2 is a magnetic tape recording format diagram, FIG. 3 is a block configuration diagram, FIG. 4 is a RAM map diagram, and FIG.
12 is a timing chart of error correction, FIG. 6 is a block diagram of the flag detection circuit, FIG. 7 is an operation timing chart of FIG. 6, FIGS. 8 and 9 are block diagrams of the algorithm control circuit, and FIG. The figure is a circuit diagram of the parity control circuit, and FIGS. 11 and 13 are operation timing charts of FIG. 12. 12... Synchronization detection circuit, 13... Parity detection circuit. 14...Flag detection circuit, 15...Address detection protection circuit, 17...Algorithm control circuit, 18...
error correction circuit, 19... RAM address generation circuit, 2
0...RAM. Plan number 72 (B)

Claims (1)

[Claims] 1. Reproducing a recording medium on which a PCM signal, an error correction code added to the PCM signal, and recording start information indicating a recording start position are recorded, and performing the error correction as described above. The playback device has an error correction circuit that corrects errors in the PCM signal using a code, and includes a recording start information detection circuit that detects the recording start information, and the error correction circuit performs correction according to the recording start information detection circuit. A PCM signal reproducing device characterized by stopping part or all of error correction or changing an error correction algorithm. 2. In the PCM signal reproducing apparatus according to claim 1, as means for stopping part or all of the error correction performed by the error correction circuit or changing the error correction algorithm, the recording start information detection circuit A PCM signal reproducing device characterized in that the detected recording start information is used. 3. In the PCM signal reproducing apparatus according to claim 1, when reproducing a recording medium on which recording B has been newly performed from the middle of a portion where recording A has already been performed, at the joint between said recording A and said recording B, A PCM signal reproducing device characterized by stopping part or all of error correction or changing an error correction algorithm. 4. The PCM signal, the error correction code added to the PCM signal, and the recording start information indicating the recording start position can be reproduced on a recording medium in which the recording is performed with a delay of time N from the actual recording start time. and use the above error correction code to perform the above P
A playback device that has an error correction circuit that corrects errors in a CM signal, and for all playback data that undergoes error correction by the error correction circuit, after a time N after the playback data is played back from the recording medium. A PCM signal reproducing device characterized by performing error correction once or multiple times. 5. In the PCM signal reproducing apparatus according to claim 4, the error correction A is performed one or more times before a time N after the reproduction data is reproduced from the recording medium, and the error correction A is performed after the time N. P that is characterized by performing error correction B once or multiple times in a data array different from
CM signal reproducing device. 6. Play back the recording medium on which the PCM signal, the error correction code added to the PCM signal, and the recording start information indicating the recording start position are recorded, and use the error correction code to read the PCM signal. The playback device is equipped with an error correction circuit that corrects errors in the recording start information, and includes an abnormality detection circuit that determines whether or not the reproduced data in the portion where the recording start information is recorded is normal. stop some or all of the error corrections being made; or
Alternatively, a PCM signal reproducing device characterized by changing an error correction algorithm.