JPH01307059A - Demodulating circuit for reproducing device - Google Patents

Abstract

PURPOSE:To obtain a circuit to give more preferential to the transfer speed by controlling a point to convert a reproducing signal to a PWM signal in accordance with the identified result of the duty ratio of header data. CONSTITUTION:Head data are compared with a reference value through an amplifier 21 by a comparator 22 and supplied to an LSI 29. A duty ratio identifying circuit 25 and a header data storing circuit 26 are activated in accordance with the recognized result with a header recognizing circuit 24. The circuit 25 identifies the duty ratio of the pulse width from the comparator 22 and the identified result is sent to the circuit 26 as demodulation data. The circuit 26 stores the data from the circuit 25 and sends them to a pulse width modulating output circuit 27. The output of the circuit 27 is given to the comparator 22 as the reference level of a threshold. The comparator 22 executes the comparing judgement of the input level with a value to correct the direct current part and an original PWM signal is faithfully reproduced as an output.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a demodulation circuit for a reproducing apparatus that records and reproduces image data using a magnetic tape.

[Conventional technology] In recent years, portable cassette tape recorders have become popular.

This cassette tape recorder uses a compact cassette tape for audio and can only listen to audio, but there is a desire to display not only audio but also video. For example, it may be possible to display a singer's face or image in time with the music, or to display sample English conversation sentences. For this purpose, it is conceivable to incorporate a so-called VTR using a 1/2 inch wide magnetic tape, but this would increase the size of the device, so it is desirable to record images on a compact cassette tape. Considering the capacity of the tape, this is technically possible if still images are recorded intermittently.

[Problems to be Solved by the Invention] However, when recording digital data on a magnetic tape and reproducing it, a normal reproduction signal may not be obtained due to code amount interference, dropout, or the like. In general, in digital magnetic recording devices, even a single bit error can completely change the meaning of the data, so strict waveform shaping is required, and various waveform equalization circuits have been proposed.

On the other hand, when recording an image signal, although some bit errors do not cause visual problems, the image signal has a large amount of information and therefore requires an extremely high data transfer rate. However, since conventional methods place emphasis on accuracy, there is a problem in that the transfer speed is slow.

For example, in the computer field, the transfer rate is generally 20
However, when recording image signals, a transfer rate of 50,000 bps or more is required.

This invention was made in view of the above circumstances,
It is an object of the present invention to provide a demodulation circuit for a simple playback device that prioritizes transfer speed over error rate.

[Means and effects for solving the problems] The present invention provides a playback method in which both a television video signal and an audio signal are recorded on a compact cassette tape, the reproduced video signal is displayed on a liquid crystal display panel, and the audio is emitted from a speaker. The demodulation circuit of the device recognizes the header data that is composed of PWM signals with a predefined duty ratio and is attached to the beginning of the reproduced signal for each specific unit, and PWMs the reproduced signal according to the identification result of the duty ratio of the header data. By controlling the comparison point of a comparator that converts into a signal, it is possible to demodulate a PWM signal that is faithful to the original PWM signal before recording from a reproduced signal.

[Embodiment] Hereinafter, the present invention will be described in which the present invention is equipped with a tape recorder section using a compact cassette tape and a liquid crystal television section using a liquid crystal display panel. An embodiment in which the present invention is applied to a recording and reproducing apparatus that displays images and emits audio from a speaker will be described with reference to the drawings.

First, the format for recording and reproducing a cassette tape in the recording and reproducing apparatus of the present invention will be explained with reference to FIGS. 1 to 6.

FIG. 1 shows a sampling state of a color video signal obtained by receiving a TV broadcast. As shown in (a) and (b) of the same figure, one screen is obtained at a rate of one image every 1760 seconds (
For example, if the number of display dots on a liquid crystal display panel is 224 vertically x 144 horizontally, the video signal for IV) is 26
Slightly less than 20 upper and lower lines of the 2.5 horizontal scanning lines are cut, and 224 lines are used as effective video signals as shown in FIG. 1(c). In this case, the - horizontal operation time IH is the first
As shown in figure (d), 1/15750 seconds (-(1/Go
)X (1/262.5). From this IH video signal, the number of horizontal dots on the liquid crystal display panel is 144.
432 pieces of data determined by X3 (RGB) are sampled and converted into PWM, and the sampling frequency at that time is <6.8 MHz as shown in FIG. 1(f). Further, the number of quantization bits at this time is 3, indicating 8 levels of gradation. FIG. 1(e) shows the image data for each color rRIJ rGIJ rBIJ rR2 obtained in this way.
JrG2J rB2J rR3J rG3J
rB3J・・・・・・rR144J rG144J
rB144J, and the obtained data is sent to the next stage processing circuit as two data columns as shown in the figure.

FIG. 2 shows a recording format of the video data obtained by sampling in FIG. 1 above onto a cassette tape. Conventional audio cassette tapes have a 4-track, 2-channel head system, which is A/
Previously, recording/playback was performed on both sides of the cassette tape, but now there are 4 tracks and 4 channels including video tracks, and the cassette tape is recorded/played on only one side. This is 1
Either one track is used for audio and the remaining three tracks are used for video, or two tracks are used for stereo audio and two tracks are used for video.

FIG. 2 shows the track configuration when one of the four tracks is used for audio and three tracks are used for video. As shown in Figure (A), the first track contains the audio data, the second track contains the R information of the color video data, the third track contains the G information, and the fourth track contains the B information. recorded. The RGB information of the second to fourth tracks has the data format shown below. In other words, each piece of RGB information is the data for IH (
The data for one screen is obtained by arranging 244 pieces (144 dots in one horizontal row) as shown in the figure while dividing them with division data called headers and separators. In each IH data, as shown in FIG. 2(B), 144 dots of data R1 to R144, Gl to
G144°81 to B144 are sequentially recorded on each track.

Each of these dot data is recorded as a 3-bit 8-gradation PWM signal as described above.

FIG. 3 shows the signal structure of the header. The header contains one screen worth of video data (
1v), and is placed at the beginning of Figure 3(
As shown in a), it is composed of a combination of a 4kHz pulse, an 8kHz pulse, and a 4kHz pulse. That is, the first 4kIiz pulse is 8 times each with a duty ratio of 1/2 as shown in Fig. 3(b), and the subsequent pulses of <8kHz are 8 times each with a duty ratio of 1/2 as shown in Fig. 3(C). There are four pulses at a duty ratio, and finally four pulses at 4 kHz, each at a duty ratio of 1/2, as shown in FIG. 3(d).

FIG. 4 shows the signal configuration of the separator. The separator is attached after the IH data stored in the track to separate it from the next data, and is composed of only 4 kHz pulses as shown in FIG. 4(a). That is, as shown in FIG. 4(b), it consists of four consecutive 4kHz pulses.

The following FIG. 5 shows the signal waveform of the video data.

As mentioned above, the video signal is a 3-bit, 8-gradation PWM signal whose fundamental frequency is f. -8kHz.

In addition, although Figure 2 above shows a case where one of the four tracks recorded on the tape is used for audio and the remaining three tracks are used for video, two tracks are used for stereo audio and two tracks are used for video. You can. in this case,
As shown in FIG. 6(A), the right (R) channel audio data is on the first track, the left (L) channel audio data is on the second track, and the third and fourth tracks are as shown in FIG. , the header and separator shown in FIG. 4 are interposed, and the color video data in the arrangement shown in FIG. 1(e) is recorded, respectively. If this is done, the tape length required for one screen of video data will be 3/2 times that of the example shown in FIG. 2 above, and the display time for one still image will also be 3/2 times as long. It is possible to listen to audio in stereo, and it is compatible with audio multiplex broadcast programs.

Next, the configuration of a demodulation circuit that demodulates the reproduced data into a PWM signal before recording when reproducing the recorded data as described above will be described.

FIG. 7 shows its schematic configuration, in which analog value input data is amplified by an amplifier 21 and then sent to a comparator 22.
is sent to the + side input terminal of. A voltage signal amplified by an amplifier 23 is input as a reference level to one side input terminal of the comparator 22, and a pulse-like signal consisting of binary high/low values is sent to the header recognition circuit 24 according to the comparison result. and is output to the duty ratio identification circuit 25. The header recognition circuit 24 recognizes whether or not the pulse signal sent from the comparator 22 is a header data pattern.
Sends a signal to instruct writing to. The duty ratio identification circuit 25 identifies the duty ratio of the pulse width sent from the comparator 22, and sends the digital data that is the identification result to the next stage processing circuit (not shown) as demodulated output data. It is also sent to the Herada data storage circuit 26. The header data storage circuit 26 stores the duty ratio and the digital data from the identification circuit 25 in response to the instruction of the write signal from the header recognition circuit 24, and reads the data to the pulse width modulation output circuit 27. The pulse width modulation output circuit 27 pulse width modulates the digital data read from the header data storage circuit 2B to generate a PWM signal, and outputs the PWM signal to a low pass filter (LPF) 28. The voltage level of the signal converted into direct current through the low-pass filter 28 is amplified by the amplifier 23 and inputted to one input terminal of the comparator 22 as a reference level. Note that 29 indicated by a dashed dotted line in the figure indicates a portion constituted by an LSI.

With the above configuration, the third input data is
Assume that header data obtained by converting the data pattern shown in the figure into an analog waveform is sent. This header data is amplified by the amplifier 21 and input to the + side input terminal of the humpator 22. A pulse width signal outputted from the pulse width modulation output circuit 27 is converted into a DC voltage by a low pass filter 28, amplified by an amplifier 23, and then input as a threshold level to one input terminal of the comparator 22. Normally, when the pulse width signal output from the pulse width modulation output circuit 27 has a duty ratio of 1/2,
If the analog signal input to the + side input terminal of the comparator 22 is an analog version of a pulse width signal with a duty ratio of 1/2, the comparator 22 outputs a pulse width signal with a duty ratio of 1/2. However, when header data including a DC bias is input as input data, the pulse width signal output from the comparator 22 does not necessarily have a duty ratio of 1/2. However, since the header recognition circuit 24 recognizes header data only based on the basic cycle, it can recognize the header data as header data even if the duty ratio deviates, and the duty ratio recognition circuit 24 recognizes the header data based on the recognition result. 25, output a signal to the header data storage circuit 26; The duty ratio identification circuit 25 identifies the duty ratio of the pulse width sent from the comparator 22, and sends the identification result, for example, 3-bit digital data, as demodulated output data to the next stage processing circuit (not shown). At the same time, it is also sent to the ladder data storage circuit 26 mentioned above. The header data storage circuit 2B stores the duty ratio identification circuit 25 in response to a signal instruction from the header recognition circuit 24.
The digital data from the pulse width modulation output circuit 27 is stored and read out to the pulse width modulation output circuit 27. The pulse width modulation output circuit 27 pulse width modulates the digital data from the Helada data storage circuit 26 and outputs it as a PWM signal, and the voltage level of the signal converted to DC via the low pass filter 28 is amplified by the amplifier 23, The signal is inputted to one input terminal of the comparator 22 as a threshold reference level. As a result, the comparator 22 compares and determines the input level using the value corrected for the DC bias.

After this, it is assumed that data as shown in FIG. 8(b), for example, is input. The PWM signal waveform that is the source of this data is shown in FIG. 8(a). If this input data contains a DC bias component and the threshold level of the normal comparator 22 is the level shown in FIG. 8(b) and (c) for the input data,
In the conventional demodulation circuit, the comparator performs comparison output using the threshold level as the reference level, so the signal output from the comparator becomes a PWM signal as shown in FIG. 8(d). The result will be completely different from the original PWM signal shown in a).

However, here, as described above, the variation in the DC bias is corrected by the header data recognition process as described above, and the one side input terminal of the comparator 22 is
Since the signal at the level shown in (b) is input as the reference level of the threshold, its output is as shown in Fig. 8 (c).
), and the original PW shown in Fig. 8(a) is obtained.
This makes it possible to faithfully reproduce the M signal.

Next, a specific example of the configuration of the above embodiment will be explained using FIG. 9.

A reproduced waveform signal S picked up by a magnetic head 31 from a magnetic tape 30 of a compact cassette, which is a recording medium.
is amplified by the amplifier 21 and then sent to the + side input terminal of the comparator 22. A control signal is converted into a DC voltage through a low-pass filter 28 and sent to one side input terminal of the comparator 22 as a slice voltage C, and the comparator 22 generates a reproduced waveform signal S using this slice voltage C as a reference. Pulse width modulation wave, LS
After being synchronized with other circuits in the LSI 29 by a flip-flop (hereinafter abbreviated as rF/FJ) 32 in the I29, it is sent to a one-pulse generation circuit 33 and an AND circuit 34. The one-pulse generation circuit 33 generates one pulse that becomes the reset signal R3T every time the input pulse width modulation wave rises, and the first pulse generation circuit 35, F/F
38 to 38, the second pulse generating circuit 39 and the eight reading circuit 40 are outputted, respectively. The clock CK22 from the second pulse generating circuit 39 is input to the AND circuit 34, and its output becomes the operating clock of the first pulse generating circuit 35 to generate pulses, and the generated pulses are F /F Input to clock terminal CK of 3B. These F/F 3B and F/F 37.38 correspond to the duty ratio identification circuit 25 in FIG. 7 above. The output from the Q terminal of F/F 3B becomes the least significant digit a of the 3-bit image data cba, and the output from the Q terminal is sent to the clock terminal CK of F/F 37 and its own D terminal. Similarly, the output from the Q terminal of F/F 37 becomes the second digit of the image data, and the output from the mouth terminal is sent to the clock terminal CK of F/F 3B and its own D terminal. Further, the output from the Q terminal of the F/F 38 becomes the highest digit C of the image data, and the output from the mouth terminal is sent to its own D terminal. This F/FH
The 3-bit image data cba output by ~38 is sent to the RAM which is the next stage processing circuit, while the data C is
/F42 D terminal, data b is F/F4
Data a is sent to the D terminal of F/F 44, respectively.

The second pulse generating circuit 39 is the one pulse generating circuit 3
It is reset by the reset signal RST from 3, and the clock pulse CK22 (waveform is the first
At the same time, the generated clock pulse is also sent to the 8 kHz data reading circuit 45.4 kHz data reading circuit 4B. The 8kHz data reading circuit 45 and the 4kHz data reading circuit 4B constitute the header recognition circuit 24 shown in FIG. The pulse is read from its cycle, and when an 8kHz pulse is read, the pulse is sent to the clock terminal CK of the F/F 47. The output from the Q terminal of F/F 3B is sent to the AND circuit 48, and the output from the opening terminal is sent to the clock terminal CK of F/F 49 and its own D terminal. Similarly, the output from the Q terminal of F/F 49 is output from AND circuit 48.
Then, the output from the Q terminal is sent to the clock terminal CK of F/F 5G and its own D terminal. Further F/F
The output from the Q terminal of 50 is sent to the reset terminal R of the 4-shot reading circuit 51 and its own D terminal. The above 4kHz data reading circuit 4B reads 4 of the first 8 shots in the Herada data.
The kHz pulse and the last four 4kHz pulses are read from their respective periods, and when read, the pulses are sent to the 4-shot reading circuit 51 and the 8-shot reading circuit 40. The 4-shot reading circuit 51 is a quaternary counter, and the 8-shot reading circuit 40 is an octal counter.
” to “0”, the above F/F47
．． A reset signal is sent to each reset terminal R of 49.50. The above AND circuit 48 connects F/F 47 and F/
A signal CKS is sent to the clock terminals CK of the F/Fs 42 to 44 by input from each Q terminal of the F/F 49. The F/Fs 42 to 44 are set to a predetermined value at the time of reset by an initial signal from the control system of the system (not shown), and temporarily hold the image data from the F/Fs 3B to 38. The output from the Q terminal goes to the D terminal of F/F 52, and the output from F/F 4
The output from the terminal No. 3 is sent to the D terminal of F/F 53.
And the output from the Q terminal of F/F 44 is F/F
Each signal is sent to the D terminal of F54. F/F
52 to 54 each operate according to the clock CKD1, and output a signal from each Q terminal to the NAND circuit 59 via OR circuits 55 to 57. This NAND circuit 59 also has
F/ which is reset by the above clock CKD1
The output from each Q terminal of F 80 to 62 is OR circuit 57 to
55.

The F/F 60 is operated by a clock pulse CKH input to its clock terminal CK, and the output from the Q terminal is sent to the clock terminal CK of the F/F 61 and its own D terminal. Similarly, the output from the Q terminal of F/F Ill is sent to the clock terminal CK of F/F 82 and its own D terminal, and the output from the Q terminal of F/F 62 is sent to its own D terminal. The output of the NAND circuit 59 is input to the D terminal of F/F[i3, where the clock pulse CKII (the waveform is shown in FIG. 12) is input to the clock terminal CK. The output from the Q terminal of F/F63 is composed of two NAND circuits and is input as a set signal for F/F B4 which uses clock pulse CKDIB as a reset signal. The output from the terminal becomes a control signal, which is converted into a DC voltage via the above-mentioned low-pass filter 28 outside the LSI 29,
The slice voltage C is sent to one input terminal of the comparator 22.

With the above configuration, header data recorded on the magnetic tape 30 is picked up by the magnetic head 31, amplified by the amplifier 21, and sent as a reproduced waveform signal S to the + side input terminal of the comparator 22. FIG. 10 shows the PWM signal waveform of the original Herada data before recording. Reproduction signal S input to the + side of comparator 22
has a signal waveform as shown in (b) for the PWM signal with a 1/2 duty ratio shown in (a) in FIG. 11(I). At this time, 1/2 is applied to one side input terminal of the comparator 22.
11 (1) as the output of the comparator 22.
) and (c), a pulse width modulated wave is obtained by faithfully demodulating the original PWM waveform signal. This pulse width modulated wave is clocked by F/F 32, and the CPU is clocked by CKI.
After being synchronized with other circuits in 29, AND circuit 3
4 and is sent to the one-pulse generating circuit 33. AND circuit 3
4 sends the clock CK22 to the -1st pulse generating circuit 35 while the pulse width modulation wave is "1". The first pulse generation circuit 35 uses this clock CK22 to generate an F/F that constitutes the duty ratio identification circuit 25.
Reference frequency 8 to F/F 3B among 36-38
Clock pulses are sent out at a rate of 8 per kHz cycle. The F/Fs 3B to 38 are reset by a pulse generated from the one-pulse generating circuit 33 at the rising edge of the pulse width modulated wave, and output 3-bit image data rcbaJ corresponding to the pulse width modulated wave.

FIG. 12 shows the waveform of the pulse width modulation wave corresponding to the image data output from the above F/Fs 3B to 38 using the clock C.
K22. It is shown together with CKII. When the header data is reproduced with the faithfully demodulated pulse width, the image data cba becomes rloOJ (-r4J).

In addition, at the same time as identifying the duty ratio of this image data, 8
kHz data reading circuit 45 and 4kHz data reading circuit 4
6, header data is recognized.

4 following the first 8 4kHz pulses of the header data.
The third of the 8 kTIz pulses is 8 kHz.
F/F 4 at the time it is read by the data reading circuit 45
The output from the Q terminal of 7°49 becomes "1", which is passed through the AND circuit 48 to F as a clock pulse CKS.
/F Input to clock terminals CK of 42 to 44.

In accordance with this, the F/Fs 42 to 44 take in the image data "cbaJ" at that time. In the initial state, the F/Fs 42 to 44 receive 8 kHz image data with a duty ratio of 1/2 according to the initial signal. control signal Cr
100J is set.

If the data taken in by the F/Fs 42 to 44 in accordance with the clock pulse CKS is, for example, "100" indicating a duty ratio of 1/2, the inverted data r011J is sent to the F/Fs 52 to 44 in synchronization with the clock pulse CKDI.
54 and sent from each Q terminal to a NAND circuit 59 via OR circuits 55 to 57. The NAND circuit 59 also receives the outputs from the Q terminals of the F/Fs 130 to 62, which are reset by the clock pulse CKDI, via the OR circuits 57 to 55.
The operating clock of the F 60 is a clock pulse CKH having the same cycle as the operating clock of the F/F 36, that is, the number of pulses during one cycle of the reference frequency of 8 kHz is 8. F by clock pulse CKH
/F The 3-bit data held by 60 to 62 is r
Until ooIJ is reached, the data input from the OR circuits 55 to 57 to the NAND circuit 59 becomes rollJ, and the NAND circuit 59 outputs a signal "1" to the D terminal of F/FH. This allows the F/F 63 Q terminal to
The signal to the set terminal of /F64 also becomes “1”,
Therefore, the control signal output from the Q terminal of the F/F 64 also becomes "1". After that, F/F80
~ From the time when the 3-bit data held by B2 becomes roolJ until it becomes "111", the OR circuits 55 to 57
The data input to the NAND circuit 59 from rl 11J
Therefore, the NAND circuit 59 outputs a signal “0” to the D terminal of the F/F 83. As a result, the signal from the Q terminal of F/F 63 to the set terminal of F/F 64 also becomes 0.
”, and therefore the control signal output from the Q terminal of the F/F 84 also becomes “0”. With the above operation, the control signal from the F/F 64 becomes 172 seconds at the beginning of one cycle of the reference frequency of 8 kHz. is "1" and the remaining 1/2 is "0", resulting in a pulse width modulation signal with a duty ratio of 172. This control signal is converted into a DC voltage via a low-pass filter 28 outside the LSI 29 and sent to one side input terminal of the comparator 22 as a slice voltage C. The reproduced waveform signal S
is made into a pulse width modulated wave based on the optimum slice voltage C, and demodulation faithful to the original signal is performed.

Further, the playback signal S of the header data inputted to the + side of the comparator 22 is 1/2 as shown in (a) in FIG. 11(n).
The signal waveform shown in (b) corresponds to the PWM signal of the duty ratio, and the slice voltage C input to the one side input terminal of the comparator 22 fluctuates for some reason and increases as shown by the solid line in the figure. If this happens, a pulse width modulated wave smaller than the original PWM waveform signal is obtained as the output of the comparator 22, as shown in FIG. 11(n) and (C). This pulse width modulated wave is sent to an AND circuit 34 and a one-pulse generation circuit 33 via an F/F 32. The AND circuit 34 sends the clock CK22 to the first pulse generation circuit 35 while the pulse width modulation wave is "1". The first pulse generation circuit 35 sends a clock pulse to the F/F 3B using this clock CK22. The F/Fs 38 to 38 are reset by a pulse generated from the one-pulse generation circuit 33 at the rising edge of the pulse width modulation wave, and 3-bit image data rebaJ according to the pulse width modulation wave is reset.
Output. In this case, the image data “cbaJ is the 11th
As shown in (d) in Figure (II), ro 11J (-
r3J).

In addition, at the same time as identifying the duty ratio of this image data, 8
kHz data reading circuit 45 and 4kHz data reading circuit 4
The header data is recognized by B, and the first eight 4kHz pulses of the header data are followed by four 8K pulses.
At the point when the third of the Hz pulses is read by the 8 kHz data reading circuit 45, the output from the Q terminal of the F/F 47°49 becomes "1°," and this is the output from the AND circuit 4.
F/F 4 as clock pulse CKS via 8
It is input to clock terminals CK 2 to 44.

F/Fs 42 to 44 follow this and take in the image data r011J at that time. Then, this F/F
The inverted data r100J of 42 to 44 is held in F/Fs 52 to 54 in synchronization with the clock pulse CKDI, and is sent from each Q terminal to the NAND circuit 59 via OR circuits 55 to 57. F/ by clock pulse CKH
The 3-bit data held by F 60 to 82 is rl
Until it reaches 10J, the NAND circuit 59 is F/F.
A signal “1” is output to the D terminal of 63. This allows F
The signal from the Q terminal of F/F 83 to the set terminal of F/F 64 also becomes "1", so F/F 6
The control signal output from the Q terminal of 4 is also “1”
becomes. Then F/F 60-62 holds 3
After the bit data becomes rl 10J, "111"
Until this happens, the NAND circuit 59 outputs a signal "0" to the D terminal of the F/F 63. This allows F/F
The signal from the Q terminal of F/F B4 to the set terminal of F/F B4 also becomes "0", so the Q of F/F B4 becomes "0".
The control signal output from the terminal also becomes "0". With the above operation, the control signal from the F/F 64 is transmitted at the beginning of 3/8 of one cycle of the reference frequency of 8kHz.
is '1' and the remaining 5/8 is '0', resulting in a pulse width modulation signal with a duty ratio of 3/8. This control signal is converted into a DC voltage via a low-pass 1 filter 2B outside the LSI 29, and is applied to the comparator 22 as a slice voltage C.
Comparator 2
2, for one cycle of the reference frequency of 8 kHz, the reproduced waveform signal S sent is converted into a pulse width modulated wave based on the optimum slice voltage C corrected for fluctuations, and demodulation faithful to the original signal is performed.

Furthermore, the reproduced signal S of the header data inputted to the + side of the comparator 22 is 1/
The signal waveform shown in (b) corresponds to a PWM signal with a duty ratio of 2, and the slice voltage C input to the one side input terminal of the comparator 22 fluctuates for some reason and becomes as shown by the solid line in the figure. If it drops, the output of the comparator 22 will be (C) in Figure 11 (III).
As shown in , a pulse width modulated wave larger than the original PWM waveform signal is obtained. This pulse width modulation wave is F/F
AND circuit 34 and one pulse generation circuit 33 via 32
sent to. The AND circuit 34 has a pulse width modulated wave of “1”.
While #, the clock CK22 is sent to the first pulse generation circuit 85. The first pulse generation circuit 35 sends a clock pulse to the F/F 3B using this clock CK22. F/F 3B to 38 are one pulse generation circuit 33 at the rising edge of the pulse width modulation wave.
The 3-bit image data rcba is reset by a pulse generated from the pulse width modulation wave.
Output J. In this case, the image data rcbaJ is the first
As shown in (d) in Figure 1 (III), rlolJ (
-r5J).

At the same time as identifying the duty ratio of this image data, 8klk
The header data is recognized by the data reading circuit 45 and the 4kHz data reading circuit 46, and the third of the four 8kHz pulses following the first eight 4kHz pulses of the header data is 8kHz. When the data is read by the data reading circuit 45, the output from the Q terminals of F/Fs 47 and 49 is '
1'', which is inputted via the AND circuit 48 to the clock terminals CK of the F/Fs 42 to 44 as a clock pulse CKS.

F/Fs 42 to 44 follow this and capture the image data "101" at that time. Then, this F/F
Inverted data r010J of 42 to 44 is held in F/Fs 52 to 54 in synchronization with the clock pulse CKDI, and is sent to the NAND circuit 59 from each Q terminal via OR circuits 55 to 57. F/ by clock pulse CKH
The 3-bit data held by F60-62 is “10
1", the NAND circuit 59 is F/F6
A signal “1” is output to the D terminal of 3. This allows F/
The signal from the Q terminal of F63 to the set terminal of F/F64 also becomes "1", so F/F64.

The control signal output from the Q terminal also becomes "1". After that, the NAND circuit 59 outputs the signal "0" to the D terminal of the F/F 63 from when the 3-bit data held by F/Fs 80 to 82 becomes "101" until it becomes "111". do. This allows F/F6
The signal from the Q terminal of F/F B4 to the set terminal of F/F B4 also becomes "0°," and therefore the control signal output from the Q terminal of F/F B84 also becomes "0#." With the above operation, the control signal from the F/F 84 has a reference frequency of 8kHz and the first 5/8 of one cycle is "
1”, the remaining 3/8 becomes “0”, and the duty ratio becomes 5/
This results in a pulse width modulation signal of 8. This control signal is converted into a DC voltage via a low-pass filter 28 outside the CPU 29 and sent to one side input terminal of the comparator 22 as a slice voltage C. The optimum slice voltage C is obtained by correcting the fluctuations in the reproduced waveform signal S.
A pulse-width modulated wave is created based on the signal, and demodulation faithful to the original signal is performed.

Therefore, according to the present embodiment, (vertical 224 dots) x (horizontal 144 dots) x (3
Since it records the amount of information (bit) x (3 colors), it is approximately 580
2000 to 9600 bps, which can achieve a transfer speed of 00 bps, and has been put into practical use in the computer field.
You can get much faster transfer speeds than

[Effects of the Invention] As detailed above, according to the present invention, both a television video signal and an audio signal are recorded on a compact cassette tape, the reproduced video signal is displayed on a liquid crystal display panel, and the audio is emitted from a speaker. In the demodulation circuit of the recording and reproducing device, header data that is composed of a PWM signal with a predefined duty ratio and is attached to the beginning of the reproduced signal for each specific unit is recognized,
By controlling the comparison point of a comparator that converts the reproduced signal into a PWM signal according to the identification result of the duty ratio of the header data, a PWM signal faithful to the original PWM signal before recording is demodulated from the reproduced signal. Therefore, it is possible to provide a demodulation circuit for a simple playback device that can follow the playback signal at high speed and prioritizes transfer speed.

[Brief explanation of the drawing]

The drawings show an example of an embodiment of the present invention.
6 to 6 are diagrams showing the recording format of the recording/reproducing device, FIG. 7 is a block diagram showing the schematic configuration of the circuit, FIG. 8 is a timing chart showing each signal waveform in FIG. 7, and FIG. A block diagram showing the detailed circuit configuration, Fig. 10 is a diagram showing the waveform of Herada data, Fig. 11 is a diagram showing the signal waveform according to each state in Fig. 9, and Fig. 12 is the waveform of PWM image data. FIG. 21, 23...Amplifier, 22...Comparator, 2
8...Low pass filter, filter, 24...Header recognition circuit, 25...Duty ratio identification circuit, 26.
...Header data storage circuit, 27...Pulse width modulation output circuit, 29...LSI. 30... Magnetic tape, 31... Magnetic head, 32.
36~38°42~44.47.49.50.52~5
4.60-64...F/F. 33... One pulse generation circuit, 34.48... AND circuit, 35... First pulse generation circuit, 39...
Second pulse generation circuit, 40...8 Reading circuit, 45
...8 kHz data reading circuit, 4B...4kHz
Z data reading circuit, 51...4 reading circuit, 55-5
7...OR circuit, 59...NAND circuit. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 (A) Figure 2 (.) ゛''77■ しくd) -``し》]- Figure 3 Figure 4 Figure 5 (A) Figure 6 Figure 8

Claims (1)

[Claims] Consisting of a PWM signal with a predefined duty ratio,
header recognition means for recognizing header data added to the beginning of a reproduced signal for each specific unit; duty ratio identification means for identifying the duty ratio of the header data according to the recognition result of the header recognition means; and the duty ratio identification means. 1. A demodulating circuit for a reproducing apparatus, comprising: control means for controlling a comparison point of a comparator that converts a reproduced signal into a PWM signal according to the identification result of the means.