JPH01311472A - Demodulation circuit for reproducing device - Google Patents

Abstract

PURPOSE:To demodulate a PWM signal with fidelity to an original PWM signal by demodulating a reproducing signal to digital data based on the number of counting of pulse width of the reproducing signal made into PWM, and correcting a demodulation signal. CONSTITUTION:Reproducing tape data 71 is inputted and the PWM signal can be obtained at an FF 72. While the signal is being outputted, a clock pulse CK2 is sent to binary counters 77 and 94 with eight stages. A pulse generation circuit 89 outputs a one-pulse signal (d), respectively when the count value of the counter 77 arrives at a prescribed value. Binary counters 93 and 97 with three stages count the signal, and the count values of the counters 93 and 97 are sent to FFs 112 and 114, respectively. And when a counter 90 shows the value of pulse width of the PWM signal, a pulse generation circuit 98 sends a signal (s) to the FF 114. The FF 114 reads the count value of the counter 93 by signal (s). The data is inverted and outputted. Meanwhile, the correction value of PWM data can be obtained by inverting 113 the read value of the counter 97 by the FF 112.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a demodulation circuit for a reproducing apparatus that records and reproduces image data using a magnetic tape.

[Conventional and technology] In recent years, portable cassette tape recorders have become popular.

This cassette tape recorder uses a compact cassette tape for audio and can only listen to audio, but there is a desire to display not only audio but also video. For example, it may be possible to display a singer's face or image in time with the music, or to display sample English conversation sentences. For this purpose, it is conceivable to incorporate a so-called VTR using a 1/2 inch wide magnetic tape, but this would increase the size of the device, so it is desirable to record images on a compact cassette tape. Considering the capacity of the tape, this is technically possible if still images are recorded intermittently.

[Problems to be Solved by the Invention] However, when recording digital data on a magnetic tape and reproducing it, a normal reproduction signal may not be obtained due to code amount interference, dropout, or the like. In general, in digital magnetic recording devices, even a single bit error can completely change the meaning of the data, so strict waveform shaping is required, and various waveform equalization circuits have been proposed.

On the other hand, when recording an image signal, although some hit errors do not cause visual problems, an extremely high data transfer rate is required because the image signal has a large amount of information. However, since conventional methods place emphasis on accuracy, there is a problem in that the transfer speed is slow.

For example, in the computer field, the transfer rate is generally 20
However, when recording image signals, a transfer speed of 50,000 bps or more is required.

This invention was made in view of the above circumstances,
The present invention aims to provide a demodulation circuit for a simple playback device that prioritizes transfer speed.

[Means and effects for solving the problems] The present invention provides a playback method in which both a television video signal and an audio signal are recorded on a compact cassette tape, the reproduced video signal is displayed on a liquid crystal display panel, and the audio is emitted from a speaker. In the demodulation circuit of the device, the pulse width of the PWM-converted playback signal is counted by a pulse width counter, and based on this count, the playback signal is demodulated into n-bit digital data, and the basic period of the playback signal is determined by the basic period counter. It counts, and from this count it determines whether or not it is necessary to correct the demodulated digital data, and if it is necessary, in which direction the correction should be made, plus or minus,
By correcting the demodulated digital data according to the determination result, a PWM signal faithful to the original PWM signal before recording can be demodulated from the reproduced signal.

[Embodiment] Hereinafter, the present invention will be described in which the present invention is equipped with a tape recorder section using a compact cassette tape and a liquid crystal television section using a liquid crystal display panel. An embodiment in which the present invention is applied to a recording and reproducing apparatus that displays images and emits audio from a speaker will be described with reference to the drawings.

First, the recording and playback format of the cassette tape of the recording and playback device of the present invention will be explained with reference to FIGS. 1 to 6.
Ru.

FIG. 1 shows a sampling state of a color video signal obtained by receiving a TV broadcast. As shown in (a) and (b) of the same figure, one screen is obtained at a rate of one image per 1/60 seconds (
For example, if the number of display dots on a liquid crystal display panel is 224 vertically x 144 horizontally, the video signal for IV) is 26
Just under 20 of the 2.5 horizontal scanning lines on the top and bottom are cut, and 224 lines are used as effective video signals as shown in FIG. 1(c). In this case, the - horizontal operation time IH is the first
As shown in figure (d), 1/15750 seconds (-160X
12B2.5). From this video signal between IH,
The number of dots in the horizontal direction of the above liquid crystal display panel is 144 x 3 (
432 pieces of data determined by RGB) are sampled and converted into PWM, and the sampling frequency at that time is <6.8 MHz as shown in FIG. 1(f). Also,
The number of quantization bits at this time is 3, indicating 8 levels of gradation.

Figure 1(e) shows the image data rR for each color obtained in this way.
IJ rGIJ rBIJ rR2J rG2JrB2
J rR3J rG3J rB3J・・・・・・
rRl, 44J rG144J rB144J, and the obtained data is sent to the next stage processing circuit as two data columns as shown.

FIG. 2 shows a recording format of the video data obtained by sampling in FIG. 1 above onto a cassette tape. Conventional audio cassette tapes have a 4-track, 2-channel head system, which is A/
Previously, recording/playback was performed on 8 double sides, but now there are 4 tracks and 4 channels, including video tracks, and recording/playback is performed on only one side of the cassette tape. This is 1
Either one track is used for audio and the remaining three tracks are used for video, or two tracks are used for stereo audio and two tracks are used for video.

FIG. 2 shows the track configuration when one of the four tracks is used for audio and three tracks are used for video. As shown in Figure (A), the first track contains the audio data, the second track contains the R information of the color video data, the third track contains the G information, and the fourth track contains the R information of the color video data.
The same B information is recorded on the track. The RGB information of the second to fourth tracks has the data format shown below. In other words, each piece of RGB information is arranged as shown in the diagram, dividing 244 pieces of IH data (144 dots in one horizontal row) with data for division called headers and separators intervening, and creating data for one screen. That is. In each IH data, as shown in Figure 2 CB), 144 dots of data R1 to R144, Gl
~G144°81~B144 are sequentially recorded for each track.

Each of these dot data is recorded as a 3-bit 8-gradation PWM signal as described above.

FIG. 3 shows the signal structure of the header. The header contains one screen worth of video data (
1v), and is placed at the beginning of Figure 3(
As shown in a), it is composed of a combination of a 4 kHz pulse, an 8 kHz pulse, and a 4 kHz pulse. That is, the first 4kHz pulse is 8 shots each with a duty ratio of 172, as shown in Figure 3(b), followed by < 8k pulses.
As shown in Figure 3 (C), 4 Hz pulses are fired each with a duty ratio of 1/2, and finally a 4 kHz pulse is fired as shown in Figure 3 (C).
As shown in d), there are four shots each with a duty ratio of 1/2.

FIG. 4 shows the signal configuration of the separator.

The separator is attached after the IH data stored in the track to separate it from the next data, and is composed of only 4 kHz pulses as shown in FIG. 4(a). That is, as shown in FIG. 4(b), it consists of four consecutive 4kHz pulses.

The following FIG. 5 shows the signal waveform of the video data.

As mentioned above, the video signal is a 3-bit, 8-gradation PWMIJ signal whose fundamental frequency is f. -8kHz.

In addition, although Fig. 2 above shows a case in which one of the four tracks recorded on the tape is used for audio and the remaining three tracks are used for video, two tracks are used for stereo audio and two tracks are used for video. You can. in this case,
As shown in FIG. 6(A), the right (R) channel audio data is on the first track, the left (L) channel audio data is on the second track, and the third and fourth tracks are as shown in FIG. , the header and separator shown in FIG. 4 are interposed, and the color video data in the arrangement shown in FIG. 1(e) is recorded, respectively. If this is done, the tape length required for one screen of video data will be 372 times that of the example shown in Figure 2 above, and the display time for one still image will also be 3/2 times that of the example shown in Figure 2 above. It can be listened to in stereo, and can support audio multiplex broadcast programs.

Next, the configuration of a demodulation circuit that demodulates the reproduced data into a PWM signal before recording when reproducing the recorded data as described above will be described.

FIG. 7 shows a schematic configuration of the demodulation circuit, in which reproduced tape data 71 based on a 3-bit PWM signal reproduced from the tape is first input to the D terminal of the F/F 72.

The clock pulse CKI, which is the basic clock for the entire device, is input to this F/F 72 as an operating clock, and the output a from the Q terminal is sent to an AND circuit 73 and a latch circuit 7.
4 and the reset terminal of F/F 75, and the output from the Q terminal is sent to a NOR circuit 76, respectively. This NOR circuit 76 also has another clock that serves as the basic clock for the entire device.
Latch circuit 7 operated by two clock pulses CK2
The output from 4 is input, and the output is sent to an 8-stage binary counter 77 and AND circuits 78 and 79. A clock pulse CK2 is also input to the AND circuit 73, and its output is sent to the 8-stage binary counter 77 as a count clock. F/F 75 is 1
The output from the Q terminal is connected to the AND circuits 80 to 83 and the AND circuit 7.
8, the output from the Q terminal is connected to its own D terminal and the latch circuit 8.
4, sent to the AND circuit 79 and AND circuits 85 to 88, respectively. The 8-stage binary counter 77 is reset by a signal from the NOR circuit 76, and the AND circuit 7
The 8-bit count value is read out to the pulse generating circuit 89. In the pulse generation circuit 89, the count value of the 8-stage binary counter 77 is r46J r56J
r66J r76J r86Jr96J r106J
When , one pulse d is sent to the AND circuit 81. H
Output to. The output of the AND circuit 78 is sent to the reset terminal of the 8-stage binary counter 90, the NOR circuits 91 and 92, and the reset terminal of the 3-stage binary counter 93.

The output of the AND circuit 79 is an 8-stage binary counter 94.
, the NOR circuits 95 and 96, and the reset terminal of the three-stage binary counter 97. Clock pulse CK2 is input to the AND circuit 80, and its output is sent to the 8-stage binary counter 90 as a count clock. The 8-stage binary counter 90 is reset by the signal from the AND circuit 78, and the AND circuit 8
The 8-bit count value is read out to the pulse generation circuit 98. The pulse generating circuit 98 outputs one pulse h to the NOR circuit 100 when the count value of the 8-stage binary counter 90 reaches r140J, and outputs one pulse g to the NOR circuit 99 when the count value reaches r180J. Clock pulse CK 2 is manually applied to the AND circuit 85,
The output is sent to the 8-stage binary counter 94 as a count clock. The 8-stage binary counter 94 is reset by a signal from the AND circuit 79 and counts the clock pulse CK2 sent through the AND circuit 85, and its 8-bit count value is read out to the pulse generation circuit 101. . Pulse generation circuit lot
The count value of the 8-stage binary counter 94 is r140J.
When this happens, one pulse j is sent to the NOR circuit 103 and "18
0'', one pulse l is output to the NOR circuit 102. The latch circuit 84 latches the output from the Q terminal of the F/F 75 using the clock pulse CK2 and sends it to the latch circuit 104. The launch circuit 104 latches the output from the latch circuit 84 using the clock pulse CKI and outputs it to the NOR circuit 105, while sending an inverted output to the NOR circuit 106 and the latch circuit 107. The latch circuit 107 is activated by the clock pulse CK2.
Latch the inverted output from 4 and send the output to NOR circuit 10
5, the inverted output is sent to the NOR circuit 106. and,
The output e of the NOR circuit +05 is the output of the NOR circuit 103, 96.
The output f of the NOR circuit 106 is the same as the NOR circuit 100,
Sent to 92. The above Noah circuit 10 ports and 91. NOR circuits 99 and 92, NOR circuits 103 and 95, and NOR circuits 102 and 96 are F/F by inputting each other's outputs.
The output of the NOR circuit 100 is sent to the AND circuit 8B, the output of the NOR circuit 99 is sent to the three-stage binary counter 93, the output of the NOR circuit 92 is sent to the AND circuit 87, and the output m of the NOR circuit 103 is sent to the AND circuit 8B. AND circuit 82, NOR circuit 1
The output n of 02 is sent to a three-stage binary counter 97, and the output of the NOR circuit 96 is sent to an AND circuit 83. The outputs of AND circuits 81 and 86 are both input to a NOR circuit 108, and the output of this NOR circuit 108 is sent to an AND circuit 109. The output of the AND circuit 87 is also input to the AND circuit 109, and the output 0 is the output from the three-stage binary counter 9.
3 as a count clock. In addition, the outputs of the AND circuits 88 and 82 are both input to the NOR circuit 110,
The output of this NOR circuit 110 is sent to an AND circuit Ill. The output of the AND circuit 83 is also input to the AND circuit 111, and its output p is sent to the three-stage binary counter 97 as a count clock. The three-stage binary counter 93 is reset by the output of the AND circuit 78, and is designated as up-counting/down-counting by the output l of the NOR circuit 99, and counts the signal 0 from the AND circuit 109. The value q is F
/F sent to 112. The F/F 112 reads the 3-bit count value q using the signal t outputted by the pulse generation circuit 101 when the count value of the 8-stage binary counter 94 reaches "20", and inverts it via the inverter circuit 113. Then, it is output to the next stage processing circuit as 3-bit output data U of D1 to D3. Also, above 3
The stage binary counter 97 is reset by the output of the AND circuit 79, and is designated as up-counting/down-counting by the output n of the NOR circuit 102.
The 3-bit count value r is sent to the F/F 114. F
/F 114 reads the 3-bit count value r using the signal S outputted by the pulse generation circuit 98 when the count value of the 8-stage binary counter 90 reaches "20", and inverts it via the inverter circuit 115. , D1-D3
It is output to the next stage processing circuit as 3-bit output data U.

Here, the basic clock used in the above circuit and the timing of pulse width modulation data created by other circuits during recording will be explained using diagram S8.

As shown in (a) and (b) in the same figure, the clock pulse CK
Both I and CK2 have a frequency of 1.28MHz, and 1/
This is a basic clock having a phase difference of two periods. Three-bit pulse width modulation data is created in synchronization with the rising edge of this clock pulse CK2, and one cycle thereof corresponds to 160 pulses of the clock pulse CK2. PWMI to 8 shown in FIGS. ) from the 0th to the 39th shot of clock CK2 “
"L" level falls when H" level 40 shots 0. Data r
As shown in FIG. 8 (1), PWM2 indicating 0012J falls to the "H° level" from the 0th to the 49th stroke of the clock CK2, and falls to the "L" level at the 50th stroke 0.Similarly, the size of the 3-bit data increases. Accordingly, in synchronization with the rise of the clock pulse CK2 in increments of 10, the level changes from “H” to “L”.
° PWM falling to level and indicating data rll12J
8 is the clock CK2's 0~ as shown in FIG.
The "H" level reaches the 109th shot, and falls to the "L" level at the 110th shot.

When the 3-bit data recorded as described above is recorded on a magnetic tape and is reproduced, the operation is as follows.

First, a case where PWM data with a correct data length that does not require correction is reproduced will be described using the waveform diagram of FIG. 9. Now, by playing back the tape, the reproduced tape data 71 is input, and after synchronization with this circuit is performed by the F/F 72, r3 (0112) Jr4 (1002) as shown in FIG. 9 (1) is input. J r7
It is assumed that a PWNi signal of a data string (1112)J is obtained. The signal a indicating this initial data "3" is F
/F 72 and sent to AND circuit 73, latch circuit 74 and F/F 75. The AND circuit 73 continues to send the clock pulse CK2 to the 8-stage binary counter 77 while the data "3" is at the "H" level. The latch circuit 74 and the NOR circuit 7B detect the rise of this data and output a one-pulse signal shown in FIG. 9(2). Furthermore, the F/F 75, which is a binary counter, inverts the "H° level and 'L" level every data period from the rising edge of this data "3", as shown in FIG. 9 (3). Outputs a signal C. The inverted signal of this signal C is sent to the latch circuit 84°104 as a clock pulse CK.
After being delayed by one clock pulse CK2, the signal is passed through the latch circuit 107 and the NOR circuits 105 and 100, resulting in a delay of one clock pulse CK2 from the rising edge of the signal C, as shown in FIG. 9 (5). One pulse signal e,
A one-pulse signal f as shown in FIG. 9(6)l, which is further delayed by one cycle of the signal a, is obtained from the signal e. The 8-stage binary counter 77 counts the clock pulses CK2 while the data "3" is at the "H#" level based on the output of the AND circuit 73, and the count value may vary slightly depending on various conditions. As shown in FIG. 8 (force) above, it is about 70. This count value is sent to the pulse generation circuit 89, and the pulse generation circuit 89 generates a one-pulse signal d as shown in FIG. Output. These three one-pulse signals d are F/F 75
The output signal C is sent from the AND circuit 81 whose gate is in an open state to the three-stage binary counter 93 via the NOR circuit 108 and the AND circuit 109 as a signal 0 as shown in FIG. 9 (15). 3-stage binary counter 9
3.97 is reset alternately every cycle of the signal a, similar to the eight-stage binary counter 90.94, by the one-pulse signal output from the NOR circuit 76. Here, the 3-stage binary counter 93 is reset, and when the signal O shown in FIG. 9 (12) from the NOR circuit 99 is designated to count up, the signal
The stage binary counter 93 sequentially counts the pulses of the signal O as shown in FIG. 9 (17), and converts the count value into "
0(0002)J to r3(0112)J.

The count value of the three-stage binary counter 93 is sent as is to the F/F 112 as a 3-bit signal q.

By the way, during this time, the AND circuit 80 inputs this data "
The number of clock pulses CK2 for one cycle of 3'' is counted by the 8-stage binary counter 90, and the pulse generation circuit 98 has a count value of ``20'' r140J and r18
When it reaches 0J, it is detected and a one-pulse signal is output. Here, the 8-stage binary counter 90 is r14
When the voltage reaches 0J, a one-pulse signal is output as shown in FIG. 9 (8), and the output signal k of the NOR circuit 100 becomes "
After that, the 8-stage binary counter 9
Since it is reset by the AND circuit 78 when 0 becomes r160J, the one-pulse signal g is not output as shown in FIG. 9 (7).

When the count value of the 8-stage binary counter 90 reaches r16UJ, the data of the signal a becomes the next data "4" and is inverted again, and when it becomes "H" level, the rising edge of the data is detected by the latch circuit 74 and the NOR circuit 76. is detected and an 8-stage binary counter is detected by one pulse signal. '14.
The three-stage binary counter 97 is reset. The eight-stage binary counter 77 counts the clock pulses CK2 while the data "4" is at the "H" level based on the output of the AND circuit 73. Although the count value varies slightly depending on the conditions, it is approximately 80 as shown in FIG. 8 (g) above. The pulse generation circuit 89 is an 8-stage binary counter 77
The count value of r46J r56J r66J "7
6'', a one-pulse signal d is output. These four one-pulse signals d are sent to an AND circuit 88 whose gate is in an open state by the output signal C of the F/F 75.
From there, it is sent to a three-stage binary counter 97 as a signal p via a NOR circuit 110 and an AND circuit 111. The three-stage binary counter 97, like the eight-stage binary counter 94, is alternately reset every cycle of the signal a by the one-pulse signal S output from the NOR circuit 7G. Here, the three-stage binary counter 97 is reset, and when the signal p is input with the count-up specified by the signal n shown in FIG. 9 (14) from the NOR circuit 102, the three-stage binary counter 97 As shown in FIG. 9 (18), the pulses of the signal p are sequentially counted, and the count value is set from rO(0002)J to "4(100□)". The count value of the three-stage binary counter 97 remains 3.
It is sent to the F/F 114 as a bit signal r.

During this time, the AND circuit 85 outputs 1 of this data "4".
The number of clock pulses CK2 for a period is counted by an 8-stage binary counter 94, and the pulse generation circuit lo
t has a count value of "20" r140J and r1, respectively.
When it reaches 80J, a one-pulse signal is output. First, when the 8-stage binary counter 94 reaches "20", the pulse generating circuit 101 sends a signal t as shown in FIG. 9 (20) to the F/F 112. The F/F 112 reads the data "3" which is the count value of the three-stage binary counter 93 in accordance with this signal t. This F/F 11
The read data of No. 2 is inverted by the inverter circuit 113 and sent to the next stage as output data U as shown in FIG. 9 (21). Next, when the count value of the 8-stage binary counter 94 reaches r140J, a one-pulse signal j is output as shown in FIG. 9 (10), and the NOR circuit 103
The output signal m becomes "L level," but after that, when the 8-stage binary counter 94 reaches r160J, it is reset by the AND circuit 79, so the one-pulse signal i is not output as shown in FIG. 9 (9). .

When the count value of the 8-stage binary counter 90 reaches r160J, the data of the signal a becomes the next data "7" and is inverted again, and when it becomes "H" level, the rising edge of the data is detected by the latch circuit 74 and the control circuit. 7G is detected, and the 8-stage bar/r counter 77.90.3 is activated by the one-pulse signal.
The stage binary counter 93 is reset. In the 8-stage binary counter 77, the data “
The clock pulse CK2 is counted while "7" is at the H" level. The count value varies slightly depending on the conditions, but as shown in FIG. 8-stage binary counter 77
The count value is r46J r56J r66Jr7
6J r86J r96J r106J, one pulse signal d is output respectively. These seven one-pulse signals d are sent from an AND circuit 81 whose gate is open by the output signal C of the F/F 75 to a three-stage binary counter 93 as a signal 0 via a NOR circuit 108 and an AND circuit 109. . The three-stage binary counter 93 is reset by the one-pulse signal output from the NOR circuit 76, and is designated to count up by the signal from the NOR circuit 99, and in this state, the signal 0 is output.
When inputted manually, the signal 0 is sequentially generated as shown in Fig. 9 (17).
count the pulses of and convert the count value to rO(000
□)'' to r7(ll12)J. The count value of the three-stage binary counter 93 is sent as is to the F/F 112 as a 3-bit signal q.

During this time, the AND circuit 80 outputs 1 of this data "7".
The number of clock pulses CK2 corresponding to the period is counted by an 8-stage binary counter 90, and the pulse generation circuit 9
8 has a count value of "20" r140J and r1
When it reaches 80J, a one-pulse signal is output. First, when the 8-stage binary counter 90 reaches "20", the pulse generating circuit 98 outputs a signal S as shown in FIG.
/F Send to 114. The F/F 114 reads the data "4" which is the count value of the three-stage binary counter 97 in accordance with this signal S. This F/F
The data read by 114 is inverted by an inverter circuit 115 and sent to the next stage as output data U as shown in FIG. 9 (21). Next, when the count value of the 8-stage binary counter 90 reaches r140J, a one-pulse signal is output as shown in FIG. 9 (8), and the NOR circuit 10
The output signal k of 0 becomes the "L" level, and the three-stage binary counter 93 enters a countdown state.

After that, when the 8-stage binary counter 90 reaches r160J, it is reset by the AND circuit 78 and
As shown in FIG. 9 (7), the one-pulse signal g is not output. .

Pulse width modulation data r3J recorded as above
r4J r7J is faithfully reproduced and the output data U
This is obtained as follows.

'Next, the correction operation when the PWM data is reproduced with a longer time will be explained with reference to FIG. Now, by playing back the tape, the reproduced tape data 71 is input manually, and after synchronization with the main circuit is performed by the F/F 72, r3 (
It is assumed that a PWM signal with a data length of J is obtained. This PWM signal is reproduced with the data length longer than originally due to some reason such as elongation of the magnetic tape, as shown by the broken line indicating the normal data length. This signal a is sent to the AND circuit 73, the latch circuit 74 and the F/F
Sent to 75. AND circuit 73 has data “3”
While the clock pulse CK2 is at H" level, the clock pulse CK2 continues to be sent to the 8-stage binary counter 77. The latch circuit 74 and the NOR circuit 7B detect the rising edge of this data, and output the one-pulse signal shown in FIG. 10 (2). The one-pulse signal resets the 8-stage binary counter 77°90.3-stage binary counter 93.In the 8-stage binary counter 77, data "3" is set by the output of the AND circuit 73.
The clock pulse CK 2 is counted while it is at H'' level. The count value is originally "70" as shown in FIG. shall become. Therefore, the pulse generating circuit 89 outputs a one-pulse signal d when the count value of the 8-stage binary counter 77 reaches r46J, r56J, r66J, and r76J, respectively. This four-shot one-pulse signal d, which is one more than the original data, is transmitted from the AND circuit 81 whose gate is open by the output signal C of the F/F 75 via the NOR circuit 108 and the AND circuit 109. It is sent to the three-stage binary counter 93 as a signal 0 shown in FIG. 10 (15).

The three-stage binary counter 93 is reset by the one-pulse signal S output from the NOR circuit 76, and is designated to count up by the signal O from the NOR circuit 99. When the signal O is input manually in this state, ), the pulses of the signal 0 are sequentially counted, and the count values are set from rO(000□) to r4(1002)J. The count value of the three-stage binary counter 93 remains 3.
It is sent to F/F 112 as a bit signal q.

During this time, the AND circuit 80 outputs 1 of this data "4".
The number of clock pulses CK2 for a period is counted by an 8-stage binary counter 90, and the pulse generation circuit 9
8 has a count value of "20" r140J and r1
When it reaches 80J, a one-pulse signal is output. First, when the 8-stage binary counter 90 reaches "20", the pulse generating circuit 98 outputs a signal S as shown in FIG.
/F Send to 114. The F/F 114 reads the previous reproduction data, which is the count value of the three-stage binary counter 97, in accordance with this signal S. This F/F1
The data read by No. 14 is inverted by an inverter circuit 115 and sent as output data U to the next stage. Next, when the count value of the 8-stage binary counter 90 reaches r140J, a one-pulse signal is output as shown in FIG. The counter 93 enters a countdown state. In this state, the 8-stage binary counter 9
When 0 reaches r180J, the signal g is output as shown in FIG.
1002)J, the count value corresponding to the original data length becomes ``3(0112)J''.

Thereafter, the next data following this "3" is input as reproduced tape data 71, and the NOR circuit 76 detects the rising edge of the data and outputs a one-pulse signal S.

The one-pulse signal is an 8-stage binary counter 77, 94.
The three-stage binary counter 97 is reset. The eight-stage binary counter 77 counts clock pulses CK2 while the next data is at the "H" level based on the output of the AND circuit 73. The pulse generation circuit 89 outputs a one-pulse signal d according to the count value of the eight-stage binary counter 77. This one-pulse signal d is sent from an AND circuit 88 whose gate is open by the output signal C of the F/F 75 to a three-stage binary counter 97 as a signal p via a NOR circuit 110 and an AND circuit 111. The three-stage binary counter 97 sequentially counts the pulses of the signal p when the signal p is input manually. 3 stage binary counter 97
The count value is directly sent to the F/F as a 3-bit signal q.
Sent to 1!2.

During this time, the AND circuit 85 calculates the number of clock pulses CK2 for one period of this data by the 8-stage binary counter 9.
The pulse generation circuit 101 sends a signal t as shown in FIG. 10 (20) to the F/F 1.12 when the count value reaches "20". F/
The F 112 reads reproduction data "3" which is the count value of the three-stage binary counter 93 in accordance with this signal t.

The data "3" read by the F/F 114 is inverted by the inverter circuit 113 and sent to the next stage as output data U with negative correction for the increased data length as shown in FIG. 10 (21). will be sent to.

Although the pulse width modulation data "3" recorded in this way, which has a longer data length than originally, is initially recognized as "4", it is faithfully reproduced as "3" through negative correction, and is output as output data U. That's what you get.

Next, a correction operation when the PWM data is reproduced with a shorter time will be explained using FIG. 11. now,
By playing back the tape, the playback tape data 7
1 is input, and after synchronization with this circuit is performed at F/F 72, r5 (10
12) Assume that a PWM signal with a data length of J is obtained. This PWM signal is reproduced with the data length shorter than originally for some reason, as shown by the broken line indicating the normal data length. This signal a is sent to the AND circuit 73,
The signal is sent to the latch circuit 74 and F/F 75. While the data “5” is at the “H” level, the AND circuit 73
The clock pulse CK2 continues to be sent to the stage binary counter 77. The latch circuit 74 and the NOR circuit 7B detect the rise of this data and output a one-pulse signal shown in FIG. 11(2). The one-pulse signal resets the 8-stage binary counter 77, 90.3-stage binary counter 93. In the 8-stage binary counter 77, the AND circuit 73
Clock pulses CK2 are counted while data "5" is at "H" level based on the output of . The count value is originally "90" as shown in FIG. 8 (ri) above, but here it is assumed to be, for example, "80" for the above-mentioned reason. Therefore, the pulse generation circuit 89 has a count value of r46J r56Jr of the 8-stage binary counter 77.
66J r76J, one pulse signal d is output respectively. The four one-pulse signals d, which are generated one less than the original data, are generated by the AND circuit 81 whose gate is in an open state by the output signal C of the F/F 75.
11 through the NOR circuit 108 and the AND circuit 109.
Three stage binary counter 9 as signal 0 shown in figure (15)
Sent to 3. The three-stage binary counter 93 is the NOR circuit 7
It is reset by the one pulse signal outputted by 6,
Count up is specified by the signal from the NOR circuit 99, and when the signal O is input in this state, the pulses of the signal O are sequentially counted as shown in FIG. 11 (17), and the count value is set to ro. (0002) J to “4(1)
002) Let it be J. The count value of the 3-stage binary counter 93 is directly input to F/F1 as a 3-bit signal q.
Sent to 12th.

During this time, the AND circuit 80 outputs 1 of this data "4".
The number of clock pulses CK2 for a period is counted by an 8-stage binary counter 90, and the pulse generation circuit 98
The count value is "20" r140J and r18, respectively.
A one-pulse signal is output when it reaches 0J. When the 8-stage binary counter 90 reaches "20", the pulse generating circuit 98 outputs a signal S as shown in FIG. 11 (19) to F/
Send to F114. The F/F 114 reads the previous reproduction data, which is the count value of the three-stage binary counter 97, in accordance with this signal S. The data read by the F/F 114 is inverted by an inverter circuit 115 and sent as output data U to the next stage. It is assumed that this data is then completed before the count value of the 8-stage binary counter 90 reaches r140J, and the next data following this "3" is manually input as the reproduced tape data 71. Therefore, the signals g and h from the pulse generating circuit 98 are as shown in FIG.
) and (8), there is no output, and the three-stage binary counter 93 continues to count up with the count value "4".

When the next data is manually input in this state, a one-pulse signal f delayed by one clock pulse CK2 is output from the NOR circuit 10B in synchronization with this, and this is output from the NOR circuit g2.
, 3 as signal 0 through AND circuit 1117.109
It is input to the stage binary counter 93. The three-stage binary counter 93 changes the count value to r4 (1
002) J to “5 (1012) J.

The eight-stage binary counter 77 counts clock pulses CK2 while the next data is at the "H" level based on the output of the AND circuit 73. The pulse generating circuit 8g outputs a one-pulse signal d according to the count value of the eight-stage binary counter 77. This one pulse signal d is F/F
From the AND circuit 88 whose gate is in an open state by the output signal C of 75 to the NOR circuit llO and the AND circuit ill
is sent to a three-stage binary counter 97 as a signal p. The three-stage binary counter 97 sequentially counts the pulses of the signal p when the signal p is input. The count value of the 3-stage binary counter 97 is the 3-bit ft number q.
It is sent to F/F 112 as a.

During this time, the AND circuit 85 calculates the number of clock pulses CK2 for one period of this data by the 8-stage binary counter 9.
The pulse generation circuit 101 sends a signal t as shown in FIG. 11 (20) to the F/F 112 when the count value reaches "20". F
/F 112 reads reproduction data "5" which is the count value of the three-stage binary counter 93 in accordance with this signal t. The data "5" read by this F/'F 114 is inverted by the inverter circuit 113, and as shown in FIG. It is sent out in stages.

Although the pulse width modulation data "5", which was recorded in this way and has a shorter data length than the original, is initially recognized as "4", it is faithfully reproduced as "5" through positive correction, and is output as output data U. That's what you get.

According to this embodiment, 3 tracks produce (vertical 224 dots) x (horizontal 144 dots) x <i color) x 5 seconds in 5 seconds.
(3 bits) of information is recorded, so approximately 58,000 b
ps transfer speed, which is much higher than the 2000 to 9600 bps that has been put into practical use in the computer field.

[Effects of the Invention] As detailed above, according to the present invention, both a television video signal and an audio signal are recorded on a compact cassette tape, the reproduced video signal is displayed on a liquid crystal display panel, and the audio is emitted from a speaker. In the demodulation circuit of the playback device, the pulse width of the PWM-converted playback signal is counted by a pulse width counter, the playback signal is demodulated into n-bit digital data based on this count, and the basic period of the playback signal is determined by the basic period counter. From this count, it is determined whether or not it is necessary to correct the demodulated digital data, and if so, whether correction should be made in the plus or minus direction. By correcting the demodulated digital data according to the results, it is possible to demodulate a PWM signal that is faithful to the original PWM signal before recording from the reproduced signal, so it is possible to follow the reproduced signal at high speed. It is possible to provide a demodulation circuit for a simple playback device that prioritizes transfer speed.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention, and FIGS. 1 to 6 are diagrams showing the recording format of the recording/reproducing device, FIG. 7 is a diagram showing the detailed circuit configuration, and FIG. 8 is a diagram showing the PWM FIG. 9 is a timing chart showing waveforms of image data, FIG. 9 is a timing chart showing signal waveforms during normal operation, and FIGS. 10 and 11 are timing charts showing signal waveforms during correction. 72, 75. 112, 114...F/F, 73
．． 78~83.85~1ift, +09, Ill
...AND circuit, 71... Reproduction tape data, 74
．． 84.104, 107...Latch circuit, 76°9
+, 92.95.96.99. 100, 102
, 103, 105. 106, 108, 110,...NOR circuit, 77
, 90.94...8-stage binary counter, 89.98
．． 101... Pulse generation circuit, 93.97... 3-stage binary counter, 113°115... Inverter circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 1 (A) 1.
Track (c) 1 Figure 3 Figure 5 1 Track Audio data R
(A) l track audio g
La Nori Figure 6

Claims (1)

[Scope of Claims] A pulse width counting circuit that counts the pulse width of a PWM reproduced signal; demodulation means that demodulates the reproduced signal into n-bit digital data based on the count number of the pulse width counting circuit; and a reproduced signal. a fundamental period counting circuit for counting the fundamental period of the fundamental period counting circuit; a determining means for determining whether or not to correct the digital data demodulated by the demodulating means and the direction of the correction based on the count number of the fundamental period counting circuit; A demodulation circuit for a reproducing apparatus, comprising a correction means for correcting the digital data demodulated by the demodulation means according to a determination result.