JPH0690851B2 - Magnetic recording / reproducing device - Google Patents

Description

The present invention relates to a magnetic recording / reproducing apparatus having a fixed head and capable of processing PCM signals encoded at different sampling frequencies by the same signal processing system.

There are various sampling frequencies for sampling the input signal in a magnetic recording / reproducing apparatus that records and reproduces a PCM signal converted from an audio signal with a plurality of fixed heads, and there is no uniform sampling frequency. .

It would be extremely convenient if PCM signals sampled and encoded at different frequencies could be processed by the same transmission system and signal processing system.

(Object of the Invention) The present invention has been conceived in view of the above, and an object of the present invention is to provide a magnetic recording / reproducing apparatus which can be processed by the same signal processing system regardless of the difference in sampling frequency.

(Structure of the Invention) The present invention is a magnetic recording / reproducing apparatus which converts an analog signal into a PCM code and records it on a magnetic recording medium, detects the recording PCM code and reproduces it into an analog signal. An equalizer amplifier that flattens the frequency within the magnetic tape signal transmission band by changing the frequency characteristic according to the sampling frequency information, a pulse slimming circuit that narrows the output pulse width of the equalizer amplifier to a predetermined width, and the pulse slimming A waveform equalizing means including an integrating circuit for integrating the output of the circuit; a DC regenerating circuit for regenerating DC from the output of the integrating circuit; and comparing the output of the integrating circuit with the output of the DC regenerating circuit. A waveform shaping unit including a level comparison circuit, and a traveling speed of the magnetic recording medium is controlled based on an output of the waveform shaping unit. And a signal processing speed control means for controlling the signal processing speed of the signal processing system based on the output of the waveform shaping means.

Hereinafter, the present invention will be described with reference to examples.

1 (a), (b) and (c) are block diagrams showing the configuration of an embodiment of the present invention. FIG. 1 (a) shows a recording system and FIGS. 1 (b) and (c). ) Indicates the reproducing system, and the magnetic tape drive system is the same and is shown only in the reproducing system.

In one embodiment of the present invention, a case where two-channel analog audio signals are converted into PCM codes and recorded and reproduced will be described as an example.

First, the recording system will be described. The left and right channel analog audio signals supplied to the input terminals INL and INR are supplied to the buffer amplifiers 1 and 2, respectively, and the output of the buffer amplifier 1 is a low-pass filter 3-1 to 3-3-for preventing aliasing noise. It is supplied to 3. Low Pass Filter 3-1
The pass band characteristics of 3 to 3-3 are set corresponding to the sampling frequencies fs1, fs2, and fs3 (for example, 48 kHz, 44.1 kHz, and 32 kHz). Similarly, the output of the buffer amplifier 2 is also supplied to the low-pass filters 4-1 to 4-3. The low-pass filters 4-1 to 4-3 have the same structure as the low-pass filters 3-1 to 3-3.

The outputs of the low-pass filters 3-1 to 3-3 are supplied to the changeover switch circuit S1 which is switched by the switching signal corresponding to the sampling frequency, and the output of the low-pass filters 3-1, 3-2 and 3-3 are supplied according to the sampling frequency. One of the outputs is selected and supplied to the variable gain buffer amplifier 5, and the output of the buffer amplifier 5 is supplied to the sample and hold circuit 7.
Similarly, the outputs of the low-pass filters 4-1 to 4-3 are supplied to the changeover switch circuit S2 which is switched by the switching signal corresponding to the sampling frequency, and the low-pass filters 4-1, 4-2, 4-corresponding to the sampling frequency are supplied. One of the three outputs is selected and supplied to the variable gain buffer amplifier 6, and the output of the buffer amplifier 6 is supplied to the sample and hold circuit 8.

The gains of the buffer amplifiers 5 and 6 are switched and controlled according to the sampling frequency.

The outputs of the sample and hold circuits 7 and 8 are separately supplied to A / D converters 9 and 10. A / D converter 9, 10
The output of is supplied to the storage circuit 13 and stored therein. Memory circuit 13
The data stored in the P check word generator in a predetermined order.
It is sent to the 11 and Q check word generators 12, the P check word and the Q check word are arithmetically generated, and the generated P check word and Q check word are supplied to the memory circuit 13 to be stored therein.
Then, the PCM code is interleaved by changing the reading order. Here, an address generation circuit for transferring data from the storage circuit 13 to the P check word generator 11 and the Q check word generator 12 and a transfer for transferring data from the P check word generator 11 and the Q check word generator 12 to the storage circuit 13 A write address generation circuit and a read address generation circuit of the address generation circuit and storage circuit 13 are omitted.

On the other hand, reference numeral 19 denotes an identification code as sampling frequency information corresponding to the sampling frequency when receiving the control signal output from the system control circuit 14 corresponding to the sampling frequency, for example, fs1 = 48 kHz is “01”, fs2 = 44.1
It is a sampling frequency identification code generator that outputs an identification code of "10" for Hz and "11" for fs3 = 32kHz, and 20 receives a control signal output from the system control circuit 14. The sub-code generating circuit outputs a sub-code, for example, a code corresponding to a music number corresponding to a PCM code, a code indicating the number of bits of the PCM code, and a code corresponding to time and the like.

The output of the sampling frequency identification code generation circuit 19 is supplied to an error correction code generation circuit 21 which generates an error correction code and adds it to the identification code, and the output of the error correction code generation circuit 21 and the output of the sub code generation circuit 20 are selected by a selector 22. To the memory circuit 13 for temporal selection and storage.

The data read from the memory circuit 13 is demultiplexer 25.
And distributed to the recording units 30-1 to 30-17. In this embodiment, the magnetic head has a case of having 18 tracks, and the recording magnetic heads are described as 40-1 to 40-18,
The reproducing magnetic heads are designated as 50-1 to 50-18, and magnetic heads with the same suffix are compatible.

Interleaved output from demultiplexer 25
The PCM code is recorded in the recording units 30-1 to 30-12, and the P check word is recorded in the recording unit.
30-13, 30-14, Q inspection word is recording section 30-15, 30-16
The sampling frequency identification code and the sub code are supplied to the recording unit 30-17.

The recording unit 30-1 receives the output from the demultiplexer 25 and CR
CRC code generation circuit 31-1 for generating C code, frame synchronization code generation circuits 32-1 and 33-1 for generating frame synchronization code, modulator 34-1 for modulation for recording, recording amplifier 35-1 The output of the frame synchronization code generation circuit 32-1, the output of the demultiplexer 25, and the output of the CRC code generation circuit 31-1 are supplied to the selector 33-1 and sequentially output to the modulator 34-1. Supply and modulate. The output of the modulator 34-1 is the recording amplifier 35-1.
And the output of the amplifier 34-1 is supplied to the magnetic head 40-1. The recording units 30-2 to 30-17 are configured similarly to the recording unit 30-1, and the outputs of the recording units 30-2 to 30-17 are individually supplied to the magnetic heads 40-2 to 40-17. There is.

Therefore, the signals obtained by modulating the synchronization code, the interleaved PCM code and the CRC code are supplied to the magnetic heads 40-1 to 40-12, and the signals obtained by modulating the synchronization code, the P check word and the CRC code are supplied to the magnetic head 40-13, The signal supplied to the 40-14 and modulated with the sync code, the Q check word and the CRC code is supplied to the magnetic heads 40-15 and 40-16 and modulated with the sync code, the sampling frequency identification code, the sub code and the CRC code. The signal will be supplied to the magnetic head 40-17.

The signal supplied to the magnetic head 40-18 will be described later.

The system control circuit 14 supplies a switching signal determined corresponding to the sampling frequency to the switching switch circuits S1 and S2 and to the buffer amplifiers 5 and 6 as a gain switching signal by the sampling frequency designating signal supplied from the key switch 15. The system control circuit 14 generates a master oscillator 16, a timing pulse generator 17, a tape running reference signal generator 18, a sampling frequency identification code generating circuit 19, and a tape running reference signal, which will be described later, based on a control signal determined according to the sampling frequency. It is supplied to the speed reference voltage generator 153 via the generator 102 and the reproduction / recording changeover switch 28-1.

Further, the system control circuit 14 supplies a sub code generation signal according to the sub code designation signal supplied from the key switch 15.

Upon receiving the control signal, the master oscillator 16 oscillates at a frequency corresponding to the sampling frequency. The timing pulse generator 17 receives the output of the master oscillator 16 and the control signal from the system control circuit 14 and selects a sampling frequency fs
The output of 1, fs2 or fs3 is output to the sample and hold circuits 7 and 8, and the predetermined timing pulse corresponding to the sampling frequency is output to the A / D converters 9 and 1.
0, P check word generation circuit 11 and Q check word generation circuit 12, write address generator and read address generator of storage circuit 13, multiplexer 25, CRC code generation circuits 31-1 to 31-17, frame synchronization code generation circuit 32-1-32-
17, selectors 33-1 to 33-17, modulators 34-1 to 34-17 sampling frequency identification code generation circuit 19, sub code generation circuit 20,
It is supplied to the error correction code generation circuit 21 and the selector 22.

The tape running reference signal generating circuit 18 receiving the control signal from the system control circuit 14 and the output of the master oscillator 16 outputs the tape running reference signal having a frequency proportional to the sampling frequency, and supplies the tape running reference signal to the recording amplifier 26. To do.
The output of the recording amplifier 26 is supplied to the magnetic head 40-18.

Reference numerals 23 and 24 are non-transmission bit control circuits for setting non-transmission bits to "0". For example, when the outputs of the A / D converters 9 and 10 are 16 bits, A / D conversion is performed when transmitting 14 bits. The lower 2 bits of the outputs of the converters 9 and 10 are deleted, and "0" is inserted at the bit corresponding to the output of the lower 2 bits of the A / D converters 9 and 10. It is controlled by the output of the system control circuit 14 which receives the bit number per word designating signal from 15.

Next, the traveling system of the magnetic tape 46 will be described (see FIG. 1 (b)). The tape running reference signal generating circuit 102, which receives the control signal from the system control circuit 14 and the oscillation output of the master oscillator 16, generates a tape running reference signal.
1 and the output of the comparison circuit 41 is supplied to the servo amplifier 42. The output of the servo amplifier 42 is supplied to the drive circuit 43, the output of the drive circuit 43 is supplied to the capstan motor 44, and the output of the drive circuit 43 drives the cabstan motor 44. 45 is a capstan. A pulse generator 154 is mechanically connected to the capstan motor 44, and the output of the pulse generator 154 is supplied to the comparison circuit 41 via the reproduction / recording changeover switch 28-2. The output of the pulse generator 154 is the playback / recording switch 28-
2 to the frequency-voltage converter 155, and the output of the frequency-voltage converter 155 and the speed reference voltage generator 153.
Is supplied to the servo amplifier 42, and the capstan motor 44 is controlled by the servo amplifier 42 so that the voltages of the both are matched and the phases of both inputs of the comparison circuit 41 are matched.

The reproduction / recording changeover switch is omitted except for the reproduction / recording changeover switches 28-1 and 28-2 described above.

Next, the reproducing system will be described. The signal detected by the magnetic head 50-18 is a tape running reference signal having a frequency proportional to the sampling frequency and is supplied to the amplifier 100. The output of the amplifier 100 is the tape running reference signal reproduction circuit 101.
The output of the tape running reference signal reproducing circuit 101 is supplied to the comparing circuit 41 via the reproducing / recording switch 28-2. On the other hand, the output from the control signal generation circuit 115 described later is supplied to the tape running reference generation circuit 102 instead of the output from the system control circuit 14, and the output from the control signal generation circuit 115 is the reproduction / recording switch 28. -1
Is supplied to the speed reference voltage generator 153 via.

103 is a sampling frequency identification code and sub code demodulation device. The signal detected by the magnetic head 50-17 is the amplifier 1
It is being supplied to 04. The signal detected by the magnetic head 50-17 includes a sampling frequency identification code, a sub code, and the like. The output of the amplifier 104 is supplied to the waveform equalizing circuit 105, and the output of the waveform equalizing circuit 105 is supplied to the waveform shaping circuit 106. The output of the waveform shaping circuit 106 is the bit synchronization detection circuit 107, the frame synchronization detection circuit 108, and the demodulator 109.
Supplied to.

FIG. 2 shows an example of the waveform equalizing circuit 105 and the waveform shaping circuit 106. The waveform equalizing circuit 105 is an equalizer amplifier 105-1 that flattens the frequency within the magnetic tape signal transmission band by changing the frequency characteristic while maintaining the linear phase according to the signal from the control signal generating circuit 115, that is, the content of the sampling frequency identification code. , The delay time of the delay circuit is set according to the content of the sampling frequency identification code, and the pulse width of the output of the equalizer amplifier 105-1 is narrowed to the required width. It comprises a pulse slimming circuit 105-2 and an integrating circuit 105-3 for integrating the output of the pulse slimming circuit 105-2. On the other hand, the waveform shaping circuit 106 is the waveform equalization circuit 1
Direct current regeneration circuit 10 for direct current regeneration from the output signal of 05
6-1 and the output of the waveform equalization circuit 105 and the DC regeneration circuit 106-1
And a voltage comparison circuit 106-2 that compares the output of the voltage comparison circuit 106-2.

FIG. 3 shows the bit synchronization detection circuit 107. The bit synchronization detection circuit 107 receives the output of the waveform shaping circuit 106, and when an edge portion of the output is generated, an edge extraction circuit 107-5 that extracts the edge portion of the signal generated from the output of the frequency divider 107-4,
Edge of output of waveform shaping circuit 106 and edge extraction circuit 107-5
Phase comparison circuit 107-1 and phase comparison circuit 1 that compare the phase with the edge of the signal created from the output of frequency divider 107-4 extracted in
Error amplifier 107-2 for amplifying the phase comparison output of 07-1, a voltage controlled oscillator (VCO) whose free-running frequency is controlled by the content of the sampling frequency detection code and whose oscillation frequency is controlled by the output of the error amplifier 107-2. ) 107-3, a PLL circuit composed of a divider circuit 107-4 for dividing the output of the VCO 107-3.

The output of the demodulator 107 and the output of the bit synchronization detection circuit 107 are supplied to the sampling frequency identification code detection circuit 110 and detect the sampling frequency identification code. The output of the identification code detection circuit 110 is supplied to the error correction circuit 112 and corrects the error of the sampling frequency detection code.
The output of the error correction circuit 112 is supplied to the code discrimination circuit 113 for discriminating the sampling frequency discrimination code, and the code discrimination circuit 1
The output of 13 is a detection frequency counter 114 that detects whether the code corresponding to the sampling frequency detection code is output at least once or more, and detects whether the code corresponding to the sampling frequency detection code is output N times or more and generates an output corresponding to the content of the sampling frequency detection code. It is supplied to the control signal generating circuit 115. The output of the control signal generation circuit 115 is the waveform equalization circuit 105,
127-1 to 127-16, bit synchronization detection circuit 107, 129-1 to 129-1
6, the control circuit 116, the master oscillator 16, the later described decoder 14
8, D / A converters 142 and 143 are supplied to "0" sets 151 and 152 and a timing pulse generation circuit 118. However, D / A converter
The 142, 143 and “0” sets 151, 152 may also receive a control signal from the control circuit 124.

FIG. 4 is a block diagram of the code discrimination circuit 113, the detection number counter 114, and the control signal generation circuit 115.

The code discrimination circuit 113 is a serial / parallel converter 113-for converting the output from the error correction circuit 112 into parallel data.
1. Data detection circuits 113-2 to 113-1 that determine the sampling frequency identification codes corresponding to the sampling frequencies fc1, fc2, and fc3 from the output of the serial / parallel converter 113-1
It consists of 13-4. The data detection circuits 113-2 to 113-4 have sampling frequency identification codes “01”, “10”,
The high potential side of "11" is output to the terminal G11 side, and the sampling frequency identification codes "01", "10", and "11" are output to the terminal G12 side, respectively.

The detection number counter 114 includes data detection circuits 113-2, 113-3, 1
Counters 114-1, 114-2, 114-3 and control circuit 116 for counting the output of each terminal G11 of 13-4 at least once
Counters 114-1 to 114-consisting of a rising edge detection circuit 114-4 for receiving the data forcibly instructing the tape speed output from the device, detecting the rising edge and resetting the counters 114-1 to 114-3. The outputs of 3 are supplied to the controller 116, respectively.

The control signal generation circuit 115 is a data detection circuit 113-2,
N-ary counters 115-1 to 115-3 and N-ary counter 115-1 for counting the output on the terminal G11 side of each of 113-3 and 113-4.
To 115-3 are switched by the output when N counts are made changeover switch circuits 115-5 to 115-7 and changeover switch circuit 115-
Data detection circuit 113-2 to 113 output via 5 to 115-7
-4 and a latch circuit 115-8 for latching the output on the terminal G12 side. The control signal generation circuit 115 also receives the reproduction instruction pulse from the control circuit 116 and is an OR circuit 115-9.
~ 115-11, 115-22, the OR circuit 115-9 is further supplied with the outputs of the counters 115-2 and 115-3,
The OR circuit 115-10 is further supplied with the outputs of the counters 115-1 and 115-3, and the OR circuit 115-11 is further supplied with the outputs of the counters 115-1 and 115-2. circuit
The outputs of 115-9 to 115-11 are counters 115-1 to 115-1, respectively.
115-3 resets a counter which is supplied as a set signal and does not generate an output. Counter 115-1 to 115-3
Of the OR circuit 115-12, the output of the OR circuit 115-12 to the delay circuit 115-13, the output of the delay circuit 115-13 to the controller 116, and the latch pulse to the latch circuit 115-8. Is supplied as a switching signal to the switch circuits 115-14 and 115-15, and the output of the latch circuit 115-8 is output as the output of the control signal generating circuit 115 via the switch circuit 115-14. The data forcibly instructing the tape speed output from the control circuit 116 is supplied to the pattern detection circuit 115-16 and set in the pattern detection circuit 115-16 to detect the pattern, for example, the pattern for fs3 = 32 kHz. 115-16 output is status counter 11
It is supplied to 5-17 and the twice count output is supplied to the controller 116 and the automatic stop display circuit 117. The reproduction instruction pulse from the control circuit 116 is reset by the output differentiated by the differentiation circuit 115-18 to reset the counter 115-17.

The error detection output from the error correction circuit 112 is the OR circuit 115.
The clock pulse is supplied to the flip-flop circuit 115-20 via -19, and the output of the flip-flop circuit 115-20 is supplied to the M-ary counter 115-21 that counts the number of errors. Counter 115-21 that counts the number of errors M times
Is supplied to the OR circuit 115-22, the output of the OR circuit 115-22 is differentiated by the differentiating circuit 115-23, and the latch circuit 115-8 is reset by the differentiated output.

On the other hand, a signal generated for each frame, like the frame synchronization output detected by the frame synchronization detection circuit 108, is supplied to the flip-flop circuit 115-20 as a reset signal, and the state count is reset for each frame. Similar to the frame synchronization output, the signal generated for each frame is simultaneously supplied to the AND circuit 115-24, the output of the AND circuit 115-25 is differentiated by the differentiating circuit 115-25, and the counter 115-
21 is reset, and the output of the counter 115-21 is reset every frame. On the other hand, the inverted output of the flip-flop circuit 115-20 is supplied to the AND circuit 115-24, which resets the counter 115-21 with a signal generated for each frame when an error is detected. Ban.

The output of the demodulator 109, the output of the bit period detection circuit 107 (hereinafter referred to as the bit synchronization signal) and the output of the frame synchronization detection circuit 108 (hereinafter referred to as the frame synchronization signal) are supplied to the sub code decoder 119 and the CRC detection circuit 120, The sub code is detected from the output of the demodulator 109, and the sub code is the sub code register.
Supply to 122. The CRC detection circuit 120 detects an error in the sub code, and when an error is detected, the CRC pointer register 121
The CRC pointer 121 stores a pointer indicating that it is wrong and the CRC pointer register 121 stores the pointer.
The output of is supplied to the sub code register 122, and if there is no pointer in the CRC pointer register, the sub code register sends the error-checked sub code to the control circuit 124 and the display circuit 123,
If there is a pointer, the sub code for which no error was detected before the pointer was set is sent to the control circuit 124 and the display circuit 123. The output of the sub code register 122 is supplied to the display circuit 123 and the control circuit 124, and the content of the sub code registered in the sub code register 122 is displayed on the display circuit 123 and controlled according to the content of the sub code. Control circuit 124, control circuit 124
Is output to select the song number, for example.

Further, the timing pulse generation circuit 111 receives the bit synchronization signal detected by the bit synchronization detection circuit 107 and the frame synchronization signal detected by the frame synchronization detection circuit 108, and receives the frame synchronization detection circuit 108, the demodulator 109, and the identification code detection circuit. A timing pulse corresponding to the output of the bit synchronization detection circuit 107 is supplied to each of the 110, the error correction circuit 112, the code determination circuit 113, and the control signal generation circuit 115.

The output detected by the magnetic heads 50-1 to 50-16 is the playback unit 1
25-1 to 125-16 are supplied separately.

The reproducing unit 125-16 amplifies the detection output from the magnetic head 50-16 and outputs the waveform equalization circuit 127-16 and the waveform equalization circuit 127-16 that equalize the output of the amplifier 126-16. A waveform synchronization circuit 128-16 for shaping, a bit synchronization detection circuit 129-16 for detecting a bit synchronization signal and a frame synchronization signal from the output of the waveform shaping circuit 128-16, a frame synchronization detection circuit 130-16, and a waveform shaping circuit 128-16, respectively. Demodulator 131-16 for demodulating the output of the above, a timing pulse generation circuit 132 for generating a timing pulse from the bit synchronization signal detected by the bit synchronization detection circuit 129-16 and the frame synchronization signal detected by the frame synchronization signal detection circuit 130-16 -16, which are code demodulators 10
Same as 3. The output of the waveform shaping circuit 128-16 is supplied to the CRC detection circuit 133-16. On the other hand, the demodulation output of the demodulator 131-16 is supplied to the register 134-16, and the register 104-16
Temporarily stores the data subjected to the error check by the CRC detection circuit 133-16, stores the pointer output from the CRC detection circuit 133-16 in pair with the data, and sends the data and the pointer to the storage circuit 135-16. The output of register 134-16 is a memory circuit
The address is designated by the write address generating circuit 136-16 and is sequentially stored in the address 136-16. Further, the reproducing section 125-16 receives a generation address of the write address generation circuit 136-16 and a read address generation circuit described later.
The memory circuit 136-16 is provided with a write priority instruction circuit that controls the memory 138 and prioritizes writing. Timing pulse generation circuit 132-16 is a frame synchronization detection circuit 130-16, demodulator
A timing pulse corresponding to the frequency of the bit synchronization signal detected by the bit synchronization detection circuit 129-16 is supplied to each of the 131-16, the CRC detection circuit 133-16, the register 134-16, and the write address generation circuit 136-16.

The reproducing units 125-1 to 125-15 have the same configuration as the reproducing unit 125-16, and the reproducing units 12-1 to 125-12 respectively include the magnetic heads 50-1 to 50-1.
Receives detection output of 50-12 and PCM to storage circuits 135-1 to 135-12
The code is stored and the reproducing units 125-13 to 125-16 are magnetic heads 50-1.
Upon receiving the detection outputs of 3 to 50-16, the P inspection word data and the Q inspection word data are stored in the storage circuits 135-13 to 135-16, respectively.

A read instruction signal generation circuit 139 that generates a data read instruction signal and a deinterleave control signal outputs the data read instruction signal to the read address generation circuit 13
8, and the read address generation circuit 138 stores the read address in a cycle corresponding to the sampling frequency.
It is supplied to 135-1 to 135-16. Memory circuit 135-1 to 135-16
The data read from is supplied to the deinterleave circuit 140, and the data written in the deinterleave circuit 140 is taken into the error correction circuit 156 in a predetermined order, subjected to error correction, deinterleaved in the deinterleave circuit 140, and then corrected in the error correction circuit 140. Supplied to 141.

On the other hand, the timing pulse generator 118 receives the output of the control signal generation circuit 115 and the output of the master oscillator 16, and outputs the read instruction address generation circuit 138, the read instruction signal generation circuit 139, the deinterleave circuit 140, the error correction circuit 156, Timing pulses corresponding to the sampling frequency are output to the error correction circuit 141, the D / A converters 142 and 143, and the deglitchers 144 and 145, respectively.

When the error correction circuit 156 cannot completely correct the error, the error correction circuit 141 corrects the error. When correction is not necessary, the error correction circuit 141 does not perform correction. It is supplied to the converter 142, and the PCM code for the right audio is supplied to the D / A converter 143. D / A converter
The output of 142 is lowpass filtered through deglitcher 144.
146-1 to 146-3, and the output of the D / A converter 143 is supplied to the low pass filter 147-1 to 147-3 via the deglitcher 145.
Supplied to. Low pass filter 146-1 to 146-
The frequency characteristics of 3 and 147-1 to 147-3 are set corresponding to the sampling frequencies.

The output of the control signal generation circuit 115 is supplied to the decoder 148, and the output of the decoder 148 is the low-pass filter 1.
Changeover switch circuit S'1 for selecting one of the outputs of 46-1 to 146-3 and 1 of the outputs of low-pass filters 147-1 to 147-3.
Which is supplied to a changeover switch circuit S'2 for selecting one of the low pass filters 146-1 to 146-3 corresponding to the sampling frequency identification code.
Select the output of 147-1 to 147-3.

The outputs of the changeover switch circuits S'and S'2 are variable gain buffer amplifiers 14 whose gains are switched by the decoding output of the decoder 148 in accordance with the sampling frequency identification code.
It is supplied to 9 and 150 respectively, amplified, and then supplied to the left and right channel output terminals OL and OR.

The D / A converters 142 and 143 receive the output of the control signal generation circuit 115, and when the output of the control signal generation circuit 115 corresponds to the sampling frequency of 32 kHz, P
The output of the non-transmission bit setter that sets the lower 2 bits of the CM code to "0" is supplied.

On the other hand, the non-transmission bit setters 151 and 152 receive the output of the control signal generation circuit 115 and receive the control signal generation circuit 1
When the output of 15 corresponds to the sampling frequency of 32 kHz, when the error correction circuit 156 performs error correction PCM
This is a setting device for making the lower 2 bits of the code "0".

(Operation of the Invention) In the embodiment of the present invention configured as described above, the operation will be described in which the number of words Nw in one frame is 8 words and the PCM code track is 12 tracks as described above.

First, the recording system will be described.

At the time of recording, the sampling frequency instruction and the sub code instruction are performed by the key switch 15, and the system control circuit 14 outputs the switching signal corresponding to the sampling frequency to the switching switch circuits S1 and S2 to switch the switching switch circuit S1. S2 is switched according to the sampling frequency. Therefore, aliasing noise does not occur even if the sampling frequency is changed. The system control circuit 14 also outputs a gain switching signal corresponding to the sampling frequency to the buffer amplifiers 5 and 6, and the gains of the buffer amplifiers 5 and 6 are switched according to the sampling frequency.
Therefore, the difference in loss between the low-pass filters 3-1, 3-2 and 3-3 and the difference in loss between the low-pass filters 4-1, 4-2 and 4-3 are compensated.

On the other hand, the master oscillator 16 which receives the control signal determined in correspondence with the sampling frequency from the system control circuit 14 generates the output of the frequency corresponding to the sampling frequency, and the oscillation output and the control signal from the system control circuit 14 are generated. The tape running reference signal generator 18 which receives the signal generates a tape running reference signal having a frequency proportional to the sampling frequency. The tape running reference signal is amplified by the amplifier 26 and then supplied to the magnetic head 40-18 and recorded on the magnetic tape.

On the other hand, when recording, the playback / recording switch 28-1, 28
-2 has been switched to the contact position shown in FIG. 1 (b).
Control signal from system control circuit 14 and master oscillator
The tape reference signal generation circuit 102 that receives the oscillation output from 16
Outputs a frequency corresponding to the sampling frequency, and the speed reference voltage generator 153 receiving the control signal from the system control circuit 14 outputs a speed reference voltage corresponding to the sampling frequency. In addition, the output of the pulse generator 154 is output to the comparison circuit 4 via the reproduction / recording switch 28-2.
1 and the frequency-voltage transformer 155. Since the magnetic tape 46 is not running at first, there is no one input of the comparison circuit 41 and the output voltage of the frequency-voltage converter 155, the output of the servo amplifier 42 becomes maximum, and the capstan motor 44 is driven with maximum torque. Then, the magnetic tape 46 is run. By this running, the pulse generator 154 generates an output pulse, and the output of the pulse generator 154 is supplied to the comparison circuit 41 and the tape running reference signal generating circuit.
The output frequency of the pulse generator 154 is converted into a voltage by the frequency-voltage converter 155 and supplied to the servo amplifier 42, and the speed reference voltage generator 153
The differential voltage from the output voltage and the output of the phase comparator 41 are added and amplified by the servo amplifier 42, and the servo motor 44 drives the magnetic tape 46 at the traveling speed corresponding to the sampling frequency.

On the other hand, the left and right channel analog audio signals supplied to the input terminals INL and INR are amplified by the buffer amplifiers 1 and 2 and supplied to the low-pass filters 3-1 to 3-3 and 4-1 to 4-3. High frequencies are limited according to the sampling frequency. One of the outputs of the low-pass filters 3-1 to 3-3 and the outputs of the low-pass filters 4-1 to 4-3 is selected by the changeover switch circuits S1 and S2 in accordance with the sampling frequency, and the buffer amplifier 7, Amplified by 8. In this case, the gains of the buffer amplifiers 7 and 8 correspond to the sampling frequency, and the loss difference between the low-pass filters 3-1 to 3-3 and the loss difference between the low-pass filters 4-1 to 4-3 are compensated. To be done.

The outputs of the buffer amplifiers 5 and 6 are supplied to the sample and hold circuits 7 and 8 and sampled and held by the sampling pulse of the frequency designated by the key switch 15. The output of the sample and hold circuits 7 and 8 is A /
The D converters 9 and 10 individually convert the PCM codes into the PCM codes and store them in the storage circuit 13. PCM stored in the memory circuit 13
The symbols are P check word generating circuits 11 and Q in a predetermined order.
The inspection word generating circuit 12 takes in the calculation, loads the P inspection word and the Q inspection word, and stores them in the memory circuit 13. When the number of non-transmitted bits of the PCM code is designated by the key switch 15, the non-transmitted bit “0” is received by the control circuits 23 and 24 from the control circuit 14 and the corresponding non-transmitted bit is set to “0”. To control. This control circuit 2
Reference numerals 3 and 24 control the non-transmission bit to "0" to generate the P check word and the Q check word to calculate the P check word and the Q check word, respectively, and set the non-transmission bit of the PCM code to "0". Control.

The PCM code stored in the storage circuit 13 is interleaved and read out, supplied to the demultiplexer 25, and the recording unit 30.
-Supplied from 1 to 30-12. The P inspection word and the Q inspection word read from the memory circuit 13 are supplied to the demultiplexer 25, and are recorded in the recording units 30-13 and 30-14 and the recording units 30-15 and 30-.
Supplied to 16.

On the other hand, the sampling frequency detection code generator 19 receives a control signal corresponding to the sampling frequency designated by the key switch 15 from the system control circuit 14 and outputs an identification code corresponding to the sampling frequency. The error correction code is added to the code generation circuit 21 and added to the selector 22. Further, the sub code generation circuit 20 receives a control signal designated by the key switch 15 from the system control circuit 14 to generate a sub code, and the sub signal is supplied to the selector 22. The identification code and the sub-code supplied to the selector 22 to which the error correction code is added are selected by the selector 22 and stored in the storage circuit 13, and the identification code and the error correction code read from the storage circuit 13 are added. The sub code is supplied to the demultiplexer 25, and is supplied to the recording unit 30-17 by the demultiplexer 25.

The code supplied to the recording units 30-1 to 30-17 is added with a frame synchronization code and a CRC code, and a predetermined modulation is performed by the modulators 34-1 to 34-
And recorded on the magnetic tape 46 by the magnetic heads 40-1 to 40-17 in the format shown in Table 1 (see page 62). In Table 1, W _N is a PCM code for the left channel analog signal, Wn is a PCM code for the right channel analog signal, P is a P check word, Q is a Q check word, and B is a sampling frequency identification code. S indicates a sub code.

On the other hand, the timing pulse generator 17 receives the control signal from the system control circuit 14 and the oscillation output of the master oscillator 16 and generates various timing pulses corresponding to the sampling frequency. The timing pulse is generated by the A / D converter 9 and 10, P inspection word generation circuit 11, Q inspection word generation circuit
12, write address generation circuit and read address generation circuit of memory circuit 13, demultiplexer 25, CRC code generation circuits 31-1 to 31-17, frame synchronization code generation circuit 32-1
~ 32-17, selectors 33-1 to 33-17, modulators 34-1 to 34-17,
The sampling frequency is supplied to the identification code generation circuit 19, the sub code generation circuit 20, the error correction code generation circuit 21, and the selector 22, and the sampling pulse is supplied to the sample and hold circuits 7 and 8. Therefore, the signal processing is performed at the signal processing speed.

Here, even if the designation of the sampling frequency by the key switch 15 is changed, the magnetic tape 46 is driven at the traveling speed corresponding to the newly designated sampling frequency. The gains of the low-pass filters 3-1 to 3-4, the low-pass filters 4-1 to 4-4, and the buffer amplifiers 5 and 6 are switched according to the newly designated sampling frequency, and the sample-and-hold circuits 7 and 8 are provided. The buffer amplifiers 5 and 6 by the sampling pulse of the newly specified frequency.
Sample and hold the output of. Further, the tape running reference signal 15 is recorded on the magnetic tape 46 in proportion to the sampling frequency newly designated by the magnetic head 40-18. On the other hand, the A / D converters 9 and 10, the P inspection word generating circuit 11, the Q inspection word generating circuit 12, the write address generating circuit and the read address generating circuit of the recording circuit 13, the multiplexer 25, the CRC code generating circuit 31-1 to 31- 31-17,
Frame synchronization code generation circuit 31-1 to 32-7, selector 33-1 to
33-17, modulators 34-1 to 34-17, sampling frequency identification code generation circuit 19, sub-code generation circuit 21, selector 22 outputs to the newly specified sampling frequency output from the timing pulse generator 17. Since the recording format shown in Table 1 does not change and the minimum recording wavelength does not change because it is operated by the corresponding various timing pulses, there is no problem in recording / reproducing.

In addition, in the case of the recording format shown in Table 1, when the sampling frequency is fa1 = 48kHz, PCM of 1mcec is used for one frame.
Codes are stored and 16 per frame when fs2 = 44.1kHz
When the PCM code for 0/147 msec is fs3 = 32 kHz, the PCM code for 1.5 msec is stored in one frame.

Next, the operation of the reproduction system will be described.

When switching to reproduction, that is, when reproduction is instructed by the key switch 15, reproduction is instructed to the system control circuit 14. The reproduction / recording changeover switches 28-1 to 28-2 are switched from the reproduction example, that is, the contact position shown in FIG. 1B by the output of the system control circuit 14 in synchronization with the reproduction instruction. On the other hand, the reproduction instruction output of the key switch 15 is the control circuit 11
It is supplied to 6 and a reproduction instruction is given. At this point the magnetic tape 46 has not yet been driven.

From the control circuit 116 to which the reproduction instruction is given, a reproduction instruction pulse is supplied to the OR circuits 115-9 to 115-11 and 115-22, and at the same time, the identification code corresponding to the sampling frequency 44.1 kHz is given for a predetermined period (t1), It is forcibly supplied to the switch circuit 115-15. Counter 115-1 to 1 by the former playback instruction pulse
15-3, 115-17 and the latch circuit 115-8 are reset, the latter is detected by the rising edge detection circuit 114-4 of the identification code, and the counters 114-1 to 114-3 are reset by the detection output (fifth). Step a) in the figure. The latter identification code is output as an output of the control signal generation circuit 115 via the switch circuit 115-15. This output is supplied to the tape running reference signal generation circuit 102 instead of the control signal of the system control circuit 14, and also supplied to the speed reference voltage generator 153 through the reproduction / recording changeover switch 28-1, and at the same time, the master oscillator 16
Is supplied instead of the control signal of the system control circuit 14.
As a result, the master oscillator 16 oscillates at a frequency corresponding to the sampling frequency corresponding to the sampling frequency identification code. Receiving the output of the control signal generating circuit 115 and the oscillation output of the master oscillator 16, the tape running reference signal generating circuit 102 generates an output of a frequency corresponding to the sampling frequency, and the speed reference voltage receiving the output of the control signal generating circuit 115. The generator 153 generates an output of a voltage corresponding to the sampling frequency. However, with the capstan motor 44 stopped, the tape running reference signal reproduction circuit
101 is not producing any output. This is a state in which the signal from the pulse generator 154 at the time of recording replaces the output of the reference signal reproducing circuit 101, and the capstan motor 44 is rotationally driven with the maximum torque as in the case of the recording start, and the magnetic tape 46 is used. Starts running. When the capstan motor 43 is rotationally driven, the tape running reference signal reproducing circuit 101 amplifies the output detected by the magnetic head 50-18 and generates a reproduced output. The output of the tape running reference signal reproduction circuit 101 is supplied to the comparison circuit 41 and the frequency-voltage converter 155 via the switch 28-2. As a result, the capstan motor is phase-cycled to the output of the tape running reference signal generating circuit 102 and is always capped so that the difference between the output voltage of the speed reference voltage generator 153 and the output of the frequency-voltage converter 155 always converges to zero. The stun motor 44 is driven to rotate at a rotation speed corresponding to the controlled sampling frequency. Even when the output of the control signal generator 115 generates the output of another sampling frequency identification code, the capstan motor is rotated at the rotation speed corresponding to the content of the sampling frequency identification code.
44 rotates, and the magnetic tape 46 runs at a running speed corresponding to the sampling frequency.

Therefore, following step a, the period t1 sampling frequency
The magnetic tape 46 is driven at a speed corresponding to fs2 = 44.1 kHz (step b). The output detected by the magnetic head 50-17 is amplified by the amplifier 104, the amplified output is equalized by the waveform equalization circuit 105 in response to the content of the identification code of the sampling frequency 44.1 kHz, and the waveform shaping circuit 106 shapes the waveform. To be done. Here, the equalizer amplifier 105-1 is a circuit that flattens the frequency characteristics of the required frequency occupied band of the signal supplied from the amplifier 104, and the pulse slimming circuit 105-2 is the pulse of the signal supplied from the equalizer amplifier 105-1. A control signal generation circuit because the required occupied band of the signal supplied from the amplifier 104, which is a circuit for narrowing the width to the required width, and the pulse width of the output signal of the equalizer amplifier 105-1 change if the sampling frequency is different.
The frequency characteristic of the equalizer amplifier and the delay time of the delay circuit which constitutes the pulse slimming circuit 105-2 are varied according to the contents of the sampling frequency identification code by the control signal from 115. Further, the integrating circuit 105-3 is provided because the characteristics of the magnetic tape at the time of recording exhibit a differential characteristic, and the pulse slimming is performed and then integrated to compensate the differential characteristic. Further, the DC shaping circuit 106-1 is provided in the waveform shaping circuit in order to perform the so-called DC level regeneration by comparing the positive half wave and the negative half of the DC level of the output signal of the integrating circuit 105-3. is there. Wave shaping circuit
In 106, the output of the waveform equalizing circuit 105 is a DC regenerating circuit 106-
Since the waveform is shaped by comparing with 1, the waveform is reliably shaped even if there is a change in the DC level.

The bit synchronization detection circuit 107 and the frame synchronization detection circuit 108 detect the bit synchronization signal and the frame synchronization signal from the output of the waveform shaping circuit 106. The bit sync signal is detected by detecting the edge of the output of the waveform shaping circuit 106 and the VCO 10 as shown in FIG.
The output of 7-3 is frequency-divided and the signal edge created by frequency divider 107-4 is phase-compared and detected. The free-running frequency of the VCO 107-3 is switched by the sampling frequency identification code.

Bit sync signal and frame sync signal are supplied,
The output of the waveform shaping circuit 106 is demodulated by the demodulator 109.
This demodulated output is a sampling frequency identification code and a sub code, and the error correction circuit 112 performs error correction,
The data is supplied to the serial / parallel converter 113-1 and converted into parallel data, and then supplied to the data detection circuits 113-2 to 113-4. If the demodulated sampling frequency identification code corresponds to the 44.1 kHz sampling frequency, an output is generated at the terminal G11 of the data detection circuit 113-2 and the counter 114-1 counts it at least once. Output α
To occur. Receiving the output α, the control circuit 116 detects the data of the sampling frequency fs2 = 44.1 kHz at least once within the predetermined period (t1) (step c), and the control circuit 11
6 is the output of the code corresponding to the sampling frequency of 44.1 kHz to the tape running reference signal generation circuit 102 and the speed reference voltage generator 153 through the switch circuit 115-15 for a predetermined period (t2) from the time when the output α is received. To do. As a result, the speed of the magnetic tape 46 is fixed to the tape running speed corresponding to Fs2 = 44.1 kHz for a predetermined period (t2) (step d). Within this predetermined period (t2), the counter 115-1 has a sampling frequency of 44.
When counting the identification code of 1 kHz, the counter 115-1 generates an output. The changeover switch circuit 115-5 is changed over by this output of the counter 115-1 and the data detection circuit 113-2 is changed.
Output from terminal G12, that is, sampling frequency 44.1k
The identification code of Hz is supplied to the latch circuit 115-8. On the other hand, the output of the counter 115-1 is supplied to the delay circuit 115-13 via the OR circuit 115-12 while resetting the counters 115-2 and 115-3 via the OR circuits 115-10 and 115-11. . The delay circuit 115-13 receives this signal and generates a signal at its output that is delayed by a predetermined time from the signal supplied from the OR circuit 115-12. The output signal of the delay circuit 115-13 is supplied to the control circuit 116. The state where the detection code of the sampling frequency 44.1 kHz is detected N times is notified (step e). The output of the delay circuit 115-13 is also supplied to the latch circuit 115-8 and the data detection circuit 113-2.
The output from the terminal G12 is latched in the latch circuit 115-8. At the same time, the switch circuits 115-14 and 115-15 are switched by the output of the delay circuit 115-13, and the latch circuit 115-8.
The latch output of the identification code of 44.1 kHz is supplied to the tape running reference signal generation circuit 102 and the speed reference voltage 153 instead of the output from the control circuit 116,
Magnetic tape running speed is sampling frequency fs2 = 44.1kHz
The speed is controlled to correspond to (step f).

On the other hand, the error detection output from the error correction circuit 112 is supplied to the flip-flop 115-20 via the OR circuit 115-19, the output of the flip-flop 115-20 is counted by the counter 115-21, and Fs2 = 44.1kHz. The number of corrections of the identification code of the sampling frequency is monitored (step g). When the error detection output is detected M times, the counter 115-21 generates an output (step h), the output of the counter 115-21 is supplied to the control circuit 116 and the automatic regeneration is stopped, and at the same time, the counter 115-21 outputs. The output is supplied to the automatic stop display circuit 117 to display the automatic regeneration stop (step i). At the same time, the output of the counter 115-21 is supplied to the latch circuit 115-8 via the OR circuit 115-22 and the differentiating circuit 115-23, and the latch circuit 115-8 is reset. On the other hand, when no error is detected by the error detection circuit 112 in step h or until the number of times reaches M times, steps f to h are repeated and the running speed of the magnetic tape is 4 times.
The speed is controlled to correspond to the sampling frequency of 4.1kHz.

The above is the case where the magnetic head 50-17 detects the identification code having the sampling frequency of 44.1 kHz. If the magnetic head 50-17 does not detect the identification code of the sampling frequency 44.1 kHz, the identification code of the sampling frequency 32 kHz is detected from step C, that is, the output of the counter 114-3 is detected (step C2), and the sampling frequency 32 kHz is detected. When the identification code of is detected, step C2
Then, steps d2, e2, f2, g2, h2 and i are executed. This is similar to steps d, e, f, g, h, i. In step C2, the sampling frequency is 32kH.
When the identification code of z is not detected at least once,
Or in step e, sampling frequency is 44.1kHz
If the identification code of is not detected N times, step C2
Subsequent to, or following step e, the running speed of the magnetic tape is set to a speed corresponding to a sampling frequency of 48 kHz for a predetermined period (t1) (step b1), and the sampling frequency of 48 kHz is set within the predetermined period (t1) in step C1. When the identification code is detected at least once (step C1), the steps d1, e1, f1, g1, i are subsequently executed. If the identification code with the sampling frequency of 48 kHz is not detected once in the predetermined period (t1) in step C1, or if the identification code with the sampling frequency of 48 kHz is not detected N times in the predetermined period (t2) in step e1, Following C1 or step e1, the control circuit 116 outputs a code corresponding to the sampling frequency 32 kHz as an output signal of the control signal generation circuit 115 for a predetermined period (t1), and (step b2) within the predetermined period (t1). When the detection code having the sampling frequency of 32 kHz is detected at least once (step j), the step d2 is subsequently executed. When the identification code with the sampling frequency of 32 kHz is not detected in step j, or
e2 sampling frequency N times within a predetermined period (t2)
If the 32 kHz identification code is not detected, step k is executed. That is, the code corresponding to the sampling frequency 32 kHz supplied from the control circuit 116 is detected by the pattern detection circuit 115-16 and counted by the counter 115-17. When the count value of the counter 115-17 is "2", that is, when the sampling frequency identification code is not detected as expected even if the same operation is repeated twice, step i is executed and the count value of the counter 115-17 is "2". If less than, step 6 is executed again.

As described above, the running speed of the magnetic tape 46 is controlled to a speed corresponding to the content of the sampling frequency identification code detected by the magnetic head 50-17, that is, the sampling frequency.

The output of the control signal generation circuit 115 is the waveform equalization circuit 10.
5, since it is supplied to the bit synchronization detection circuit 107, the master oscillator 16, and the timing pulse generation circuit 118, the frequency characteristic of the waveform equalization circuit 105, the VCO 107 of the bit synchronization detection circuit 107.
The −3 free-running frequency, the oscillation frequency of the master oscillator 16, and the timing pulse output from the timing pulse generation circuit 118 are switched according to the sampling frequency.

The output of the demodulator 109 is supplied to the sub-code decoder 119 and the CRC detection circuit 120 together with the bit synchronization signal and the frame synchronization signal, and the sub-code in the output of the demodulator 109 is decoded by the sub-code decoder 119 and the decoded output is output. Is registered in the sub code register 122. An error in the sub code is detected by the CRC detection circuit 120, and the pointer set there is supplied to the CRC pointer register 121. The CRC pointer 121 sends a control signal to the sub code register 122, and when there is a pointer in the CRC pointer register 121, it outputs from the sub code register 122 before the pointer is set. Further, when there is no pointer in the CRC pointer register 121, the sub code checked by the CRC detection circuit 120 is output from the sub register 122. CRC pointer register
The control signal is sent from 121 to the error correction circuit 112, and when the pointer does not exist in the CRC pointer register 121, the error correction circuit 112 sends a control signal that does not cause an error correction operation, and when the pointer exists, the error correction circuit 112 A control signal for making an error correction operation is sent to 112.

The timing pulse generation circuit 111, which receives the bit synchronization signal detected by the bit synchronization detection circuit 107 and the frame synchronization signal detected by the frame synchronization detection circuit 108, outputs various timing pulses corresponding to the bit synchronization signal detected by the bit detection circuit 107. Output, frame sync detection circuit 10
8, demodulator 109, identification code detection circuit 110, error correction circuit 1
12, the code discrimination circuit 113, and the control signal generation circuit 115 are operated in response to the bit synchronization signal detected by the bit synchronization detection circuit 107.

On the other hand, the code detected by the magnetic head 50-16 is the amplifier 1
26-16 is amplified and equalized by the waveform equalization circuit 127-16, and the output of the waveform equalization circuit 127-16 is the waveform shaping circuit 128-16.
The waveform is shaped with. The output of the waveform shaping circuit 128-16 is detected by the bit synchronization detection circuit 129-16 and the frame synchronization detection circuit 130-16, and the demodulator
It is demodulated by 131-16. The output of demodulator 131-16 is register 13
Registered in 4-16. The output of the waveform shaping circuit 128-16 is checked for errors by the CRC detection circuit 133-16 for each frame, and when an error is detected as a result of the CRC check, a pointer is set and a pointer is set in the register 134-16. Output. The pointer is stored in the register 134-16 together with the CRC-checked PCM code. The register value of the register 134-16 is stored in the storage circuit 135-16 according to the address designation of the write address generation circuit 136-16.
Memorized in. The write address generation timing signal of the write address generation circuit 136-16 is supplied to the write priority instructing circuit 137-16 and the read address generation circuit 13-16.
When reading from 8 and write address generation circuit 136
-If there is a conflict with the write command from -16, the write is prioritized.

Further, the timing pulse generation circuit 132-16, which receives the bit synchronization signal detected by the bit synchronization detection circuit 129-16 and the frame synchronization signal detected by the frame synchronization detection circuit 130-16, is detected by the bit synchronization detection circuit 129-16. Various timing pulses corresponding to bit synchronization signals are output, and frame synchronization detection circuit 130-16, demodulator 131-16, CRC detection circuit 133
-16 and the register 134-16 are operated in response to the bit synchronization signal, and the address signal of the write address generation circuit 136-16 is output.

Also, the operation of the reproducing units 125-1 to 125-15 is similar to that of the reproducing unit 125-16.

The read instruction signal generation circuit 139 receives the oscillation output of the master oscillator 16 according to the content of the sampling frequency identification code and supplies the read instruction signal to the read address generation circuit 138. The read address generation circuit 138 that has received the read instruction signal supplies the read address to the storage circuits 135-1 to 135-16, the storage data of the storage circuits 135-1 to 135-16 is read, and the deinterleave circuit 140 is read. Written in. The data written in the deinterleave circuit 140 is error-corrected by the error correction circuit 156, deinterleaved by the deinterleave circuit 140, and read.
When the deinterleaved PCM data cannot be corrected by the error correction circuit 156, the error correction circuit 141 receives the error correction. When there is no error or when the error can be corrected, the PCM code of the left channel audio is D / A converter 14 as it is.
The PCM code of the right channel sound is supplied to the D / A converter 143 and converted into an analog signal.

The analog signal output from the D / A converter 142 is supplied to the deglitcher 144, and the analog signal output from the D / A converter 143 is supplied to the deglitcher 145 to eliminate glitches.
The output of the deglitcher 144 is a low-pass filter 146-1 to 146-.
3 and the output of the deglitcher 145 is supplied to the low-pass filters 147-1 to 147-3. Low Pass Filter 146-1
One of the outputs of ˜146-3 is selected by the changeover switch circuit S1 ′, amplified by the buffer amplifier 149, and output from the output terminal O.
The left channel audio signal that is supplied to L and reproduced is output. One of the outputs of the low-pass filters 147-1 to 147-3 is selected by the changeover switch circuit S2 'and supplied to the output terminal OR amplified by the buffer amplifier 150 to output the reproduced right channel audio signal.

On the other hand, the output of the control signal generation circuit 115 is the decoder 1
The signal is supplied to the decoder 48 and is decoded, and by this decoded output, the changeover switch circuits S1 'and S2' are switched and the gains of the buffer amplifiers 149 and 150 are controlled. Ie filter 14
6-1 to 146-3, 147-1 to 147-3 will be switched according to the sampling frequency of the PCM code recorded on the magnetic tape, and converted by the D / A converters 142 and 143. The high frequency component of the analog signal is removed according to the sampling frequency, and the gains of the buffer amplifiers 149 and 150 are also switched according to the sampling frequency, which results in a difference in the loss of the low-pass filters 146-1 to 146-3. And the difference in loss of the low-pass filters 147-1 to 147-3 is compensated.

The timing pulse generation circuit 118 that receives the output of the control signal generation circuit 115 and the output of the master oscillator 16 generates various timing pulses corresponding to the sampling frequency, and outputs the read instruction address generation circuit 138, the read instruction signal generation circuit 139, and the Interleave circuit 140, error correction circuit 156, D / A converters 142, 143, deglitchers 144, 1
45, the magnetic tape 4 to be supplied to the error correction circuit 141
The signal processing is performed at the signal processing speed according to the sampling frequency of the PCM code recorded in 6.

Also, the output of the control signal generation circuit 115 is supplied to the "0" setting circuits 151, 152 and the D / A converters 142, 143, and corresponds to the non-transmission bit when the non-transmission bit is determined in advance according to the sampling frequency. Set the bit to be set to “0”.

If the non-transmission bits are not determined in advance according to the sampling frequency, the control circuit 124 reads the code representing the number of non-transmission bits sent by the sub-code, and the control circuit 124 reads "0" setting circuits 151, 152. And D / A converter 14
A control signal (not shown) is sent to 2 and 143 to set the corresponding non-transmission bit to "0".

As described above, according to the present invention, when the moving speed of the magnetic recording medium is variable and the number of tracks to be recorded on the magnetic recording medium and the number of frames are configured, it is possible to record without changing the number of words per rack. The running speed of the magnetic recording medium and the processing speed of the signal processing system are controlled according to the sampling frequency, and the sampling frequency information is recorded on the magnetic recording medium, and according to the sampling frequency information recorded on the magnetic recording medium during reproduction. Since the traveling speed of the magnetic recording medium and the processing speed of the signal processing system are controlled, it is not necessary to provide a plurality of pairs of signal processing systems regardless of the difference in sampling frequency, and the minimum recording wavelength can be made almost the same to achieve good signal transmission. It will be possible.

Further, since the same parity check system is used, the error correction capability can be made almost the same regardless of the sampling frequency.

By providing the waveform equalization circuit and the waveform shaping circuit,
Even if there is a change in DC level, waveform shaping can be performed reliably,
Even if the sampling frequency information changes, the recorded waveform can be faithfully reproduced and detected.

[Brief description of drawings]

1 (a), 1 (b) and 1 (c) are block diagrams showing an embodiment of the present invention. FIG. 1 (a) shows a recording system and FIG. ) And FIG. 1 (c) show a reproducing system. FIG. 2 is a block diagram of an equalizing circuit and a waveform shaping circuit according to an embodiment of the present invention. FIG. 3 is a block diagram of a bit synchronization detection circuit according to an embodiment of the present invention. FIG. 4 is a block diagram of a code discrimination circuit, a detection number counter and a control signal generation circuit according to an embodiment of the present invention. FIG. 5 is a flow chart for explaining the operation of one embodiment of the present invention. 1,2,149 and 150 ...... buffer amplifier, _3-1 ～3- _3,
4-1 ～4- _3, 146- ₁ ～146- ₃ and 147- ₁ ～147- ₃ ...... low pass filter, 7 and 8 ...... sample and hold circuit, 9 and 10 ...... A / D converter, 11 and 12 ...... P and Q check word generating circuit, 13,135- ₁ ～135- ₁₆ ...... storage circuit, 14 ...... system control circuit, 16 ...... master oscillator,
17,111,118,132- ₁ ～132- ₁₆ ...... timing pulse generator circuit, 18 ...... tape running reference signal generating circuit, 19 ...... sampling frequency identification code generating circuit, 20 ...... sub code generating circuit, 21 ... ... error-correcting code generating circuit, 22,33- _1-33
- ₁₇ ...... selector, 25 ...... demultiplexer, 26,35- ₁
～35- ₁₆ ...... recording amplifier, 28- ₁ and 28- ₂ ...... reproducing recording changeover switch, 30- ₁ ～30- ₁₇ ...... recording unit, 31- ₁ ～31- ₁₆ ...
... CRC code generating circuit, 32 ₁ ～32- ₁₇ ...... frame synchronization code generator, 34- ₁ ～34- ₁₇ ...... modulator, 40- ₁ ～40- ₁₈ and
50- ₁ ～50- ₁₈ ...... magnetic head, 41 ...... comparator circuit, 42 ......
Servo amplifier, 44 ... Capstan motor, 45 ... Capstan, 101 ... Tape running reference signal reproduction circuit, 102 ...
... tape running reference signal generating circuit, 105,127- ₁ ～127- ₁₆ ...
... waveform equalizer, 106,128- ₁ ～128- ₁₆ ...... waveform shaping circuit, 107,129- ₁ ～129- ₁₆ ...... bit synchronization detection circuit, 10
8,130- ₁ ～130- ₁₆ ...... frame synchronization detection circuit, 109,131
_{-1 to} 131- ₁₆ ...... Demodulator, 110 ...... Identification code detection circuit, 113
…… Sign discrimination circuit, 114 …… Detection counter, 115 ……
Control signal generation circuit, 116 ... Control circuit, 117 ...
Automatic stopping display circuit, 136- ₁ ～136- ₁₆ ...... write address generator circuit, 138 ...... read address generator circuit, 139 ...
… Read instruction signal generator circuit, 140 …… Deinterleave circuit, 142 and 143 …… D / A converter, 153 …… Speed reference voltage generator, 154 …… Pulse generator, 155 …… Frequency-voltage converter, 156 ...... Error correction circuit.

Claims (1)

[Claims] 1. A magnetic recording / reproducing apparatus for converting an analog signal into a PCM code, recording the same on a magnetic recording medium, detecting the recording PCM code and reproducing the analog signal, which is recorded on the magnetic recording medium during reproduction. An equalizer amplifier that flattens the frequency within the magnetic tape signal transmission band by changing frequency characteristics according to sampling frequency information, a pulse slimming circuit that narrows the output pulse width of the equalizer amplifier to a predetermined width, and an output of the pulse slimming circuit Waveform equalizing means that includes an integrating circuit that integrates, a DC regenerating circuit that regenerates DC from the output of the integrating circuit, and a level comparison circuit that compares the output of the integrating circuit with the output of the DC regenerating circuit. And a traveling speed for controlling the traveling speed of the magnetic recording medium based on the output of the waveform shaping means. And control means, a magnetic recording and reproducing apparatus characterized by comprising a signal processing speed control means for controlling the signal processing speed of the signal processing system based on the output of said waveform shaping means.