JPH0264965A - Data identifying device and data format - Google Patents

Abstract

PURPOSE:To enlarge capacity by sampling an input signal with an integer number-fold clock frequency, storing the input signal to a memory, reading the signal at a speed to be different from a speed, with which stored time sequence data are written, and executing the identification processing of data. CONSTITUTION:A reproducing signal is sampled by an analog-digital converter 5 and quantized and an obtained signal sequence is stored in a memory 8 and after that, successively read at the different suitable speed. Then, the identification operation is executed by a phase synchronizing circuit 6 and a code discriminator 7. Accordingly, even when the transferring rate of recording and reproducing is increased, the processing speed of the data identification is not improved. When there is an error in identifying data, an identifying characteristic is changed and re-operation can be easily executed. Thus, the storing capacity can be enlarged.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data identification device in an apparatus for recording and reproducing PCM signals and a data format for recording and reproducing the same.

BACKGROUND OF THE INVENTION In recent years, pulse code modulation has been used as a storage device for large-capacity digital data.
tion, PCM) signals are being actively developed. An example of such a device is an optical disk device. In devices that perform high-density recording such as optical disks, the PCM signal that is reproduced is band-limited, and the clock component in the reproduced signal also has jitter peculiar to the device, so it is difficult to binarize data and change the clock component. A data identification device for reproduction is required.

In this data identification device, recording and playback are performed by dividing sectors according to a specific data format, so the signal sequence for recording and playback is intermittent, and in data identification of the playback signal of each sector, the clock component is set at high speed. A data identification device has been developed that includes a phase-locked circuit that pulls in and regenerates stably. Furthermore, for the recording/reproduction format, a synchronization pull-in pattern is provided at the beginning for synchronization pull-in of the phase synchronization circuit used for this clock reproduction.

Hereinafter, the conventional data identification device and data formant as described above will be explained with reference to the drawings.

FIG. 5 shows a first configuration of a conventional data identification device, FIG. 6 shows a second configuration, FIG. 7 is a waveform diagram for explaining its operation, and FIG. 8 shows a conventional data identification device. FIG. 9 is an explanatory diagram of the operation of the device. In Fig. 5, 1 is a comparator, 2 is a monostable multipipe rake,
3 is a phase locked circuit (Phase Locked 1
oop, PLL), 4 is a D flip-flop.

In FIG. 6, 5 is an analog-to-digital converter;
is a phase synchronized circuit, and 7 is a sign determiner. The PCM signal recorded and reproduced here is an 8-10 converted signal,
In data detection of the reproduced signal, after clock reproduction is performed using the zero crossing points as clock edge information, the code of the originally recorded data is detected and output as identification data.

In FIG. 10, the comparator 1 binarizes the input signal so as to detect the zero crossing point, and the monostable multivibrator 2 detects the clock of the recorded PCM signal every time a rising or falling edge occurs in the output of the comparator 1. Outputs a pulse with a width equal to 1/2 of the period. The phase synchronization circuit 3 reproduces and outputs a clock synchronized with the output of the monostable multi-bi break 2. D flip flop 4
is a sign determiner which samples the output of the comparator 1 using the recovered clock as a clock and outputs it as identification data.

Through the above series of operations, data is identified from the input signal.

In FIG. 6, data identification is performed by digital signal processing, and as shown in FIG.
It samples, quantizes, and outputs using a fixed clock with twice the frequency.

At this time, since the clock of the input signal is approximately equal to 1/2 of the sampling clock, the change in the phase difference between the two is slight. When a zero crossing point occurs, the relative time relationship between the clock component and the sampling clock is calculated as the discrimination point phase φi, and the reproduced clock phase φr is output so as to smoothly interpolate the intermittently obtained discrimination point phase. do. Assuming that a zero crossing point has now occurred in the input signal, the input signal sampled by the analog-to-digital converter 5 is converted to 31. S2, the phase φi at S2 is calculated by linear interpolation with the zero crossing phase as 180'' phase, where 5IXS2≦0 and S1≠0. A recovered clock phase φr is output as a result of reducing and filtering the phase φi and interpolating it in all processing clocks. Data punching is performed at the position where the recovered clock phase is 0°, and the sign determiner 7
determines whether the sign of the input signal is positive or negative at the punching point position of the data represented by the reproduced clock phase φr obtained by the phase synchronization circuit 6, and outputs it as identification data as shown in (e). The reproduced clock is output in correspondence with 1" for each punching. Through the above series of operations, data is identified.

As described above, in data identification of a reproduced signal, after the clock information is reproduced, the data is punched out, that is, the sign is determined based on this information.

Therefore, the recording/reproduction format is as shown in FIG. 8 in order to guarantee the synchronization pull-in time required from when a reproduction signal is obtained to when this clock reproduction is normally performed.

In FIG. 8, the synchronization pull-in pattern is followed by a synchronization pattern for detecting synchronization as a group of data, and this is followed by a data section. FIG. 9 is a signal explanatory diagram corresponding to the first example, in which the phase-locked circuit uses a binarized reproduced signal as an input signal, and is free-running before the input is applied, and after the input is applied. Synchronization pull-in is started, synchronization is completed within the sync pull-in pattern, and the data is normally determined.

Problems to be Solved by the Invention In conventional data identification devices, the operating speed of the phase synchronization circuit section and code determination section must be equal to the data transfer rate of the reproduced signal. A corresponding increase in speed was required.

In addition, the phase synchronized circuit is in a free-running state when there is no input signal, and the time from when the input signal is input until the clock is correctly regenerated is required as the synchronization pull-in time, and the data format for recording and playback is also As shown in Figure 8, it was necessary to provide a pattern for this synchronization pull-in. This synchronization pattern has nothing to do with the data being recorded, and has resulted in a decrease in the recording capacity of the recording device.

In view of the above-mentioned problems, the present invention converts the processing speed of the phase synchronization circuit and code judger to the required speed by sampling input symbols, temporarily storing them in memory, and then reading them at any time to perform digital signal processing. This can be done by doing this.

Furthermore, when performing data identification of a symbol sequence sampled from memory, the above-mentioned operation is used as the first operation, and in addition,
Data identification that obtains correct identification results even at the beginning of the signal sequence by performing the second operation of operating the phase-locked circuit and the discriminator in the opposite direction in time, and connecting the results of both in a synchronized manner. This is what realizes the device.

Furthermore, the present invention provides a recording and reproducing format that does not have the synchronization pull-in pattern and is composed of only a synchronization pattern and a data section and is capable of increasing the capacity.

Means for Solving the Problems In order to achieve the object of not causing an increase in data identification processing speed even when the transfer rate increases, the data identification device of the present invention includes an analog-to-digital converter that samples an input signal; The first step is to store the output once.
It consists of a memory, a phase synchronization circuit that reads the memory output at any time and reproduces the clock, and a sign determiner that determines the original data from the reproduced clock and the sampled input signal.

Further, in order to achieve the purpose of performing correct data identification from the beginning of the reproduced signal, the data identification device of the present invention, in addition to the above configuration, temporarily stores the output of the code determiner and outputs it after performing appropriate synchronization matching. and a second memory.

Furthermore, in order to increase the recording capacity, a recording/reproducing format without a synchronization pull-in pattern is provided.

Effect of the present invention With the above configuration, the input signal is sampled at an integer multiple of its clock frequency, stored in the memory, and read out at a speed different from the speed at which the stored time series data is written to perform data identification processing. This realizes data identification processing that does not depend on the transfer rate of recording and reproduction.

Further, the present invention performs reverse data identification processing in addition to forward data identification processing when identifying the signal sequence read from the first memory, and further connects both by synchronization matching, The present invention provides a data identification device that can correctly identify data from the beginning of a signal sequence.

Furthermore, the present invention provides a data format that does not have a synchronization pull-in pattern and is capable of increasing capacity.

Embodiment Hereinafter, a data identification device and format according to an embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 shows the basic configuration of a data identification device in an embodiment of the present invention, FIG. 2 is a block diagram of the second embodiment, FIG. 3 shows the data format of the present invention, and FIG. It is an explanatory diagram of the operation. In the following explanation of the drawings, the same components as those in FIG. 6 of the conventional example will be designated by the same numbers and will not be repeated. In FIG. 1, 8 is a memory. In FIG. 2, 9 is a memory.

The operation of the data identification device configured as described above will be explained below.

First, in FIG. 1, the analog-to-digital converter 5 takes as an input signal an 8-10 converted and recorded/reproduced signal, samples it at twice the frequency of the clock signal, quantizes it, and outputs it. Memory 8 stores the output of analog-to-digital converter 1. The phase synchronization circuit 6 and the sign determiner 7 identify the data while reading out the signal sequence written in the memory 8 at an appropriate speed. As can be easily seen, it is possible to prepare a plurality of phase synchronization circuits 6 and sign determiners 7 and operate them in parallel, thereby equivalently increasing the data identification speed. In addition, the normal operation of the device is
Similar to the conventional example, the analog-to-digital converter 5 directly outputs the data to the phase synchronization circuit 6 and the sign determiner 7 to perform the identification operation, and at the same time stores the sampled data in the memory 8, and the identification result is stored in the memory 8. Only when an error occurs, it is also possible to read out the corresponding signal sequence from the memory 8, change the characteristics of the phase synchronization circuit or the criterion of the code discriminator, and perform data discrimination again.

In addition, in FIG.
As a first operation, as described above, the signal sequence stored in the memory 8 is data-identified at an appropriate speed and stored in the memory 9, and as a second operation, the memory 8 processed in the first operation is Data identification is performed while reading the signal series stored in the memory 9 in a direction opposite to the order in which they were written, and the results are stored in the memory 9. These two operations result in a total of two determination operations for the same data.

The memory 9 rearranges the second half of the result obtained in the second operation described above in a temporally backward direction, that is, in a temporally forward direction with respect to the reproduced signal sequence, and stores the first half and the second half of the result. The second half of the result obtained in step 1 is matched by detecting a synchronization pattern, and these are connected and output.

It goes without saying that the first operation described above does not need to be performed after being stored in the memory, and the identification operation may be performed directly from the output of the analog-to-digital converter.

Further, in FIG. 3, synchronization pattern 1 is a pattern representing the beginning of data, synchronization patterns 2, 3, and 4 are synchronization patterns for resynchronizing the middle part of data, and synchronization pattern 5 represents the end. It's a pattern. According to this data formant, as shown in FIG. 4, correct data can be reproduced by the above-mentioned data identification operation, and synchronization matching is also easy due to the arrangement of synchronization patterns representing the beginning and end. The reproduced signal shown in (a) in the figure and stored in the memory 8 is processed by the first operation (b).
), there is an error in the first half because the phase-locked circuit is asynchronous, but at least the second half shows correct identification results.
By the above-mentioned second operation, at least the first half is connected with the correct identification result when considered in the forward direction in time, and a result as shown in (d) is obtained. The length of the data processed at this time may be as short as (or more than twice) the length required for synchronization of the phase synchronized circuit.

As can be easily understood, the second operation described above does not necessarily have to be performed from the end of the data format, but may be performed from the middle as long as synchronization can be achieved.

Effects of the Invention The present invention samples and quantizes a reproduced signal using an analog-to-digital converter, stores the resulting signal sequence in a memory, and then sequentially reads it out at an appropriate speed using a phase synchronization circuit and a sign determiner. By performing the identification operation, the processing speed of data identification increases even when the transfer rate of recording and playback increases, and the advantage is that if there is an error in the identification data, it is easy to change the identification characteristics and restart the operation. The purpose of this invention is to provide a data identification device.

In addition, a second memory for storing the output of the sign determiner is added, the above-mentioned identification operation is performed as the first operation, and the signal sequence stored in the first memory is read out in the backward direction in time for identification. By performing the second operation to synchronize and connect the two results, correct data identification is performed from the beginning of the reproduced signal.

Furthermore, by arranging synchronization patterns at the beginning and end and making the overall length more than twice the synchronization pull-in length of phase synchronization, the data identification operation described above is made possible, which was previously necessary. The present invention provides a data format that does not cause a decrease in recording capacity due to the setting of a synchronization pull-in pattern.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data identification device in a first embodiment of the present invention, FIG. 2 is a block diagram of the second embodiment, and FIG. 3 is an explanatory diagram showing the data format of the present invention. Fig. 4 is an explanatory diagram of its operation, Fig. 5 is a first configuration diagram of a conventional data identification device, Fig. 6 is a second configuration diagram, Fig. 7 is an explanatory diagram of its operation, and Fig. 8 is a data format. Figure, No. 9
The figure is an explanatory diagram of the conventional operation. 1... Comparator, 2... Monostable multivibrator, 3.6... Phase synchronized circuit,
4.7... Sign determiner, 5... Analog-digital converter, 8.9... Memory. Name of agent Patent attorney Shigetaka Awano 1 person 1 Figure 3 Figure 1 Lost dream Figure 4 Figure 2 Figure Figure Figure Cause lfl! lFJ edition prefecture

Claims (3)

[Claims] (1) An analog-to-digital converter that samples and quantizes an input signal, which is a band-limited pulse code modulation signal, at a frequency that is an integral multiple of its clock frequency, and outputs the quantized signal; and a sampling signal that is the output of the analog-to-digital converter. a memory for storing the signal sequence written in the memory, a phase synchronized circuit that reads out the signal sequence written in the memory, reproduces and outputs a clock component of the signal sequence, and inputs the signal sequence and the output of the phase synchronized circuit. and a code determiner that identifies the code of the signal series and outputs the code together with the data punching signal. (2) the first one that stores the analog-to-digital converter output;
In addition to the above memory, the configuration includes a second memory that temporarily stores and outputs the output of the sign determiner, and the phase synchronized circuit and the sign determiner are stored in the first memory during operation. a first memory which performs a discrimination operation by reading out the signal series in the same direction as the stored order and stores the discrimination result in the second memory;
A second operation is performed in which the data is read out in a temporally reverse direction from the stored order, an identification operation is performed, and the identification result is stored in the second memory. The second half of the results identified in the backward direction in time by the operation is rearranged in the forward direction in time. Subsequently, the second half of the results identified in the forward direction in time by the first operation is rearranged. 2. The data identification device according to claim 1, wherein the data identification device connects the data in a synchronous manner and outputs the data identification result. (3) It has a synchronization detection pattern indicating the start of data, a synchronization detection pattern indicating the end, and at least one synchronization detection pattern placed in between, and the entire length is the phase synchronization of the data discriminator. 2 of the circuit synchronization pull-in time
A data format characterized by being longer than twice.