JPH0653231A - Manufacture of mosfet - Google Patents
Manufacture of mosfetInfo
- Publication number
- JPH0653231A JPH0653231A JP5163331A JP16333193A JPH0653231A JP H0653231 A JPH0653231 A JP H0653231A JP 5163331 A JP5163331 A JP 5163331A JP 16333193 A JP16333193 A JP 16333193A JP H0653231 A JPH0653231 A JP H0653231A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- insulating film
- film
- oxide film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 239000012535 impurity Substances 0.000 claims abstract description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 44
- 229920005591 polysilicon Polymers 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 36
- 125000006850 spacer group Chemical group 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 150000004767 nitrides Chemical class 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 13
- 230000000903 blocking effect Effects 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000010408 film Substances 0.000 claims 42
- 239000004065 semiconductor Substances 0.000 claims 4
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract 2
- 230000000694 effects Effects 0.000 description 16
- 239000000969 carrier Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、金属酸化物電界効果ト
ランジスタ（ＭＯＳＦＥＴ）に関し、特に限界電圧およ
び接合容量を減少でき、かつ工程の単純化が可能なＬＤ
Ｄ（Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒａｉｎ）の構造
のＭＯＳＦＥＴ製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal oxide field effect transistor (MOSFET), and more particularly to an LD capable of reducing the limit voltage and the junction capacitance and simplifying the process.
The present invention relates to a method for manufacturing a MOSFET having a D (Lightly Doped Drain) structure.
【０００２】[0002]
【従来の技術】一般的なＭＯＳＦＥＴは、ゲート電極の
エッジ部分において、高電界が形成されてホットキャリ
ヤが発生し、発生されたホットキャリヤがゲート絶縁膜
にトラップされる場合、ゲート絶縁膜に欠点が発生する
のでＭＯＳＦＥＴの動作特性が低下されるのみならず、
寿命が短縮される問題点があった。このようなホットキ
ャリヤの効果を減少させるために、図１〜図３に示すよ
うなＬＤＤ構造のＭＯＳＦＥＴが考えられる。2. Description of the Related Art In a general MOSFET, when a high electric field is formed at the edge portion of a gate electrode and hot carriers are generated, and the generated hot carriers are trapped in the gate insulating film, there is a defect in the gate insulating film. Occurs, not only the operating characteristics of the MOSFET are deteriorated,
There was a problem that the life was shortened. In order to reduce the effect of such hot carriers, an LDD structure MOSFET as shown in FIGS. 1 to 3 can be considered.
【０００３】図１に示すように、Ｐ型基板１１上に各セ
ルを電気的に絶縁するためのフィールド酸化膜１２を形
成し、その後Ｐ型基板１１の全表面にわたってゲート絶
縁膜１３を形成し、そのゲート絶縁膜１３上にポリシリ
コン膜を塗布したのちパターニングしてゲート電極１４
を形成する。ついで、ゲート電極１４の露出された表面
を酸化させてゲートギャップ（Ｇａｐ）酸化膜１５を形
成し、ゲート側壁用ポリシリコン膜１６を基板の全ての
表面にわたって形成する。図２に示すように、ポリシリ
コン膜１６をＲＩＥ法により異方性エッチングしてゲー
ト側壁１７を形成する。前記工程において、ゲート電極
１４上に形成されたゲートギャップ酸化膜１５は、ゲー
ト側壁１７を形成するためのポリシリコン膜１６のエッ
チングの時のエッチングストッパとして作用する。ゲー
トギャップ酸化膜１５およびゲート側壁１７をマスクと
して自己アライメントさせて高濃度のＮ+ の不純物をイ
オン注入し、これを拡散させ、フィールド酸化膜１２と
ゲート側壁１７との間のアクチブ領域に、高濃度のＮ+
型ソース／ドレーン領域１８ａ，１８ｂを形成する。As shown in FIG. 1, a field oxide film 12 for electrically insulating each cell is formed on a P-type substrate 11, and then a gate insulating film 13 is formed on the entire surface of the P-type substrate 11. A gate electrode 14 is formed by applying a polysilicon film on the gate insulating film 13 and then patterning it.
To form. Next, the exposed surface of the gate electrode 14 is oxidized to form a gate gap (Gap) oxide film 15, and a gate sidewall polysilicon film 16 is formed over the entire surface of the substrate. As shown in FIG. 2, the polysilicon film 16 is anisotropically etched by the RIE method to form the gate sidewall 17. In the above process, the gate gap oxide film 15 formed on the gate electrode 14 acts as an etching stopper when etching the polysilicon film 16 for forming the gate sidewall 17. Self-alignment is performed using the gate gap oxide film 15 and the gate side wall 17 as a mask to ion-implant a high-concentration N + impurity, and this is diffused to form a high concentration in the active region between the field oxide film 12 and the gate side wall 17. Concentration N +
Form source / drain regions 18a, 18b.
【０００４】図３に示すように、ゲート側壁１７を除去
し、ゲートギャップ酸化膜１５をマスクとして自己アラ
イメントさせて低濃度のＮ- 型の不純物をイオン注入
し、これを拡散させ、ゲートギャップ酸化膜１５と前記
Ｎ+ 型ソース／ドレーン領域１８ａ，１８ｂとの間のア
クチブ領域に、低濃度のＮ- 型ソース／ドレーン領域１
９ａ，１９ｂを形成する。したがって、ＭＯＳＦＥＴ
は、ソース／ドレーン領域が高濃度の不純物領域１８
ａ，１８ｂと低濃度の不純物領域１９ａ，１９ｂとから
なるＬＤＤ構造を有する。As shown in FIG. 3, the gate side wall 17 is removed, the gate gap oxide film 15 is used as a mask for self-alignment, and a low concentration N − -type impurity is ion-implanted. In the active region between the film 15 and the N + type source / drain regions 18a and 18b, a low concentration N − type source / drain region 1 is formed.
9a and 19b are formed. Therefore, MOSFET
Is the impurity region 18 having a high concentration of the source / drain region.
It has an LDD structure composed of a and 18b and low concentration impurity regions 19a and 19b.
【０００５】上述したＬＤＤ構造は、高電界によるホッ
トキャリヤ効果を減少することができるが、ソース／ド
レーン領域がＮ- 型不純物領域およびＮ+ 型不純物領域
で構成されているので、抵抗が増加し、これにより、Ｍ
ＯＳＦＥＴの動作速度が遅くなる。また、ゲート側壁の
厚さを正確に調節することが難しいので、所望の幅のソ
ース／ドレーン領域を得ないので、ショートチャネル効
果が発生する問題点があった。The LDD structure described above can reduce the hot carrier effect due to a high electric field, but since the source / drain region is composed of the N − type impurity region and the N + type impurity region, the resistance increases. , By this, M
The operating speed of the OSFET becomes slow. In addition, since it is difficult to accurately control the thickness of the gate sidewall, a source / drain region having a desired width cannot be obtained, which causes a problem of a short channel effect.
【０００６】ショートチャンネル効果を減少させるため
には、Ｐ型基板の濃度を高くドーピングさせなければな
らないが、このような方法としてはＰ型基板の自身を高
い濃度でドーピングさせるか、または高濃度のＮ+ 型ソ
ース／ドレーン領域および低濃度のＮ- 型ソース／ドレ
ーン領域を覆うように、Ｐ型不純物をイオン注入して基
板上に別のＰ型不純物領域を形成する方法がある。前記
２つの方法によりＬＤＤ構造のＭＯＳＦＥＴのショート
チャネル効果を減少させることができる。In order to reduce the short channel effect, the P-type substrate must be highly doped, and as such a method, the P-type substrate itself can be highly doped or the P-type substrate can be highly doped. There is a method of ion-implanting a P-type impurity to form another P-type impurity region on the substrate so as to cover the N + -type source / drain region and the low concentration N − -type source / drain region. The short channel effect of the LDD structure MOSFET can be reduced by the above two methods.
【０００７】しかしながら、ＭＯＳＦＥＴの限界電圧と
ソース／ドレーン領域の接合容量は、不純物のドーピン
グ濃度に比例して増加するが、上記の方法によるＬＤＤ
構造のＭＯＳＦＥＴは、従来のＬＤＤ構造のＭＯＳＦＥ
Ｔ基板の濃度より、基板の濃度が高くドーピングされて
いるので、限界電圧およびソース／ドレーン領域の接合
容量が増加してその動作特性が低下される問題点があっ
た。However, although the limit voltage of the MOSFET and the junction capacitance of the source / drain region increase in proportion to the doping concentration of impurities, the LDD according to the above method is used.
The structure MOSFET is a conventional LDD structure MOSFET.
Since the concentration of the substrate is higher than that of the T substrate, the limit voltage and the junction capacitance of the source / drain region are increased and the operating characteristics thereof are deteriorated.
【０００８】図４〜図９はショートチャネル効果を減少
させると共に限界電圧およびソース／ドレーン領域の接
合容量を減少させることができる従来のＬＤＤ構造のＭ
ＯＳＦＥＴの製造工程図である。図４を参照すれば、Ｐ
型基板２１上に通常のＬＯＣＯＳ工程によりフィールド
酸化膜２２を形成してフィールド領域およびアクチブ領
域を限定する。FIGS. 4 to 9 show the M of the conventional LDD structure capable of reducing the short channel effect and the limit voltage and the source / drain region junction capacitance.
It is a manufacturing process drawing of OSFET. Referring to FIG. 4, P
A field oxide film 22 is formed on the mold substrate 21 by a normal LOCOS process to define a field region and an active region.
【０００９】図５に示すように、基板２１の全ての表面
にわたってゲート酸化膜２３、第１ポリシリコン膜２
４、窒化膜２５および第２ポリシリコン膜２６を順次形
成し、ついで前記第２ポリシリコン膜２６、窒化膜２
５、第１ポリシリコン膜２４およびゲート酸化膜２３を
順次パターニングして３層構造のゲートを形成する。ゲ
ートを形成した後基板の全ての表面にわたって酸化膜を
形成しＲＩＥ法により異方性エッチングして側壁酸化膜
１７を形成する。As shown in FIG. 5, the gate oxide film 23 and the first polysilicon film 2 are formed on the entire surface of the substrate 21.
4, the nitride film 25 and the second polysilicon film 26 are sequentially formed, and then the second polysilicon film 26 and the nitride film 2 are formed.
5, the first polysilicon film 24 and the gate oxide film 23 are sequentially patterned to form a gate having a three-layer structure. After forming the gate, an oxide film is formed on the entire surface of the substrate and anisotropically etched by the RIE method to form a sidewall oxide film 17.
【００１０】図６に示すように、基板の全面にわたって
Ｎ+ 型不純物がドーピングされた第３ポリシリコン膜２
８を形成した後、フィールド間のアクチブ領域にのみ第
３ポリシリコン膜２８が残存するように選択的にエッチ
ングする。基板の全面にわたってホトレジスト膜２９を
塗布した後前記第３ポリシリコン膜２８が露出される時
までエッチングバックする。As shown in FIG. 6, a third polysilicon film 2 doped with N + type impurities is formed on the entire surface of the substrate.
After forming 8, the third polysilicon film 28 is selectively etched so that the third polysilicon film 28 remains only in the active region between the fields. After applying a photoresist film 29 over the entire surface of the substrate, etching back is performed until the third polysilicon film 28 is exposed.
【００１１】図７に示すように、ゲート２４の上方の窒
化膜２５が露出される時まで第２ポリシリコン膜２６お
よび第３ポリシリコン膜２８をエッチングする。この
時、ゲート２４の上方の第２ポリシリコン膜２６および
第３ポリシリコン膜２８は全て除去され、ゲート２４と
フィールド酸化膜２２間のアクチブ領域上にＮ+ 型ドー
ピングされた第３ポリシリコン膜２８が残存することと
なる。この時、残存しているＮ+ 型ドーピングされた第
３ポリシリコン膜２８は、後続されるＮ+ 型ソース／ド
レーン領域を形成するための拡散工程が行われる時、高
濃度のＮ+ 型ソース／ドレーン領域のための拡散ソース
として作用し、ゲート上の窒化膜は前記エッチング工程
の際のストッパとして作用する。As shown in FIG. 7, the second polysilicon film 26 and the third polysilicon film 28 are etched until the nitride film 25 above the gate 24 is exposed. At this time, the second polysilicon film 26 and the third polysilicon film 28 above the gate 24 are all removed, and the N + -type doped third polysilicon film is formed on the active region between the gate 24 and the field oxide film 22. 28 will remain. At this time, the remaining N + -type doped third polysilicon film 28 may have a high concentration of N + -type source when a diffusion process for forming a subsequent N + -type source / drain region is performed. / Acts as a diffusion source for the drain region, and the nitride film on the gate acts as a stopper during the etching process.
【００１２】図８に示すように、ホトレジスト膜２９と
側壁酸化膜２７とを順次除去し、前記ゲート２４に残存
しているポリシリコン膜２８をマスクとして自己アライ
メントさせて低濃度のＮ- 型およびＰ- 型不純物を順次
イオン注入する。As shown in FIG. 8, the photoresist film 29 and the sidewall oxide film 27 are sequentially removed, and the polysilicon film 28 remaining on the gate 24 is used as a mask for self-alignment to form a low concentration N − -type and P − type impurities are sequentially ion-implanted.
【００１３】ついでイオン注入された不純物を拡散させ
ると、低濃度のＮ- 型ソース／ドレーン領域３１ａ，３
１ｂが形成される。この時残存しているＮ+ 型ドーピン
グされたポリシリコン膜２８から不純物が拡散されて高
濃度のＮ+ 型ソース／ドレーン領域３０ａ，３０ｂが形
成され、これと同時にイオン注入されたＰ- 型不純物も
拡散されて低濃度のＰ- 型不純物領域３２ａ，３２ｂが
形成される。Then, when the ion-implanted impurities are diffused, low concentration N -- type source / drain regions 31a, 3 are formed.
1b is formed. At this time, impurities are diffused from the remaining N + -type doped polysilicon film 28 to form high-concentration N + -type source / drain regions 30a and 30b, and at the same time, ion-implanted P − -type impurities are formed. Is also diffused to form low concentration P − -type impurity regions 32a and 32b.
【００１４】上述したイオン注入工程において、低濃度
のＮ- 型およびＰ- 型不純物が残存している第３ポリシ
リコン膜２８およびゲート２４をマスクとしてイオン注
入されるので、低濃度のＮ- 型ソース／ドレーン領域３
１ａ，３１ｂは、前記高度Ｎ+ 型ソース／ドレーン領域
３０ａ，３０ｂと各々当接するように形成され、低濃度
のＰ- 型不純物領域３２ａ，３２ｂは、前記各々の低濃
度のＮ- 型ソース／ドレーン領域３１ａ，３１ｂのみを
覆うように形成される。In the above-described ion implantation step, since the third polysilicon film 28 and the gate 24, in which the low concentration N − -type and P − -type impurities remain, are ion-implanted, the low concentration N − -type is used. Source / drain area 3
1a, 31b, the high N + -type source / drain regions 30a, is formed so as to 30b and each contact, low-concentration P - -type impurity regions 32a, 32b is N the low concentration of the respective - -type source / It is formed so as to cover only the drain regions 31a and 31b.
【００１５】図９に示すように、基板全ての表面にわた
って平坦化用ＳＯＧ膜３３を形成し、前記第２ポリシリ
コン膜２８との内部接続のため、前記ＳＯＧ膜３３をエ
ッチングしてコンタクトを形成し、金属電極３４を形成
してＬＤＤ構造のＭＯＳＦＥＴを製造する。As shown in FIG. 9, a flattening SOG film 33 is formed over the entire surface of the substrate, and the SOG film 33 is etched to form a contact for internal connection with the second polysilicon film 28. Then, the metal electrode 34 is formed to manufacture the LDD structure MOSFET.
【００１６】前述したＬＤＤ構造のＭＯＳＦＥＴは、Ｐ
- 型不純物領域が高濃度および低濃度のソース／ドレー
ン領域のみを覆うように形成されているので、Ｐ- 型不
純物領域が高濃度および低濃度のソース／ドレーン領域
を覆う従来のＬＤＤ構造のＭＯＳＦＥＴよりも、接合容
量および限界電圧を減少させることができる利点があ
る。The LDD structure MOSFET described above has a P
Since the -type impurity region is formed so as to cover only the high-concentration and low-concentration source / drain regions, the conventional LDD structure MOSFET in which the P - type impurity region covers the high-concentration and low-concentration source / drain regions. Than that, there is an advantage that the junction capacitance and the limit voltage can be reduced.
【００１７】[0017]
【発明が解決しようとする課題】しかしながら、前述し
たＬＤＤ構造のＭＯＳＦＥＴの製造方法は、ゲートを３
層構造と形成するために、第１，第２ポリシリコン膜と
窒化膜の形成工程およびエッチング工程を行わなければ
ならないし、ソース／ドレーン金属電極とソース／ドレ
ーン不純物領域間の内部接続用、および高濃度のソース
／ドレーン領域のための拡散ソース用第３ポリシリコン
膜の蒸着およびエッチング工程と、ホトレジストの塗布
およびエッチングバック工程を行わなければならない
等、多数工程が必要とするので、製造工程が複雑化とす
る問題点がある。本発明は、限界電圧およびソース／ド
レーン領域の接合容量を減少させることができ、従来の
ＬＤＤ構造のＭＯＳＦＥＴ製造方法より工程数およびマ
スク数の増加なく、単純なＬＤＤ構造のＭＯＳＦＥＴ製
造方法を提供するにその目的がある。However, in the method for manufacturing the LDD-structured MOSFET described above, the gate has three gates.
In order to form a layered structure, a step of forming the first and second polysilicon films and a nitride film and an etching process must be performed, for internal connection between the source / drain metal electrode and the source / drain impurity region, and Since many steps are required, such as a deposition and etching process of the third polysilicon film for the diffusion source for the high-concentration source / drain region and a photoresist coating and etching back process, the manufacturing process is difficult. There is a problem that it becomes complicated. The present invention provides a simple LDD structure MOSFET manufacturing method that can reduce the limit voltage and the junction capacitance of the source / drain region, and does not increase the number of steps and masks compared to the conventional LDD structure MOSFET manufacturing method. Has that purpose.
【００１８】[0018]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明は、第１導電型の基板上に酸化膜を形成し
てフィールド領域およびアクチブ領域を限定するステッ
プと，アクチブ領域上にゲート酸化膜を形成するステッ
プと，アクチブ領域に限界電圧を調節するための不純物
をイオン注入するステップと，ポリシリコン膜を前記ゲ
ート酸化膜上に形成するステップと，ポリシリコン膜お
よび酸化膜をエッチングしてゲートを形成するステップ
と，絶縁膜を基板の全面にわたって形成した後、異方性
エッチングしてゲートおよびゲート酸化膜の側面に側壁
スペーサを形成するステップと，前記側壁スペーサをマ
スクとして自己アライメントさせて第２導電型の不純物
をイオン注入して高濃度のソース／ドレーン領域を形成
するステップと，前記フィールド酸化膜とスペーサとの
間の前記高濃度のソース／ドレーン領域に厚膜の絶縁膜
を形成し、ゲート上にゲートギャップ絶縁膜を形成する
ステップと，前記側壁スペーサを除去するステップと，
前記厚膜の絶縁膜およびゲートをマスクとして自己アラ
イメントさせて第１導電型の低濃度不純物および第２導
電型の低濃度不純物をイオン注入して前記高濃度のソー
ス／ドレーン領域とゲートとの間のアクチブ領域内に前
記高濃度のソース／ドレーン領域に当接するように、第
２導電型の低濃度ソース／ドレーン領域を形成し、第２
導電型の低濃度ソース／ドレーン領域を覆うように第１
導電型の低濃度の不純物領域を形成するステップと，を
含む構造のＭＯＳＦＥＴの製造方法を提供する。To achieve the above object, the present invention provides a step of forming an oxide film on a substrate of the first conductivity type to define a field region and an active region, and a step of forming an active region on the active region. Forming a gate oxide film on the gate, implanting impurities for adjusting the limit voltage into the active region, forming a polysilicon film on the gate oxide film, and removing the polysilicon film and the oxide film. Etching to form a gate, forming an insulating film over the entire surface of the substrate, and then anisotropically etching to form sidewall spacers on the side surfaces of the gate and the gate oxide film, and using the sidewall spacer as a mask Aligning and ion-implanting impurities of the second conductivity type to form high-concentration source / drain regions; Serial field forming the high concentration thick insulating film on the source / drain region of between the oxide film and the spacer, forming a gate gap insulating film over the gate, and removing the sidewall spacers,
Between the high-concentration source / drain region and the gate by self-aligning with the thick insulating film and the gate as a mask to ion-implant the low-concentration impurity of the first conductivity type and the low-concentration impurity of the second conductivity type. A low-concentration source / drain region of the second conductivity type is formed so as to contact the high-concentration source / drain region in the active region of
First to cover the conductive type low concentration source / drain region
A method of manufacturing a MOSFET having a structure including a step of forming a conductive type low-concentration impurity region.
【００１９】[0019]
【実施例】以下、本発明の実施例を添付された図面に基
づいて詳細に説明する。図１０〜図１４は、本発明の第
１実施例によるＬＤＤ構造のＭＯＳＦＥＴ製造工程であ
る。図１０に示すように、Ｐ型基板４１上に通常のＬＯ
ＣＯＳ工程でフィールド酸化膜４２を成長させてフィー
ルド領域およびアクチブ領域を限定し、アクチブ領域上
にゲート酸化膜４３を形成し、限界電圧を調節するため
に不純物をアクチブ領域にイオン注入する。図１１に示
すように、ゲート酸化膜４３上にポリシリコン膜４４を
蒸着し、このポリシリコン膜４４およびゲート酸化膜４
３をエッチングしてゲートを形成する。図１２に示すよ
うに、基板の全面にわたって窒化膜を形成し、ＲＩＥ法
により異方性エッチングしてゲート４４およびゲート酸
化膜４４の側面に側壁スペーサ４５を形成する。Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. 10 to 14 show a process for manufacturing a MOSFET having an LDD structure according to the first embodiment of the present invention. As shown in FIG. 10, a normal LO is formed on the P-type substrate 41.
In the COS process, a field oxide film 42 is grown to define a field region and an active region, a gate oxide film 43 is formed on the active region, and impurities are ion-implanted in the active region to adjust a limit voltage. As shown in FIG. 11, a polysilicon film 44 is deposited on the gate oxide film 43, and the polysilicon film 44 and the gate oxide film 4 are deposited.
Etch 3 to form the gate. As shown in FIG. 12, a nitride film is formed over the entire surface of the substrate and anisotropically etched by RIE to form sidewall spacers 45 on the side surfaces of the gate 44 and the gate oxide film 44.
【００２０】前記側壁スペーサ４５をマスクとして自己
アライメントさせて高濃度のＮ+ 型不純物をフィールド
酸化膜４２と側壁スペーサ４５間のアクチブ領域にイオ
ン注入して高濃度のＮ+ 型ソース／ドレーン領域４６
ａ，４６ｂを形成する。図１３に示すように、前記フィ
ールド酸化膜４２を形成する方法と同様にＬＯＣＯＳ工
程を行ってＰ型基板４１上に厚膜の酸化膜４７を形成す
る。この時、窒化膜となる側壁スペーサ４５が厚膜の酸
化膜４７の形成を制限するブロッキング手段として作用
してフィールド酸化膜４２と側壁スペーサ４５間のアク
チブ領域上では約１０００Å乃至１５００Å厚さとな
る。厚膜の酸化膜４７の形成工程の際、ポリシリコン膜
４４の上方部位も酸化されゲートギャップ酸化膜４８が
形成される。The sidewall spacer 45 is used as a mask for self-alignment, and high-concentration N + -type impurities are ion-implanted into the active region between the field oxide film 42 and the sidewall spacer 45 to high-concentration N + -type source / drain region 46.
a and 46b are formed. As shown in FIG. 13, a LOCOS process is performed in the same manner as the method for forming the field oxide film 42, and a thick oxide film 47 is formed on the P-type substrate 41. At this time, the sidewall spacer 45 serving as a nitride film acts as a blocking means for limiting the formation of the thick oxide film 47, and the thickness is about 1000Å to 1500Å on the active region between the field oxide film 42 and the sidewall spacer 45. During the step of forming the thick oxide film 47, the upper portion of the polysilicon film 44 is also oxidized and the gate gap oxide film 48 is formed.
【００２１】図１４に示すように、残った窒化膜を除去
し、前記ゲート４４および厚膜の酸化膜４７をマスクと
して自己アライメントさせてＮ- 型およびＰ- 型不純物
を順次イオン注入する。低濃度のＮ- 型ソース／ドレー
ン領域４９ａ，４９ｂが、前記高濃度のＮ+ 型ソース／
ドレーン領域４６ａ，４６ｂに各々当接するように、前
記ゲート４４と厚膜の酸化膜４７間のアクチブ領域内に
形成され、低濃度のＰ- 型不純物領域５０ａ，５０ｂが
前記低濃度のＮ- 型ソース／ドレーン領域４９ａ，４９
ｂを覆うように、前記ゲート４４と厚膜酸化膜４７間の
アクチブ領域内に形成される。As shown in FIG. 14, the remaining nitride film is removed, the gate 44 and the thick oxide film 47 are used as a mask for self-alignment, and N − -type and P − -type impurities are sequentially ion-implanted. The low-concentration N − -type source / drain regions 49a and 49b correspond to the high-concentration N + -type source /
Drain region 46a, respectively so as to contact the 46b, it is formed in the active region between the oxide film 47 of the gate 44 and the thick, low-concentration P - -type impurity regions 50a, 50b of the low concentration N - type Source / drain regions 49a, 49
It is formed in the active region between the gate 44 and the thick oxide film 47 so as to cover b.
【００２２】これにより、高濃度のＮ+ 型ソース／ドレ
ーン領域４６ａ，４６ｂおよび低濃度のＮ- 型ソース／
ドレーン領域４９ａ，４９ｂを有するＬＤＤ構造のＭＯ
ＳＦＥＴが製造される。すなわち、Ｎ- 型およびＰ- イ
オン注入の際、厚膜の酸化膜が不純物イオン注入を制限
するブロッキング手段としてＮ- 型およびＰ- 型不純物
が厚膜の酸化膜４７を通じてはイオン注入されないの
で、低濃度のＮ- 型ソース／ドレーン領域４９ａ，４９
ｂおよびＰ- 型不純物領域５０ａ，５０ｂは、酸化膜４
７とゲート４４間のアクチブ領域にのみ形成される。As a result, the high concentration N + type source / drain regions 46a and 46b and the low concentration N − type source /
MO of LDD structure having drain regions 49a and 49b
The SFET is manufactured. That is, at the time of N − -type and P − -ion implantation, the N − -type and P − -type impurities are not ion-implanted through the thick-film oxide film 47 as a blocking means for restricting impurity ion implantation. Low concentration N - type source / drain regions 49a, 49
b and the P − -type impurity regions 50a and 50b are formed by the oxide film 4
It is formed only in the active region between 7 and the gate 44.
【００２３】図１５〜図１９は本発明の第２実施例によ
るＬＤＤ構造のＭＯＳＦＥＴ製造工程断面図である。こ
の第２実施例によるＭＯＳＦＥＴ製造工程と、前記した
第１実施例によるＭＯＳＦＥＴ製造工程との差異点は、
ゲート側壁スペーサとして、第１実施例では、単一の窒
化膜のみが使用され、第２実施例では、薄膜の窒化膜と
ポリシリコン膜とを使用する点である。FIGS. 15 to 19 are sectional views of the LDD structure MOSFET manufacturing process according to the second embodiment of the present invention. The difference between the MOSFET manufacturing process according to the second embodiment and the MOSFET manufacturing process according to the first embodiment is that
As a gate sidewall spacer, only a single nitride film is used in the first embodiment, and a thin nitride film and a polysilicon film are used in the second embodiment.
【００２４】第２実施例によるＬＤＤ構造のＭＯＳＦＥ
Ｔの製造工程を説明すれば、図１５に示すように、Ｐ型
基板６１上に通常のＬＯＣＯＳ工程により、フィールド
酸化膜６２を形成してフィールド領域およびアクチブ領
域を限定し、アクチブ領域上にゲート酸化膜６３を形成
する。ゲート酸化膜６３を形成した後、アクチブ領域に
限界電圧の調節用不純物を注入する。MOSF of LDD structure according to the second embodiment
The manufacturing process of T will be described. As shown in FIG. 15, a field oxide film 62 is formed on a P-type substrate 61 by a normal LOCOS process to define a field region and an active region, and a gate is formed on the active region. The oxide film 63 is formed. After forming the gate oxide film 63, an impurity for adjusting the limit voltage is implanted into the active region.
【００２５】図１６に示すように、ゲート酸化膜６３上
にポリシリコン膜６４を蒸着し、このポリシリコン膜６
４およびゲート酸化膜４３をパターニングしてアクチブ
領域上にゲートを形成する。図１７に示すように、基板
の全面にわたって薄膜の窒化膜とポリシリコン膜６６と
を順次蒸着し、ＲＩＥ法により異方性エッチングしてゲ
ート６４およびゲート酸化膜６３の側面に窒化膜６５と
ポリシリコン膜６６とからなる側壁スペーサを形成す
る。ついで、高濃度のＮ+ 型不純物を側壁スペーサマス
クとして自己アライメントさせてアクチブ領域内にイオ
ン注入して高濃度のＮ+ 型ソース／ドレーン領域６７
ａ，６７ｂをフィールド酸化膜４２と側壁スペーサ間の
アクチブ領域に形成する。As shown in FIG. 16, a polysilicon film 64 is deposited on the gate oxide film 63, and the polysilicon film 6 is formed.
4 and the gate oxide film 43 are patterned to form a gate on the active region. As shown in FIG. 17, a thin nitride film and a polysilicon film 66 are sequentially deposited on the entire surface of the substrate and anisotropically etched by RIE to form a nitride film 65 and a polysilicon film on the side surfaces of the gate 64 and the gate oxide film 63. A sidewall spacer made of the silicon film 66 is formed. Then, a high-concentration N + -type impurity is self-aligned as a sidewall spacer mask and ion-implanted into the active region to form a high-concentration N + -type source / drain region 67.
a and 67b are formed in the active region between the field oxide film 42 and the sidewall spacer.
【００２６】図１８に示すように、残存する側壁スペー
サ用ポリシリコン膜６６および窒化膜６５のうち、ポリ
シリコン膜６６を除去し、通常のＬＯＣＯＳ工程によ
り、前記高濃度のＮ+ 型ソース／ドレーン領域６７ａ，
６７ｂの上方に厚膜の酸化膜６８を形成する。この時、
残存する薄膜の窒化膜６５は、厚膜の酸化膜６８を形成
する時にブロッキング手段として作用して酸化膜６８が
フィールド酸化膜４２と窒化膜６５間のアクチブ領域上
では厚さが約１０００Å乃至１５００Åに形成される。As shown in FIG. 18, of the remaining sidewall spacer polysilicon film 66 and nitride film 65, the polysilicon film 66 is removed, and the high-concentration N + type source / drain is formed by a normal LOCOS process. Region 67a,
A thick oxide film 68 is formed above 67b. At this time,
The remaining thin nitride film 65 acts as a blocking means when forming the thick oxide film 68, and the oxide film 68 has a thickness of about 1000Å to 1500Å on the active region between the field oxide film 42 and the nitride film 65. Is formed.
【００２７】一方、厚膜の酸化膜を形成するためのＬＯ
ＣＯＳ工程の時、ゲート用ポリシリコン膜６４もその上
方が酸化されてゲート６４上には、ゲートギャップ酸化
膜６９が形成される。図１９に示すように、残存する窒
化膜６５を除去した後前記厚膜の酸化膜６８およびゲー
ト６４をマスクとして自己アライメントさせてＮ- 型お
よびＰ- 型不純物を順次イオン注入して低濃度のＮ- 型
ソース／ドレーン領域７０ａ，７０ｂが前記高濃度のＮ
+ 型ソース／ドレーン領域６７ａ，６７ｂに当接するよ
うに酸化膜６８とゲート６４間のアクチブ領域に形成
し、低濃度のＰ- 型不純物領域７１ａ，７１ｂが前記低
濃度のＮ- ソース／ドレーン領域６７ａ，６７ｂを覆う
ように酸化膜６８とゲート６４間のアクチブ領域に形成
する。これにより、高濃度のＮ+ 型ソース／ドレーン領
域６７ａ，６７ｂおよび低濃度のＮ- 型ソース／ドレー
ン領域７０ａ，７０ｂを有するＬＤＤ構造のＭＯＳＦＥ
Ｔを製造する。On the other hand, LO for forming a thick oxide film
During the COS process, the upper portion of the gate polysilicon film 64 is also oxidized and a gate gap oxide film 69 is formed on the gate 64. As shown in FIG. 19, after the remaining nitride film 65 is removed, self-alignment is performed using the thick oxide film 68 and the gate 64 as a mask, and N − -type and P − -type impurities are sequentially ion-implanted to reduce the concentration. The N − type source / drain regions 70a and 70b are the high concentration N
It is formed in the active region between the oxide film 68 and the gate 64 so as to be in contact with the + type source / drain regions 67a and 67b, and the low concentration P − type impurity regions 71a and 71b are the low concentration N − source / drain regions. An active region between oxide film 68 and gate 64 is formed so as to cover 67a and 67b. Thereby, the LDD structure MOSFE having the high concentration N + type source / drain regions 67a and 67b and the low concentration N − type source / drain regions 70a and 70b.
Manufacture T.
【００２８】[0028]
【発明の効果】以上説明したように、本発明のＬＤＤ構
造のＭＯＳＦＥＴは、Ｐ- 型不純物領域が低濃度のＮ-
型ソース／ドレーン領域のみを覆うように形成されてい
るので、ショートチャネル効果を減少するのみならず、
従来のＬＤＤ構造のＭＯＳＦＥＴより接合容量および限
界電圧を減少することができ、これにより、ＭＯＳＦＥ
Ｔの動作特性を向上させることができる。As described above, according to the present invention, MOSFET of the LDD structure of the present invention, P - -type impurity regions low concentrations of N -
Since it is formed so as to cover only the mold source / drain region, not only the short channel effect is reduced but also
The junction capacitance and the limit voltage can be reduced as compared with the conventional LDD structure MOSFET, and thus, the MOSFET
The operating characteristics of T can be improved.
【００２９】かつ、本発明は側壁スペーサ用窒化膜を使
用して通常のＬＯＣＯＳ工程により、厚膜の酸化膜を形
成し、この厚膜の酸化膜および側壁スペーサをマスクと
して自己アライメントさせて、イオン注入工程を行って
ＬＤＤ構造のＭＯＳＦＥＴを製造しているので、従来の
ＬＤＤ構造のＭＯＳＦＥＴの製造工程に比べて別の追加
される工程がなく、ゲート形成のためのマスク工程外に
は他のマスク工程はない。したがって、従来のマスク数
および工程数の増加なく、単純な工程でＬＤＤ構造のＭ
ＯＳＦＥＴを製造することができる。In addition, according to the present invention, a thick oxide film is formed by a normal LOCOS process using a nitride film for a sidewall spacer, and the thick oxide film and the sidewall spacer are used as a mask for self-alignment, and an ion is formed. Since the LDD structure MOSFET is manufactured by performing the implantation process, there is no additional process as compared with the conventional LDD structure MOSFET manufacturing process, and other masks are provided outside the mask process for gate formation. There is no process. Therefore, the M of the LDD structure can be formed by a simple process without increasing the number of masks and the number of processes of the related art.
OSFETs can be manufactured.
【図１】従来のホットキャリヤ効果を防止するためのＬ
ＤＤ構造のＭＯＳＦＥＴ製造工程断面図である。FIG. 1 L for preventing the conventional hot carrier effect
It is a MOSFET manufacturing process sectional view of a DD structure.
【図２】従来のホットキャリヤ効果を防止するためのＬ
ＤＤ構造のＭＯＳＦＥＴ製造工程断面図である。FIG. 2 L for preventing the conventional hot carrier effect
It is a MOSFET manufacturing process sectional view of a DD structure.
【図３】従来のホットキャリヤ効果を防止するためのＬ
ＤＤ構造のＭＯＳＦＥＴ製造工程断面図である。FIG. 3 L for preventing the conventional hot carrier effect
It is a MOSFET manufacturing process sectional view of a DD structure.
【図４】従来のショートチャネル効果を防止するための
ＬＤＤ構造のＭＯＳＦＥＴ製造工程断面図である。FIG. 4 is a sectional view of a conventional MOSFET manufacturing process having an LDD structure for preventing a short channel effect.
【図５】従来のショートチャネル効果を防止するための
ＬＤＤ構造のＭＯＳＦＥＴ製造工程断面図である。FIG. 5 is a sectional view of a conventional MOSFET manufacturing process having an LDD structure for preventing a short channel effect.
【図６】従来のショートチャネル効果を防止するための
ＬＤＤ構造のＭＯＳＦＥＴ製造工程断面図である。FIG. 6 is a sectional view of a conventional MOSFET manufacturing process having an LDD structure for preventing a short channel effect.
【図７】従来のショートチャネル効果を防止するための
ＬＤＤ構造のＭＯＳＦＥＴ製造工程断面図である。FIG. 7 is a sectional view of a conventional MOSFET manufacturing process having an LDD structure for preventing a short channel effect.
【図８】従来のショートチャネル効果を防止するための
ＬＤＤ構造のＭＯＳＦＥＴ製造工程断面図である。FIG. 8 is a sectional view of a conventional MOSFET manufacturing process having an LDD structure for preventing a short channel effect.
【図９】従来のショートチャネル効果を防止するための
ＬＤＤ構造のＭＯＳＦＥＴ製造工程断面図である。FIG. 9 is a sectional view of a conventional MOSFET manufacturing process having an LDD structure for preventing a short channel effect.
【図１０】本発明の第１実施例によるＬＤＤ構造のＭＯ
ＳＦＥＴ製造工程断面図である。FIG. 10 is an MO of an LDD structure according to a first embodiment of the present invention.
It is a SFET manufacturing process sectional view.
【図１１】本発明の第１実施例によるＬＤＤ構造のＭＯ
ＳＦＥＴ製造工程断面図である。FIG. 11 is an MO of an LDD structure according to a first embodiment of the present invention.
It is a SFET manufacturing process sectional view.
【図１２】本発明の第１実施例によるＬＤＤ構造のＭＯ
ＳＦＥＴ製造工程断面図である。FIG. 12 is an MO of an LDD structure according to a first embodiment of the present invention.
It is a SFET manufacturing process sectional view.
【図１３】本発明の第１実施例によるＬＤＤ構造のＭＯ
ＳＦＥＴ製造工程断面図である。FIG. 13 is an MO of an LDD structure according to a first embodiment of the present invention.
It is a SFET manufacturing process sectional view.
【図１４】本発明の第１実施例によるＬＤＤ構造のＭＯ
ＳＦＥＴ製造工程断面図である。FIG. 14 is an MO of an LDD structure according to a first embodiment of the present invention.
It is a SFET manufacturing process sectional view.
【図１５】本発明の第２実施例によるＬＤＤ構造のＭＯ
ＳＦＥＴ製造工程断面図である。FIG. 15 is an MO of an LDD structure according to a second embodiment of the present invention.
It is a SFET manufacturing process sectional view.
【図１６】本発明の第２実施例によるＬＤＤ構造のＭＯ
ＳＦＥＴ製造工程断面図である。FIG. 16 is an MO of an LDD structure according to a second embodiment of the present invention.
It is a SFET manufacturing process sectional view.
【図１７】本発明の第２実施例によるＬＤＤ構造のＭＯ
ＳＦＥＴ製造工程断面図である。FIG. 17 is an MO of an LDD structure according to a second embodiment of the present invention.
It is a SFET manufacturing process sectional view.
【図１８】本発明の第２実施例によるＬＤＤ構造のＭＯ
ＳＦＥＴ製造工程断面図である。FIG. 18 is an MO of an LDD structure according to a second embodiment of the present invention.
It is a SFET manufacturing process sectional view.
【図１９】本発明の第２実施例によるＬＤＤ構造のＭＯ
ＳＦＥＴ製造工程断面図である。FIG. 19 is an MO of an LDD structure according to a second embodiment of the present invention.
It is a SFET manufacturing process sectional view.
４１ Ｐ型基板 ４２ フィールド酸化膜 ４３ ゲート酸化膜 ４４ ゲート ４５ 側壁スペーサ ４６ Ｎ+ 型ソース／ドレーン領域 ４７ 絶縁膜 ４８ ギャップ酸化膜 ４９ Ｎ- 型ソース／ドレーン領域 ５０ Ｐ- 型不純物領域41 P-type substrate 42 Field oxide film 43 Gate oxide film 44 Gate 45 Side wall spacer 46 N + type source / drain region 47 Insulating film 48 Gap oxide film 49 N − type source / drain region 50 P − type impurity region
Claims (12)
フィールド領域およびアクチブ領域を限定するステップ
と；アクチブ領域上にゲート酸化膜を形成するステップ
と；アクチブ領域に限界電圧の調節用不純物をイオン注
入するステップと；基板の全ての表面にわたってポリシ
リコン膜を形成するステップと；前記ポリシリコン膜お
よび酸化膜をエッチングしてアクチブ領域上にゲートを
形成するステップと；基板の全面にわたって絶縁膜を形
成するステップと；前記絶縁膜をＲＩＥ法により異方性
エッチングしてゲートおよびゲート酸化膜の側面に側壁
スペーサを形成するステップと；前記側壁スペーサをマ
スクとして自己アライメントさせて高濃度の第２導電型
の不純物をイオン注入して高濃度の第２導電型のソース
／ドレーン領域を形成するステップと；厚膜の絶縁膜お
よびゲートギャップ絶縁膜を形成するステップと；側壁
スペーサ用絶縁膜を除去するステップと；前記ゲートお
よび厚膜の絶縁膜をマスクとして自己アライメントさせ
てアクチブ領域に、第２導電型の低濃度不純物および第
１導電型の低濃度不純物をイオン注入して前記高濃度の
ソース／ドレーン領域に当接するように、低濃度の第２
導電型のソース／ドレーン領域を形成し、 前記低濃度の第２導電型のソース／ドレーン領域を覆う
ように低濃度の第１導電型の不純物領域を形成するステ
ップと；を含むことを特徴とするＭＯＳＦＥＴ製造方
法。1. A step of forming an oxide film on a substrate of the first conductivity type to define a field region and an active region; a step of forming a gate oxide film on the active region; adjusting a limit voltage in the active region. Ion implantation of impurities for use; forming a polysilicon film over the entire surface of the substrate; etching the polysilicon film and the oxide film to form a gate on the active region; covering the entire surface of the substrate Forming an insulating film; anisotropically etching the insulating film by an RIE method to form sidewall spacers on side surfaces of the gate and the gate oxide film; Ion-implanting impurities of the second conductivity type to form high-concentration second conductivity type source / drain regions. A step of forming a thick insulating film and a gate gap insulating film; a step of removing the sidewall spacer insulating film; a self-alignment using the gate and the thick insulating film as a mask in the active region , A low concentration second impurity of the second conductivity type and a low concentration impurity of the first conductivity type are ion-implanted to contact the high concentration source / drain region.
Forming a conductivity type source / drain region, and forming a low concentration first conductivity type impurity region so as to cover the low concentration second conductivity type source / drain region. Method for manufacturing MOSFET.
ことを特徴とする請求項１記載のＭＯＳＦＥＴ製造方
法。2. The MOSFET manufacturing method according to claim 1, wherein the sidewall spacer insulating film is a nitride film.
導電型のソース／ドレーン領域上のみ形成されるように
制限するブロッキング手段として作用することを特徴と
する請求項２記載のＭＯＳＦＥＴ製造方法。3. The nitride film is a thick insulating film which has a high concentration of the second insulating film.
3. The method of manufacturing a MOSFET according to claim 2, wherein the MOSFET acts as a blocking means for restricting formation only on a conductive type source / drain region.
徴とする請求項１記載のＭＯＳＦＥＴ製造方法。4. The MOSFET manufacturing method according to claim 1, wherein the thick insulating film is an oxide film.
０Åであることを特徴とする請求項４記載のＭＯＳＦＥ
Ｔ製造方法。5. The oxide film having a thickness of 1000Å to 150
The MOSFE according to claim 4, characterized in that it is 0Å.
T manufacturing method.
れることを特徴とする請求項４記載のＭＯＳＦＥＴ製造
方法。6. The MOSFET manufacturing method according to claim 4, wherein the oxide film is formed by a LOCOS process.
ことを特徴とする請求項１記載のＭＯＳＦＥＴ製造方
法。7. The method of manufacturing a MOSFET according to claim 1, wherein the gate gap insulating film is an oxide film.
シリコンの上側部位が酸化されて形成されたことを特徴
とする請求項７記載のＭＯＳＦＥＴ製造方法。8. The method of manufacturing a MOSFET according to claim 7, wherein the gate gap oxide film is formed by oxidizing an upper portion of the gate polysilicon.
ステップと；アクチブ領域上にゲート酸化膜を形成する
ステップと；アクチブ領域に限界電圧の調節用不純物を
イオン注入するステップと；基板の全ての表面にわたっ
てポリシリコン膜を形成するステップと；前記ポリシリ
コン膜およびゲート酸化膜をエッチングしてアクチブ領
域上にゲートを形成するステップと；基板の全面にわた
って絶縁膜を形成するステップと；前記薄膜の絶縁膜上
に半導体層を形成するステップと；前記薄膜の絶縁膜お
よび半導体層をＲＩＥ法により異方性エッチングしてゲ
ートおよびゲート酸化膜の側面に側壁スペーサを形成す
るステップと；前記側壁スペーサをマスクとして自己ア
ライメントさせて高濃度の第２導電型の不純物をイオン
注入して高濃度の第２導電型のソース／ドレーン領域を
形成するステップと；前記側壁スペーサ用半導体層を除
去するステップと；厚膜の絶縁膜およびゲートギャップ
絶縁膜を形成するステップと；前記側壁スペーサ用薄膜
の絶縁膜を除去するステップと；前記ゲートおよび厚膜
の絶縁膜をマスクとして自己アライメントさせてアクチ
ブ領域に、第２導電型の低濃度不純物および第１導電型
の低濃度不純物をイオン注入して前記高濃度のソース／
ドレーン領域に当接するように、低濃度の第２導電型の
ソース／ドレーン領域を形成し、 前記低濃度の第２導電型のソース／ドレーン領域を覆う
ように低濃度の第１導電型の不純物領域を形成するステ
ップと；を含むことを特徴とするＭＯＳＦＥＴ製造方
法。9. A step of forming an oxide film on a substrate of the first conductivity type; a step of forming a gate oxide film on an active region; a step of ion-implanting a limiting voltage adjusting impurity into the active region; Forming a polysilicon film over the entire surface of the substrate; etching the polysilicon film and the gate oxide film to form a gate on the active region; forming an insulating film over the entire surface of the substrate; Forming a semiconductor layer on the thin insulating film; anisotropically etching the thin insulating film and the semiconductor layer by an RIE method to form sidewall spacers on side surfaces of the gate and the gate oxide film; Self-alignment is performed using the sidewall spacers as a mask, and high-concentration second-conductivity-type impurities are ion-implanted so that high-concentration first A step of forming a source / drain region of two conductivity type; a step of removing the semiconductor layer for sidewall spacers; a step of forming a thick insulating film and a gate gap insulating film; a thin insulating film for sidewall spacers Removing the second conductive type low concentration impurity and the first conductive type low concentration impurity into the active region by self-alignment using the gate and the thick insulating film as a mask. Source of /
A low-concentration second conductivity type source / drain region is formed so as to abut the drain region, and a low-concentration first conductivity type impurity is formed so as to cover the low-concentration second conductivity type source / drain region. Forming a region; and a method of manufacturing a MOSFET, comprising:
あることを特徴とする請求項９記載のＭＯＳＦＥＴ製造
方法。10. The method of manufacturing a MOSFET according to claim 9, wherein the insulating film of the spacer thin film is a nitride film.
膜であることを特徴とする請求項９記載のＭＯＳＦＥＴ
製造方法。11. The MOSFET according to claim 9, wherein the spacer semiconductor layer is a polysilicon film.
Production method.
２導電型のソース／ドレーン領域上のみ形成されるよう
に制限するブロッキング手段として作用することを特徴
とする請求項１０記載のＭＯＳＦＥＴ製造方法。12. The nitride film acts as a blocking means for restricting the thick insulating film to be formed only on the high-concentration second conductivity type source / drain regions. MOSFET manufacturing method.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10235/1992 | 1992-06-12 | ||
| KR1019920010235A KR950002196B1 (en) | 1992-06-12 | 1992-06-12 | Making method of ldd for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0653231A true JPH0653231A (en) | 1994-02-25 |
| JP3394562B2 JP3394562B2 (en) | 2003-04-07 |
Family
ID=19334606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16333193A Expired - Fee Related JP3394562B2 (en) | 1992-06-12 | 1993-06-08 | MOSFET manufacturing method |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP3394562B2 (en) |
| KR (1) | KR950002196B1 (en) |
| DE (1) | DE4318866C2 (en) |
| TW (1) | TW234773B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5444002A (en) * | 1993-12-22 | 1995-08-22 | United Microelectronics Corp. | Method of fabricating a short-channel DMOS transistor with removable sidewall spacers |
| EP2073391B1 (en) | 2007-12-21 | 2011-06-08 | Fujitsu Ten Limited | Method of operating a radio tuner, for detecting and responding to effects of tunnel situations on radio reception by an in-vehicle radio receiver |
-
1992
- 1992-06-12 KR KR1019920010235A patent/KR950002196B1/en not_active IP Right Cessation
-
1993
- 1993-04-02 TW TW082102471A patent/TW234773B/zh not_active IP Right Cessation
- 1993-06-07 DE DE4318866A patent/DE4318866C2/en not_active Expired - Fee Related
- 1993-06-08 JP JP16333193A patent/JP3394562B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE4318866A1 (en) | 1993-12-16 |
| DE4318866C2 (en) | 1997-01-23 |
| TW234773B (en) | 1994-11-21 |
| KR950002196B1 (en) | 1995-03-14 |
| KR940001460A (en) | 1994-01-11 |
| JP3394562B2 (en) | 2003-04-07 |
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