JPH08293599A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide the structure of a semiconductor device and a method for manufacturing the same in which a heavily doped layer or a three-layer LDD structure for reducing the contact resistance in a source-drain region can be formed relatively easily and accurately. CONSTITUTION: A plurality of times of depositing an oxide insulating film and anisotropically etching it are conducted, at least once or more of the plurality of anisotropically etchings are conducted under the condition where the one sidewall side of a gate electrode 74 is covered with a mask. Thus, sidewall spaces 78, 83 having different widths are formed at both sidewalls of the electrode 74, with the spacers 78, 83 of the one sidewall used as masks a heavily doped n-type layer 87 is so formed on the semiconductor substrate surface of only one side as to be introduced inside source and drain regions 77, 85.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a field effect transistor and a method of manufacturing the same, and more particularly, to alleviate a peak electric field intensity of a drain depletion layer generated in a pinch-off state to suppress a hot carrier effect. LD
MOS (Meta) with D (Lightly Doped Drain) structure
The present invention relates to a structure of a semiconductor device including an Oxide Semiconductor) type field effect transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art The basic structure of a MOS type field effect transistor is such that a source serving as a carrier and a carrier are provided on both sides of a so-called MOS capacitor having a metal electrode provided on a Si substrate with a thin oxide film interposed. The drain and the takeout are arranged. The metal electrode on the oxide film has a function of controlling the conductance between the source / drain and is called a gate electrode. As the material of the gate electrode, polycrystalline silicon doped with impurities, metal silicide formed by heat-treating refractory metal such as tungsten deposited on the polycrystalline silicon in an inert gas, and the like are often used. .

When the voltage of the gate electrode (gate voltage) is lower than the threshold voltage Vth required to invert the conductivity type in the vicinity of the Si substrate surface (channel) between the source / drain, either of the source / drain Are also separated by the pn junction, and no current flows. When a gate voltage of Vth or more is applied, the conductivity type of the channel surface is inverted, a layer of the same conductivity type as the source / drain is formed in this portion, and a current between the source / drain flows.

When the impurity concentration distribution at the boundary between the source / drain and the channel changes rapidly, the electric field strength at this portion increases. The electric field causes the carriers to obtain energy, and so-called hot carriers are generated.
Then, the carriers are injected into the gate insulating film,
An interface state is generated at the interface between the gate insulating film and the semiconductor substrate, or trapped in the gate insulating film. Therefore, the threshold voltage and transconductance of the MOS transistor deteriorate during operation. This is a deterioration phenomenon of the MOS transistor due to hot carriers.
Also, the so-called avalanche breakdown voltage against avalanche breakdown between the source and drain is deteriorated by the hot carriers.
Therefore, the n-type impurity concentration near the source / drain is lowered to moderate the concentration distribution change, thereby relaxing the electric field intensity, thereby suppressing deterioration of the MOS transistor due to hot carriers, and at the same time, avalanche breakdown voltage of the source / drain. The MOS-type LDD structure field effect transistor has been improved.

As a conventional method for manufacturing a MOS type LDD structure field effect transistor, for example, FIGS.
There are the following. In this manufacturing method, first, a so-called LOCOS (Local Oxidation of) is formed on the p-type semiconductor substrate 1.
Silicon) is used to form the gate insulating film 3 in the element formation region surrounded by the element isolation insulating film 2 (FIG. 33). Next, in order to control the threshold voltage, p-type impurities such as boron ions are implanted into the entire surface of the semiconductor substrate 1 as needed to form the ion-implanted region 4 (FIG. 34). afterwards,
A film of polycrystalline silicon is deposited on the entire surface of the gate insulating film 3 by the low pressure CVD method, and the gate electrode 5 is formed by the photoengraving technique and the reactive ion etching (FIG. 3).
5). The gate electrode 5 may be formed of a two-layer film of polycrystalline silicon and a refractory metal such as tungsten, molybdenum, or titanium, or a silicide thereof, instead of polycrystalline silicon. The gate electrode 5 is doped with, for example, phosphorus ions in order to enhance the conductivity.

Next, using the gate electrode 5 as a mask, n-type impurities such as phosphorus ions and arsenic ions are vertically injected into the surface of the semiconductor substrate 1 to form an n-type ion-implanted layer 6 (FIG. 36). . After that, an insulating film such as silicon dioxide is deposited on the entire surface of the semiconductor substrate 1 by the low pressure CVD method or the atmospheric pressure CVD method, and anisotropic etching is performed on the insulating film to form the sidewall spacers 7 (FIG. 37). Next, the surface of the semiconductor substrate 1 is vertically irradiated with n-type impurities such as phosphorus ions and arsenic ions by using both the gate electrode 5 and the sidewall spacers 7 as masks, and the ions are injected into the injection layer 6.
An n-type injection layer 8 having a higher concentration than that is formed (FIG. 38).
After that, a heat treatment for activating the implanted impurity ions is performed to complete the MOS type LDD structure field effect transistor.

MO obtained by the above conventional manufacturing method
According to the S-type LDD structure field effect transistor, since the ion implantation region 6 having a lower concentration is provided on the side of the source / drain region adjacent to the channel, the change in the impurity concentration distribution of the source / drain region is alleviated. The electric field strength in this portion is lowered, and the deterioration phenomenon of the transistor due to hot carriers is prevented.

However, the conventional MOS LDD described above is used.
In the method for manufacturing the structure field effect transistor, a pair of sidewall spacers 7, 7 is simultaneously formed by depositing the same oxide insulating film on both side walls of the gate electrode 5 and anisotropically etching the same, so that it is necessary. Even when it is desired to change the concentration profiles of the impurity diffusion layers of the pair of source / drain regions depending on the performance of the gate electrode 5, the optimum sidewall spacer width required for each side wall of the gate electrode 5 is set. There was a problem that I could not get it.

As a solution to the above-mentioned conventional problems,
The inventor of the present invention discloses in Japanese Patent Laid-Open No. 4-218925.
A method of manufacturing the semiconductor device shown in FIGS. 39 to 46 has been proposed.

In this manufacturing method, first, a polycrystalline silicon layer 54 is deposited on the surface of a p-type semiconductor substrate 52 separated by an element isolation insulating film 51 with a gate oxide film 53 interposed, and further oxidized. After forming the insulating film 55,
Except for the gate electrode portion 56, the gate insulating film 53 and the polycrystalline silicon layer 54 are removed by photoetching.
The structure shown in 9 is formed. Then, n-type impurity ions such as phosphorus and arsenic are implanted, and the low-concentration n-type diffusion layers 57 are formed on the left and right sides of the gate electrode portion 56 as a mask (FIG. 40). Next, after depositing an oxide insulating film such as silicon oxide on the entire surface of the semiconductor substrate 52 by the CVD method,
By performing anisotropic etching, the sidewall spacers 58 are formed (FIG. 41). After that, on the semiconductor substrate 52, the right half from the center of the gate electrode portion 56 is covered with a resist film 59, n-type impurity ions are implanted, and the sidewall spacer 58 is used as a mask to form a high-concentration n-type region 60 in the source region. Formed (FIG. 42).

Next, after removing the resist film 59, an oxide insulating film 61 of silicon oxide or the like is formed on the entire surface of the p-type semiconductor substrate 52 by CVD (FIG. 43). afterwards,
A resist film 62 is selectively formed except the region from the center of the gate electrode portion 56 to the drain region (FIG. 44),
In that state, anisotropic etching is performed to form the sidewall spacer 63 and the contact hole 64. Then, by implanting n-type impurity ions using the sidewall spacer 63 as a mask, a high-concentration n-type diffusion layer 65 is formed in the drain region side in a self-aligned manner (FIG. 45).

Next, a wiring layer 66 in which a metal layer or a doped polycrystalline silicon layer is selectively formed so as to be electrically connected to the high concentration n-type diffusion layer 65 in the contact hole 64.
Are formed (FIG. 46).

According to this manufacturing method, the sidewalls having different widths are not formed separately, but the deposition of the oxide insulating film and the anisotropic etching thereof are sequentially repeated a plurality of times to make the sidewall width smaller. Since it is performed by covering with a resist as needed, the efficiency of forming the side wall spacers is improved as compared with the case where the side wall spacers having different widths are formed separately. In addition, sidewall spacers having different widths can be formed according to the required characteristics for each sidewall of the gate electrode.

[0014]

However, as shown in FIG.
38 to 46, the manufacturing method disclosed in the above publication discloses a MOS having a two-layer LDD structure in which the offset amounts of the low-concentration n-type diffusion layers 57 are different on both side walls of one gate electrode. Concentration n-type layer at the portion connected to the conductive wiring layer on the surface of the source / drain region in addition to the formation of the three-layer LDD structure, which is intended only for the method of manufacturing the field effect transistor It was not intended for the formation of.

The present invention utilizes the advantages of the manufacturing method already proposed by the inventor in the above publication, and is connected to a MOS field effect transistor having a three-layer LDD structure or a conductive wiring layer in a source / drain region. It is an object of the present invention to provide a semiconductor device structure capable of forming a high-concentration impurity layer in a self-aligning manner in a region and a manufacturing method thereof.

[0016]

A semiconductor device according to the present invention for solving the above-mentioned problems is a semiconductor device having a field-effect transistor, wherein the field-effect transistor is at least near the surface. A semiconductor substrate having a conductive type region, a gate electrode formed on the semiconductor substrate with a gate insulating film interposed, and formed on one side wall surface of the gate electrode and formed of a predetermined number of layers of insulating film. A first sidewall spacer having a predetermined width and an insulating film of a predetermined number of layers formed on the other sidewall surface of the gate electrode and different from the first sidewall spacer, and the first sidewall A second sidewall spacer having a width different from that of the spacer; and a second sidewall spacer formed on the surface of the semiconductor substrate from the vicinity immediately below both side walls of the gate electrode to the outside. It includes a pair of source / drain regions of the conductivity type, and a high-concentration second conductivity type layer formed on the semiconductor substrate surface as a part near just below the side wall portion in contact with the second sidewall spacers of the semiconductor substrate surface. The high-concentration second-conductivity-type layer has a second-conductivity-type impurity concentration higher than that of the source / drain regions, and is formed inside the region of the pair of source / drain regions on the side of the second sidewall spacer. There is.

The semiconductor device of the present invention according to claim 2 is
In addition to the structure described in claim 1, a conductive layer is provided which covers the surface of the second sidewall and is in contact with the high concentration second conductivity type layer.

In the semiconductor device of the present invention as defined in claim 3, the conductive layer includes polycrystalline silicon doped with an impurity layer of the second conductivity type, and the high-concentration second conductivity type layer is formed from the conductive layer. The second conductivity type impurities are formed in a self-aligned manner by thermal diffusion.

A method for manufacturing a semiconductor device according to a fourth aspect of the present invention is a method for manufacturing a semiconductor device including a field effect transistor, wherein the main part of the semiconductor substrate has a region of the first conductivity type at least near the main surface. The step of forming a gate electrode on the surface with a gate insulating film interposed, the first sidewall spacer on one side wall of the gate electrode, and the first sidewall spacer on the other side wall of the gate electrode Forming second side wall spacers having different widths; forming a source / drain region by implanting a second conductivity type impurity into the semiconductor substrate surface using at least the gate electrode as a mask; By using the second sidewall spacer as a mask, the second conductivity type impurity is provided only on the front second sidewall spacer side of the semiconductor substrate surface. Type, the neighborhood immediately below the side end portion of the semiconductor substrate surface position of the second sidewall spacers and end, and the second of the pair of source / drain regions
And a step of forming the high concentration second conductivity type layer so as to be inside the region on the side wall spacer side. The step of forming the first and second sidewall spacers is performed by depositing an insulating film and performing anisotropic etching a plurality of times, and the step of performing anisotropic etching a plurality of times is performed at least once. The width of each of the first and second sidewall spacers is different from each other by being performed in a state in which one of the side walls of the gate electrode is covered with a mask.

A method of manufacturing a semiconductor device according to a fifth aspect is a method of manufacturing a semiconductor device including a field effect transistor, wherein the semiconductor device has a region of the first conductivity type at least near the main surface on the main surface of the semiconductor substrate. , A step of forming a gate electrode with a gate insulating film interposed, and an oxide insulating film is deposited on a semiconductor substrate so as to cover the upper surface and both side wall surfaces of the gate electrode, and anisotropic etching is applied to this to form a gate insulating film. A step of forming a pair of first-layer sidewall spacers on both side wall surfaces of the electrodes, and depositing an oxide insulating film on the semiconductor substrate so as to cover the upper surface of the gate electrode and the first-layer sidewall spacers. Anisotropic etching is performed only on one side wall side of the gate electrode so that the second side wall spacer is formed on the side wall spacer of the first layer on one side wall side of the gate electrode. And a step of forming a gate electrode, or using the gate electrode alone or the gate electrode and the sidewall spacer of the first layer as a mask, implanting a second conductivity type impurity into the semiconductor substrate to form a pair of source / drain regions. Step, and using the gate electrode, the first-layer sidewall spacer, and the second-layer sidewall spacer as a mask, the second-conductivity-type impurities are formed on the surface of the semiconductor substrate only on the side where the second-layer sidewall spacer is formed. And forming a high-concentration second-conductivity-type layer having a higher concentration than the source / drain regions inside the region on the side wall side of one of the pair of source / drain regions.

In a method of manufacturing a semiconductor device according to a sixth aspect of the present invention, the second conductivity type impurity is formed on the semiconductor substrate after the step of forming the source / drain regions in the manufacturing method according to the fifth aspect. Forming a doped polycrystalline silicon layer, and patterning the polycrystalline silicon layer to form the surface of the second sidewall spacer and the surface of the semiconductor substrate in the region where the high-concentration second conductivity type layer is to be formed. And a step of forming a conductive layer in contact with. Then, the step of forming the high-concentration second conductivity type layer includes
After the step of forming the polycrystalline silicon layer, heat treatment is performed to thermally diffuse the second conductivity type impurity from the polycrystalline silicon layer or the conductive layer after patterning the layer to the surface of the semiconductor substrate.

[0022]

According to the semiconductor device of the present invention as set forth in claim 1, the second sidewall spacer has a larger number of layers and width than the first sidewall spacer, and the high-concentration second conductivity type layer. Has a structure in which one end of the second sidewall spacer is located immediately below a side end portion of the second sidewall spacer, so that the concentration distribution of the source / drain region and the source / drain region of the high-concentration second conductivity type layer are formed in the formation process. The positional relationship can be appropriately controlled by each layer of the first and second sidewall spacers.

The structure of the semiconductor device according to the first aspect is formed relatively efficiently and highly accurately by using the process according to the fourth aspect. That is, when forming side wall spacers having different widths on both side walls of the gate electrode, instead of forming them separately, deposition of an oxide insulating film and its anisotropic etching are sequentially repeated several times to form side wall spacers. Since the position where the spacer width should be made smaller is covered with a mask as necessary, the sidewall spacers at each stage are formed at the end of the gate electrode each time each layer of the individual sidewall spacers made up of a plurality of layers is formed. It can be used as a mask for setting different offset amounts from a part, for example, a source / source of an LDD structure having a predetermined offset amount.
A drain electrode is formed, and a high-concentration impurity layer for reducing contact resistance is formed on the surface of the semiconductor substrate at the connection between the conductive layer connected to the surface of the source / drain region and the source / drain region. It is possible to control the offset amount from the end of the with high accuracy and to form in a self-aligned manner.

Further, the semiconductor device of the present invention according to claim 1 realizes a structure further comprising the conductive layer according to claim 2 or 3 as an actual device, and such a semiconductor device comprises: As in the method for manufacturing a semiconductor device according to the present invention as set forth in claim 6, the conductive layer is formed by using a polycrystalline silicon layer doped with the second conductivity type, and heat treatment is applied to the polycrystalline silicon layer to form a layer in the polycrystalline silicon layer. It can be formed by thermally diffusing the second conductivity type impurity onto the surface of the semiconductor substrate, that is, by so-called autodoping.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIG.
Or, it demonstrates based on FIG.

In this embodiment, first, a polycrystalline silicon layer 74 is deposited on the surface of the p-type semiconductor substrate 72 separated by the element isolation insulating film 71 with the gate insulating film 73 interposed. After forming the oxide insulating film 75, the gate insulating film 73 and the polycrystalline silicon layer 74 are removed by photoetching leaving the gate electrode portion 76.
The structure shown in FIG. 1 is formed. Next, n such as phosphorus and arsenic
Type impurity ions are implanted, and the low-concentration n-type diffusion layers 77 are formed on the left and right sides of the gate electrode section 76 as a mask (FIG. 2). As the ion implantation conditions for forming the low concentration n-type diffusion layer 77, when phosphorus is used as the n-type impurity, the dose amount is 5 × 10 ^{12 to} 5 × 10 ¹⁴ / cm ² , and the implantation energy is 5 KeV to 60 KeV. Is preferred. When arsenic is used as the n-type impurity, the dose is 5 × 10 ^{12 to} 5 × 10 ¹⁴ / cm as in the case of phosphorus.
² is preferable and the implantation energy is 15 KeV to 15
It is preferably 0 KeV. The impurity implantation step may be performed with an angle of 0 ° to 70 ° from the normal line direction of the semiconductor substrate surface, and the range of the implantation energy includes the case where such a variation in the implantation angle is taken into consideration. I'm out.

Next, the semiconductor substrate 72 is formed by the CVD method.
After depositing an oxide insulating film such as silicon oxide on the entire upper surface (FIG. 3), anisotropic etching is performed to form first-layer sidewall spacers 78, 78 on both side walls of the gate electrode portion 76. (Fig. 4). Then, using the gate electrode portion 76 and the pair of first-layer sidewall spacers 78, 78 as a mask, n-type impurities such as phosphorus and arsenic are implanted, and high-concentration n-type diffusion of the source / drain regions of the LDD structure is performed. The n ⁺ layers 85, 85 to be the layers are formed (FIG. 5). Ion implantation conditions for forming the n ⁺ layer are as follows: when the n-type impurity is phosphorus, the dose amount is 5 × 1.
0 ¹⁴ to 1 × 10 ¹⁶ / cm ² , implantation energy is 10 to 60
KeV is preferable, and when the n-type impurity is arsenic, the dose amount is 5 × 10 ¹⁴ to 1 × as in the case of phosphorus.
It is preferable that the implantation energy is 10 ¹⁶ / cm ² and the implantation energy is 20 to 150 KeV.

N after the source / drain regions are formed
The target values of the concentrations of the ⁻ layers 77 and 77 and the ⁺ layers 85 and 85 are 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ , respectively.
It is preferably 5 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ .

Next, as shown in FIG. 6, an oxide insulating film 81 having a predetermined thickness is deposited on the entire surface of the semiconductor substrate 72, and then a region from the center of the gate electrode portion 76 to one side of the source / drain region is formed. Except for this, the resist film 82 is selectively formed (FIG. 7), and anisotropic etching is performed in that state to form the sidewall spacers 83 and the contact holes 8.
4 and (FIG. 8). Then, as shown in FIG.
An n-type impurity-doped polycrystalline silicon layer 86a is formed on the entire surface of the semiconductor substrate 72, and heat treatment is applied to the polycrystalline silicon layer 86a.
The n-type impurity doped in the polycrystalline silicon layer 86a is
A high concentration n-type impurity layer (n ²⁺ layer) 87 having a concentration higher than that of the n ⁺ layer 85 is formed by thermal diffusion on the surface of the semiconductor substrate (FIG. 10). Then, the polycrystalline silicon layer 86a is subjected to predetermined patterning to form the conductive layer 86 connected to the source / drain regions in the high-concentration n-type impurity layer 87 (FIG. 11).

In the above embodiment, the heat treatment for forming the high-concentration n-type impurity layer 86 is performed before the conductive layer 86 is patterned. However, the heat treatment is performed after the conductive layer 86 is patterned. It can also be formed by thermally diffusing n-type impurities contained in the conductive layer 86 onto the surface of the semiconductor substrate 72.

The polycrystalline silicon layer 86a or the polycrystalline silicon layer 86a
The concentration of n-type impurities in the conductive layer 86 after turning and
In the case of either phosphorus or arsenic as the n-type impurity
Also in 5-6 × 10²⁰/ Cm³Something used
Up to 5 × 10^{twenty one}/ Cm ³Can be used up to a degree
Is. Polycrystalline silicon having such n-type impurity concentration
So-called auto from the con layer 86a or the conductive layer 86
N formed by dope²⁺And the target value for the concentration of layer 87
Then, the finished product is 5 × 10¹⁹~ 5 × 10^{twenty one}/ Cm³In
Is set.

According to the present embodiment, the pair of source / drain regions having the symmetrical LDD structure has a width of the n ⁻ layer 77 at the surface of the semiconductor substrate 72 of the sidewall spacers 78, 78 of the first layer. The width, that is, the amount of offset of the n ⁺ layer 85 from the side edge of the gate electrode portion 76 is formed in a self-aligned and highly accurate position control so as to substantially match the width. Further, the distance from the end of the n ²⁺ layer 87 on the side of the gate electrode portion 76 is also surely controlled in a self-aligned manner by the sidewall spacer 78 of the first layer and the sidewall spacer 83 of the second layer. The n ²⁺ layer 87 is the n ⁺ layer 85
It is controlled so that it can be put inside.

Although the polycrystalline silicon layer 86a doped with an n-type impurity is used as the conductive material for forming the conductive layer 86, amorphous silicon may be used instead of the polycrystalline silicon layer. Even when amorphous silicon is used, the concentration of n-type impurities contained therein and the heat treatment conditions for thermal diffusion are the same as those when polycrystalline silicon is used.

Further, formation of the n ²⁺ layer 87 by thermal diffusion as described above does not necessarily need to include an independent heat treatment step only for that purpose, and for example, heat treatment for activating the source / drain regions is performed. It is also possible to simultaneously perform the heat treatment step for another purpose such as performing.

Further, in the step of forming the n ²⁺ layer 87, without using so-called autodoping, as shown in FIG. 12, the gate electrode portion 76, the sidewall spacers 83 and the oxide insulating film 81 are used as a mask to remove phosphorus. It can also be performed by ion-implanting n-type impurities such as arsenic and arsenic.

Next, a second embodiment of the present invention will be described with reference to FIGS. In this embodiment, the same or corresponding elements as those in the first embodiment are designated by the same reference numerals and detailed description thereof will be omitted.

In the present embodiment, first, after the steps similar to those described with reference to FIGS. 1 to 4 are performed, as shown in FIG. 13, the region on the right side from the center of the gate electrode portion 76 is a resist film. By covering with 79 and implanting an n-type impurity such as phosphorus or arsenic, an n ⁺ layer 85 is formed only in the region on the left side of the gate electrode portion 76. Thereafter, as shown in FIG. 12B, after removing the resist film 79, an oxide insulating film 81 having a predetermined thickness is deposited on the entire surface of the semiconductor substrate 72. Then, the gate electrode portion 76 is formed on the upper surface of the oxide insulating film 81.
A resist film 82 is formed by patterning so that only the region from the center to the right source / drain region is opened. In this state, the oxide insulating film 81 is anisotropically etched, and the resist film 82 is removed to obtain the structure shown in FIG.

After that, through the steps similar to those described with reference to FIGS. 10 and 11, the structure shown in FIG.
That is, the patterned conductive layer 86 and the n ²⁺ layer 87.
The structure including is completed. Regarding the material and the impurity concentration of the conductive layer 86, the method of forming the n ²⁺ layer 87, and the like, the same method as in the first embodiment can be applied.

The manufacturing method of this embodiment is a DRAM (Dynamic
When applied to the process of forming a memory cell of a Random Access Memory), the process shown in FIGS. 17 to 20 is continuously performed.

That is, first, as shown in FIG. 17, a conductive layer 89 is formed so as to cover the exposed surface of the conductive layer 86 with an insulating film 88 interposed. Then, the semiconductor substrate 7
2, an interlayer insulating film 91 is formed on the entire surface, and a resist film 92 is formed on the surface of the interlayer insulating film 91 at a position where a contact hole is to be formed by patterning, and anisotropic etching is performed using the resist film 92 as a mask. A contact hole 100 reaching the upper surface of the semiconductor substrate 72 is formed (FIG. 18).

Next, an impurity-doped polycrystalline silicon layer 93 is formed on the upper surface of the interlayer insulating film 91 including the inside of the contact hole 100 (FIG. 19), and heat treatment is applied to the polycrystalline silicon layer 93. 20, the high-concentration n-type impurity layer (n ³⁺ layer) 94 having the n-type impurity concentration higher than that of the n ⁺ layer 85 is thermally diffused.
Are formed inside the n ⁺ layer 85.

The ion implantation conditions and the target concentration values for forming the n ³⁺ layer 94 are n ²⁺ in the first embodiment.
It can be set to the same value as the layer.

When the structure shown in FIG. 20 is a DRAM memory cell, conductive layer 86 is a storage node of a capacitor, insulating film 88 is a capacitor insulating film, and conductive layer 8 is formed.
9 is a cell plate, and the polycrystalline silicon layer 93 is a bit line.

In the step of forming the n ²⁺ layer 94 in this embodiment, the so-called auto-doping from the polycrystalline silicon layer 93 is not used, but the contact hole is formed at the stage shown in FIG. 18 as shown in FIG. It can also be formed by ion-implanting n-type impurities through 100.

As described above, according to this embodiment, in the MOS type field effect transistor having the asymmetric LDD structure, the inside of the source / drain region (n ⁻ layer 77) not having the double structure is appropriately arranged. The n ³⁺ layer can be formed relatively easily at the controlled position. As a result, a preferred manufacturing process for forming the memory cells of the DRAM is provided.

In this embodiment, FIGS. 17 to 2 are used.
It goes without saying that the process for forming the memory cell of the DRAM described based on No. 1 can be applied in substantially the same manner even after the process shown in FIG. 11 in the first embodiment.

Next, a third embodiment of the present invention will be described with reference to FIGS. In this embodiment, first, after the steps similar to the steps described with reference to FIGS. 1 to 4 are performed, as shown in FIG.
After forming an oxide insulating film 81 of a predetermined thickness on the entire upper surface, a part of the surface of the oxide insulating film 81 is covered with a resist film 82,
This is anisotropically etched to form a pair of side walls 83, 83 of the second layer on both side walls of the gate electrode portion 76 as shown in FIG. Then, as shown in FIG. 24, a polycrystalline silicon layer 86a doped with impurities is formed on the entire surface of the semiconductor substrate 72, and this is patterned to form a conductive layer 86 as shown in FIG. The surface of the semiconductor substrate at the connecting portion between the conductive layer 86 and the semiconductor substrate 72 is subjected to the same steps as those in the first embodiment, and then the first
An n ⁴⁺ layer having a concentration similar to that of the n ²⁺ layer in the above embodiment is formed.

Thereafter, as shown in FIG. 26, a conductive layer 89 is formed with an insulating film 88 interposed, and then an oxide insulating film 96a having a predetermined thickness is deposited on the entire surface of the semiconductor substrate 72. 27, a side wall spacer 96 of the third layer is formed on the left side wall of the gate electrode portion 76 by performing a selective etching.

Next, in the state shown in FIG. 27, by implanting n-type impurities as shown in FIG. 28, an n ⁵⁺ layer having almost the same impurity concentration as the n ⁴⁺ layer is formed inside the n ⁻ layer. Form to enter.

After that, the interlayer insulating film 91 and the polycrystalline silicon layer 93 are formed through the steps similar to those shown in FIGS. 17 to 19 (FIG. 29).

In this embodiment, the n ⁵⁺ layer is formed by ion implantation using the third sidewall as a mask, but the second embodiment described with reference to FIG. As in the case of
The n ⁵⁺ layer 97 can be formed by so-called auto-doping. Further, in the case of forming the n ⁵⁺ layer 97 by ion implantation, instead of forming the sidewall spacer as a mask in a self-aligned manner, as shown in FIG. 30, the interlayer insulating film 91 is contacted by using the resist film 92 as a mask. After forming the hole 100, the interlayer insulating film 91 and the resist film 92 are used as a mask for n.
It can also be formed by ion-implanting type impurities.

The above-mentioned embodiments are all LOCOS.
Although the semiconductor device to which the present invention is applied when the element isolation region is formed by the method has been described, the same effects can be obtained even when the present invention is applied to a semiconductor device in which the element isolation region is formed by the field shield electrode. It goes without saying that you can do it.

Further, in each of the above-mentioned embodiments, when the sidewall spacers are formed of a plurality of layers, even if the cross section of the completed sidewall spacers is observed, the boundaries of the layers can be identified by the same layer. It is difficult as long as it is formed by CVD of the material. This is because the CVD film is in an amorphous state. However, due to over-etching of the semiconductor substrate surface at the time of forming each layer of the sidewall spacer formed of a plurality of layers, a step is formed on the semiconductor substrate surface at the boundary of each layer. Therefore, by observing the cross section of the completed semiconductor device with an electron microscope, it is possible to judge whether the sidewall is composed of a plurality of layers or not, depending on whether or not there is a step.

Further, in each of the above embodiments, in order to simplify the description, an example in which one MOS field effect transistor is formed in one active region surrounded by the element isolation region 71. Although shown, it goes without saying that the application of the present invention is not limited to such a case. For example, the second embodiment is shown in FIG.
31 corresponding to FIG. 31 or the structure of the third embodiment shown in FIG. 32 corresponding to FIG. 29, two elements are formed in one active region surrounded by the element isolation region 71.
It is similarly applicable to the formation of a structure including one or more MOS field effect transistors and having the gate electrode 74 extending over the element isolation region 71.

[0055]

As described above, according to the semiconductor device of the present invention described in claim 1, each side wall of the gate electrode is
By providing the side wall spacers having a predetermined width in which a predetermined number of insulating films are deposited, the source / drain regions and the high-concentration impurity layer formed on the surface of the semiconductor substrate at the contact portion can be relatively easily and easily formed. The formation position can be controlled appropriately. Therefore, the leakage current to the semiconductor substrate is suppressed and the M having good characteristics is provided.
A field effect transistor having an OS LDD structure can be manufactured with high productivity.

This effect is particularly noticeable as an improvement in refresh characteristics when applied to a DRAM memory cell.

Further, in the semiconductor device according to the second aspect, the distance from the side end of the gate electrode of the contact portion between the conductive layer and the semiconductor substrate surface depends on the width of the second sidewall spacer on the semiconductor substrate surface. Therefore, the position of the contact portion with respect to the gate electrode can be set with high accuracy.

Further, according to the semiconductor device of the third aspect, the conductive layer includes a polycrystalline silicon layer doped with the second conductivity type impurity, and the high-concentration second conductivity type layer is the second conductivity from the conductive layer. By being formed in a self-aligned manner by thermal diffusion of the type impurities, the high-concentration second conductivity type layer can be formed in a self-aligned manner without passing through an ion implantation step.

The structure of the semiconductor device described in claim 1 can be formed relatively easily and with high precision by the method for manufacturing a semiconductor device according to the present invention described in claim 4 or 5. A semiconductor device including a MOS field effect transistor having good characteristics can be manufactured with high productivity.

Further, the semiconductor device of the present invention described in claim 3 can be formed relatively easily and highly accurately by the method of manufacturing a semiconductor device of the present invention described in claim 6.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second step of the method for manufacturing the semiconductor device of the embodiment.

FIG. 3 is a cross-sectional view showing a third step of the method for manufacturing the semiconductor device of the embodiment.

FIG. 4 is a cross-sectional view showing a fourth step of the method for manufacturing the semiconductor device of the embodiment.

FIG. 5 is a cross-sectional view showing a fifth step of the method for manufacturing the semiconductor device of the embodiment.

FIG. 6 is a sectional view showing a sixth step of the method for manufacturing the semiconductor device of the embodiment.

FIG. 7 is a cross-sectional view showing a seventh step of the method for manufacturing the semiconductor device of the example.

FIG. 8 is a cross-sectional view showing an eighth step of the method for manufacturing the semiconductor device of the embodiment.

FIG. 9 is a sectional view showing a ninth step of the method for manufacturing the semiconductor device of the example.

FIG. 10 is a tenth method of manufacturing the semiconductor device according to the embodiment.
It is sectional drawing which shows a process.

FIG. 11 is an eleventh method of manufacturing the semiconductor device of the embodiment.
It is sectional drawing which shows a process.

FIG. 12 is a cross-sectional view showing a modification of the process for forming the n ²⁺ layer 87 in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 13 is a sectional view showing a first step of a method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a sectional view showing a second step of the method for manufacturing the semiconductor device of the example.

FIG. 15 is a sectional view showing a third step of the method for manufacturing the semiconductor device of the example.

FIG. 16 is a cross-sectional view showing a fourth step of the method for manufacturing the semiconductor device of the example.

FIG. 17 is a cross-sectional view showing a fifth step of the method for manufacturing the semiconductor device of the example.

FIG. 18 is a cross-sectional view showing a sixth step of the method for manufacturing the semiconductor device of the example.

FIG. 19 is a cross-sectional view showing a seventh step of the method for manufacturing the semiconductor device of the example.

FIG. 20 is a sectional view showing an eighth step of the method for manufacturing the semiconductor device of the example.

FIG. 21 is a cross-sectional view showing a modified example of the process for forming the n ³⁺ layer in the method for manufacturing a semiconductor device according to the second embodiment of the present invention.

FIG. 22 is a sectional view showing a first step of a method for manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 23 is a cross-sectional view showing a second step of the method for manufacturing the semiconductor device of the example.

FIG. 24 is a cross-sectional view showing the third step of the method for manufacturing the semiconductor device of the example.

FIG. 25 is a cross-sectional view showing a fourth step of the method for manufacturing the semiconductor device of the example.

FIG. 26 is a sectional view showing a fifth step of the method for manufacturing the semiconductor device of the example.

FIG. 27 is a cross-sectional view showing a sixth step of the method for manufacturing the semiconductor device of the example.

FIG. 28 is a cross-sectional view showing the seventh step of the method for manufacturing the semiconductor device of the example.

FIG. 29 is a cross-sectional view showing the eighth step of the method for manufacturing the semiconductor device of the example.

FIG. 30 is a cross-sectional view showing a modified example of the process for forming n ⁵⁺ layer 97 in the method of manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 31 is a sectional view, corresponding to FIG. 19, of an example of an actual device structure that can be formed by applying the same manufacturing process as that of the second embodiment.

32 is a cross-sectional view corresponding to FIG. 29, of an example of an actual device structure that can be formed by applying the same manufacturing process as that of the third embodiment.

FIG. 33 is a cross-sectional view showing a first step of a conventional typical method for forming a field effect transistor having an LDD structure.

FIG. 34 is a sectional view showing a second step of the conventional example.

FIG. 35 is a sectional view showing a third step of the conventional example.

FIG. 36 is a sectional view showing a fourth step of the conventional example.

FIG. 37 is a cross-sectional view showing a fifth step of the conventional example.

FIG. 38 is a sectional view showing a sixth step of the conventional example.

39. In order to improve the above conventional method for manufacturing a field effect transistor, the present inventor has disclosed in Japanese Patent Laid-Open No. 4-218925.
FIG. 7 is a cross-sectional view showing a first step of a conventional method for manufacturing a field effect transistor proposed in Japanese Patent Publication No.

FIG. 40 is a sectional view showing a second step of the conventional example.

FIG. 41 is a sectional view showing a third step of the conventional example.

FIG. 42 is a sectional view showing a fourth step of the conventional example.

FIG. 43 is a sectional view showing a fifth step of the conventional example.

FIG. 44 is a sectional view showing a sixth step of the conventional example.

FIG. 45 is a sectional view showing a seventh step of the conventional example.

FIG. 46 is a cross-sectional view showing an eighth step of the conventional example.

[Explanation of symbols]

71 element isolation insulating film, 72 semiconductor substrate, 73 gate insulating film, 74 gate electrode, 76 gate electrode part, 7
7 low-concentration n-type diffusion layer (n ⁻ layer), 78 first-layer sidewall spacer, 83 second-layer sidewall spacer, 85 high-concentration n-type diffusion layer (n ⁺ layer), 86a polycrystalline silicon layer , 86 conductive layer, 87 high-concentration n-type impurity layer (n ²⁺ layer), 93 polycrystalline silicon layer, 94 n
³⁺ layer, 96 Third side wall spacer, 97
n ⁵⁺ layers. In addition, in the drawings, the parts to which the same numbers are attached indicate the same or corresponding elements.

Claims (6)

[Claims] 1. A semiconductor device having a field effect transistor, wherein the field effect transistor has a semiconductor substrate having a region of a first conductivity type at least near a surface, and a gate insulating film interposed on the semiconductor substrate. The formed gate electrode, a first sidewall spacer formed on one side wall surface of the gate electrode and having a predetermined number of layers and having a predetermined width, and the other side of the gate electrode. A second sidewall spacer which is formed on the wall surface and has a different number of layers from that of the first sidewall spacer and has a width different from that of the first sidewall spacer; A pair of source / drain regions of the second conductivity type that are formed on the surface from the vicinity immediately below both side walls of the gate electrode to the outside; A second high-concentration second-conductivity-type layer formed on the surface of the semiconductor substrate with one end of the sidewall spacer immediately below the side end of the semiconductor substrate surface position as one end; A semiconductor device having a second conductivity type impurity concentration higher than that of the source / drain regions and formed inside a region of the pair of source / drain regions on the side of the second sidewall spacer. 2. The semiconductor device according to claim 1, further comprising a conductive layer formed so as to cover the surface of the second sidewall spacer and contact the high-concentration second conductivity type layer. 3. The conductive layer includes polycrystalline silicon doped with a second conductivity type impurity, and the high-concentration second conductivity type layer is self-aligned by thermal diffusion of the second conductivity type impurity from the conductive layer. The semiconductor device according to claim 2, wherein the semiconductor device is formed on. 4. A method of manufacturing a semiconductor device including a field effect transistor, comprising: forming a gate electrode on at least a main surface of a semiconductor substrate having a first conductivity type region near the main surface with a gate insulating film interposed. A step of forming the first side wall spacer on one side wall of the gate electrode, and a second side wall spacer having a width different from that of the first side wall spacer on the other side wall of the gate electrode. Forming a pair of source / drain regions by injecting an impurity of a second conductivity type into the surface of the semiconductor substrate using at least the gate electrode as a mask; and the gate electrode and the second sidewall. Using the spacer as a mask, introducing the second conductivity type impurity only on the side of the second sidewall spacer on the surface of the semiconductor substrate. , One end of the second sidewall spacer immediately below the side end portion of the semiconductor substrate surface position, and inside the region of the pair of source / drain regions on the second sidewall spacer side. And a step of forming the high-concentration second conductivity type layer, the step of forming the first and second sidewall spacers is performed by depositing an oxide insulating film and performing anisotropic etching a plurality of times. The step of performing the anisotropic etching a plurality of times is performed at least once with the mask covering a region on either side of both side walls of the gate electrode. A method of manufacturing a semiconductor device, wherein the widths of the first and second sidewall spacers are different from each other. 5. A method of manufacturing a semiconductor device including a field effect transistor, comprising: forming a gate electrode on at least a main surface of a semiconductor substrate having a first conductivity type region near the main surface with a gate insulating film interposed. And a step of forming an oxide insulating film on the semiconductor substrate so as to cover the upper surface and both side wall surfaces of the gate electrode, and anisotropically etching the oxide insulating film to form a pair of side wall surfaces of the gate electrode. Forming a sidewall spacer of a first layer; depositing an oxide insulating film on the semiconductor substrate so as to cover the upper surface of the gate electrode and the sidewall spacer of the first layer; Anisotropic etching is performed only on one side wall side, and on the side wall spacer of the first layer on the one side wall side of the gate electrode,
A step of forming a second-layer sidewall spacer, and using the gate electrode alone or the gate electrode and the first-layer sidewall spacer as a mask,
Implanting a second conductivity type impurity into the semiconductor substrate to form a pair of source / drain regions; and forming the gate electrode, the first-layer sidewall spacer and the second-layer sidewall spacer. As a mask, a second conductivity type impurity is introduced into the surface of the semiconductor substrate only on the one side wall side of the gate electrode, and inside the region on the one side wall side of the pair of source / drain regions, And a step of forming a high-concentration second conductivity type layer having a concentration higher than that of the source / drain regions. 6. A step of forming a polycrystalline silicon layer doped with a second conductivity type impurity on the semiconductor substrate after the step of forming the pair of source / drain regions, and patterning the polycrystalline silicon layer. And forming a conductive layer in contact with the surface of the sidewall spacer of the second layer and a region where the high-concentration second conductivity type layer is to be formed. The forming step is performed by thermal diffusion of the second conductivity type impurity from the polycrystalline silicon layer or the conductive layer to the surface of the semiconductor substrate by performing heat treatment after the step of forming the polycrystalline silicon layer, A method of manufacturing a semiconductor device according to claim 5.