JP2009158821A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can be manufactured through simple processes and has superior high breakdown voltage characteristics. <P>SOLUTION: The semiconductor device comprises: an N-type first drain drift region 4 formed on a P-type semiconductor substrate 1; an N-type second drain drift region 5 formed having a bottom surface deeper than the first drain drift region 4 and connecting with the region 4, and also having higher density than the region 4; an N-type drain region 7 formed in contact with the second drain drift region 5 and also having higher density than the region 5, an N-type source region formed on the semiconductor substrate 1 apart from the first drain drift region 5; a gate insulating film 2 formed as an upper layer of the semiconductor substrate 1; and a gate electrode 3 formed as an upper layer of the gate insulating film 2 from above an end of the source region 6 on the side of the drain region 4 to above an end of the first drain drift region 4 on the side of the source region 6. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  High breakdown voltage semiconductor devices are used for power supply ICs, display device drive ICs, and the like, and have many uses. Under such circumstances, there is a demand for a semiconductor device that can realize a high breakdown voltage at a lower cost. As a method for this, a method has been used in which a low concentration drift region is added to a high concentration source / drain region to relax the electric field (see, for example, Patent Document 1 below).

  FIG. 8 is a schematic cross-sectional structure diagram of a semiconductor device disclosed in Patent Document 1 below. A semiconductor device 100 shown in FIG. 8 includes a gate electrode 3 formed on one main surface of a P-type semiconductor substrate 1 via a gate insulating film 2. A high-concentration N-type source region 6 is provided on the main surface of the semiconductor substrate 1 including immediately below one end of the gate electrode 3.

  Further, a low concentration N-type first drain drift region 4 is provided on the main surface of the semiconductor substrate 1 including directly under the other end of the gate electrode 3, and at a position outside the region immediately below the gate electrode 3. The second drain drift region 5 is in contact with the first drain drift region 4 and is formed in an N type having a higher concentration than the first drain drift region 4. A drain region 7 is formed on the main surface of the semiconductor substrate 1 in the second drain drift region 5 and is formed in an N-type having a higher concentration than the second drain drift region 5.

  A first insulating film 9 is formed on the entire surface including the upper layer of the gate electrode 3, and the wiring layer 8 is formed so as to penetrate the first insulating film 8 and come into contact with the source region 6 and the drain region 7. Has been.

  According to the semiconductor device 100 shown in FIG. 8, the horizontal electric field along the main surface of the semiconductor substrate 1 is relaxed in two stages by the two drain drift regions 4 and 5 having different concentrations. A semiconductor device with a higher breakdown voltage can be realized as compared with a case where no region is provided and a case where a single drain drift region is provided.

Japanese Patent Laid-Open No. 61-180483

  In the case of the method described in Patent Document 1, although it is possible to achieve a certain high breakdown voltage, it has been desired to realize a semiconductor device having a higher breakdown voltage.

  An object of this invention is to provide the semiconductor device which was further excellent in the high pressure | voltage resistance than before.

  In order to achieve the above object, a semiconductor device according to the present invention includes a first drain drift region of a second conductivity type different from the first conductivity type formed on a semiconductor substrate of a first conductivity type, and the first A second drain drift region of the second conductivity type having a higher concentration than the first drain drift region and having a deeper bottom position than the drain drift region and continuous with the first drain drift region. A drain region of the second conductivity type having a higher concentration than the second drain drift region formed in contact with the second drain drift region, and spaced apart from the first drain drift region on the semiconductor substrate. A source region of the second conductivity type formed on the semiconductor substrate, a gate insulating film formed on an upper layer of the semiconductor substrate, and an end of the source region on the first drain drift region side From above, toward the end above the source region side of the first drain drift region, the first, comprising a gate electrode formed on the upper layer of the gate insulating film.

According to another aspect of the present invention, there is provided a semiconductor device having a second conductivity type first drain drift region different from the first conductivity type formed on a first conductivity type semiconductor substrate, and the first drain drift region. A second drain drift region of the second conductivity type with a higher concentration than the first drain drift region, formed so as to have a deep bottom surface and continuous with the first drain drift region; The second conductivity type drain region having a higher concentration than the second drain drift region formed in contact with the drain drift region, and the semiconductor substrate formed on the semiconductor substrate spaced apart from the first drain drift region A source drift region of a second conductivity type;
The source region of the second conductivity type having a higher concentration than the source drift region formed in contact with the source drift region, a gate insulating film formed in an upper layer of the semiconductor substrate, and the drain of the source drift region And a gate electrode formed in an upper layer of the gate insulating film from above the end on the region side to above the end on the source drift region side of the first drain drift region. .

  According to the first or second characteristic configuration of the semiconductor device according to the present invention, the first and second drain drift regions having different concentrations are formed in a direction parallel to the semiconductor substrate surface. Is relaxed in two stages by both drain drift regions. Since the high-concentration second drain drift region is formed deeper than the first drain drift region, the effect of relaxing the electric field in the direction perpendicular to the substrate surface can be enhanced.

  That is, according to the semiconductor device of the present invention, the effect of relaxing the electric field can be exhibited in both the direction parallel to the substrate surface and the direction perpendicular to the substrate surface. For this reason, it is possible to realize a semiconductor device having a higher breakdown voltage than the conventional configuration.

  In addition to the second characteristic configuration, the semiconductor device according to the present invention has a conductive material doped with the second conductivity type, wherein the source region is formed in contact with the upper layer of the source drift region. The third characteristic is that it is a film.

  In the semiconductor device according to the present invention, in addition to any one of the first to third features, the second drain drift region is formed at a position outside the region directly below the gate electrode. The fourth feature.

  According to the fourth characteristic configuration of the semiconductor device according to the present invention, the second drain drift region formed deeper than the first drain drift region is formed apart from the region immediately below the gate electrode, thereby causing a punch-through phenomenon. A semiconductor device with high withstand voltage can be realized while suppressing the above.

  According to the semiconductor device of the present invention, in addition to any one of the first to fourth characteristic configurations, the drain region is an impurity diffusion region formed in the second drain drift region. The fifth feature.

  Further, in the semiconductor device according to the present invention, in addition to any one of the first to fourth characteristic configurations, the second drain region is formed in contact with the upper layer of the second drain drift region. A sixth feature is that the conductive material film is doped in a conductive type.

  According to the sixth characteristic configuration of the semiconductor device according to the present invention, the drain region can be formed of the conductive material film on the upper layer of the semiconductor substrate. For this reason, it is not necessary to secure a region for forming the drain region in the second drain drift region. Therefore, since the area of the second drain drift region can be reduced, a high breakdown voltage semiconductor device can be realized with a small device size.

  A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having the first characteristic configuration, wherein the second conductivity type impurity ions are implanted into a predetermined region of the semiconductor substrate and the semiconductor device is manufactured. A first step of forming a first drain drift region; and after completion of the first step, the second conductivity type impurity ions are implanted into the predetermined region of the semiconductor substrate at a higher concentration and higher energy than in the first step. A second step of forming the second drain drift region which is continuous with the first drain drift region and has a deeper bottom surface than the first drain drift region; and after the second step, Injecting impurity ions of the second conductivity type having a concentration higher than that in the second step into a predetermined region in the second drain drift region and a predetermined region separated from the first drain drift region, The third step of forming the drain region and the source region, the fourth step of forming the gate insulating film on the semiconductor substrate after the completion of the third step, and the source region after the completion of the fourth step And a fifth step of forming the gate electrode in the upper layer of the gate insulating film from above the drain side end of the first drain drift region to above the source region side end of the first drain drift region. And

  According to the first feature of the method of manufacturing a semiconductor device according to the present invention, it has a high electric field relaxation effect not only in a direction parallel to the substrate surface of the semiconductor substrate but also in a direction perpendicular to the substrate surface. It is possible to manufacture an excellent semiconductor device.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having the third characteristic configuration described above, wherein impurity ions of the second conductivity type are implanted into a predetermined region of the semiconductor substrate. A first step of forming a first diffusion region spaced apart from the first drain drift region and the first drain drift region; and a step of forming the gate insulating film on the semiconductor substrate after completion of the first step. After the two steps and the second step, the gate insulation extends from above the end of the first drain drift region on the first diffusion region side to above the end of the first diffusion region on the first drain drift region side. A third step of forming the gate electrode on the upper layer of the film; and after completion of the third step, using the gate electrode as a mask, the impurity of the second conductivity type is higher in concentration and energy than in the first step. Ions are implanted, and the second drain drift region which is continuous with the first drain drift region and has a deeper bottom surface than the first drain drift region, and the second diffusion region which is continuous with the first diffusion region. A fourth step of forming a diffusion region; and after the completion of the fourth step, a first insulating film is formed on the entire surface, a partial upper surface of the second drain drift region, and the first and second diffusion regions A fifth step of exposing the upper part of the source drift region formed in step S5 to be exposed, and the second conductivity type at a higher concentration than the impurity ions implanted in the fourth step after completion of the fifth step. After forming a conductive material film doped on the entire surface, a patterning process is performed so that the drain region is formed by the conductive material film in contact with the second drain drift region. The source region by the conductive material film in contact with the lift region, the second, comprising a sixth step of respectively forming, a.

  According to the second feature of the method for manufacturing a semiconductor device according to the present invention, it has a high electric field relaxation effect not only in a direction parallel to the substrate surface of the semiconductor substrate but also in a direction perpendicular to the substrate surface. It is possible to manufacture an excellent semiconductor device. In particular, according to this feature, since the drain region can be composed of a conductive material film on a semiconductor substrate, the area of the second drain drift region can be reduced, and a high breakdown voltage semiconductor device can be reduced in scale. It can be realized with the device size.

  According to the configuration of the present invention, it is possible to realize a semiconductor device that can be manufactured by a simple process and has excellent high voltage resistance.

  Embodiments of a semiconductor device according to the present invention (hereinafter referred to as “the present invention device” as appropriate) and a manufacturing method thereof (hereinafter referred to as “the present invention method” as appropriate) will be described below with reference to the drawings. .

[First Embodiment]
A first embodiment of the device and method of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIGS.

  FIG. 1 is a schematic sectional view of the apparatus of the present invention. The following sectional structural views are schematically shown, and the dimensional ratio on the drawing does not necessarily match the actual dimensional ratio. The same applies to the following embodiments. In the drawing, the same components as those in FIG. 8 are denoted by the same reference numerals, and the description thereof will be simplified.

  A device 10 of the present invention shown in FIG. 1 is similar to the conventional semiconductor device 100 shown in FIG. 8 in that a P-type semiconductor substrate 1, a gate insulating film 2, a gate electrode 3, a first drain drift region 4, and a second drain drift. A region 5, a source region 6, a drain region 7, a wiring layer 8, and a first insulating film 9 are provided. The device 10 of the present invention is formed so that the bottom surface of the second drain drift region 5 is located deeper than the bottom surface of the first drain drift region 4 as compared with the conventional semiconductor device 100. Different.

  That is, as shown in FIG. 1, the device 10 of the present invention includes an N-type first drain drift region 4 and an N-type high-concentration source region formed separately on the P-type semiconductor substrate 1. The second drain drift region 5 having a higher concentration N than the first drain drift region 4 is formed to be continuous with the first drain drift region 4 outside the gate electrode 3. As described above, the depth position of the bottom surface of the second drain drift region 5 is formed to be deeper than the bottom surface of the first drain drift region 4. In other words, the formation depth d2 of the second drain drift region 5 is larger than the formation depth d1 of the first drain drift region 4. As in the conventional semiconductor device 100, a higher concentration N-type drain region 7 than the drain drift region 5 is formed in the second drain drift region 5.

  With this configuration, two drain drift regions having different concentrations are formed in a direction parallel to the substrate surface of the semiconductor substrate 1 as in the conventional semiconductor device 100 shown in FIG. Has the effect of being relaxed in two stages by both drain drift regions 4 and 5.

  Further, unlike the conventional semiconductor device 100, the second drain drift region 5 is formed deeper than the first drain drift region 4, so that the electric field in the direction perpendicular to the substrate surface is relaxed compared to the conventional semiconductor device 100. The effect can be enhanced.

  In general, when the depth of the drift region is increased, the drift region is also formed at a depth position away from the gate electrode. Therefore, there is a problem that punch-through is likely to occur when the depletion layer expands at such a location.

  However, as in the device 10 of the present invention, the first drain drift region 4 located immediately below the gate electrode 3 is formed shallow as in the prior art, and the second drain formed outside the region directly below the gate electrode 3. By forming only the drift region 5 deeply, it is possible to enhance the electric field relaxation effect in the direction perpendicular to the substrate surface while suppressing the punch through. In particular, by deeply forming the second drain drift region 5 having a higher concentration than the first drain drift region 4, the electric field relaxation effect in the direction perpendicular to the substrate surface can be further enhanced.

  Hereinafter, the manufacturing process when manufacturing the inventive device 10 according to the present embodiment will be described. FIG. 2 schematically shows a schematic cross-sectional structure diagram in each process when the apparatus 10 of the present invention is manufactured using the method of the present invention, and is divided into FIGS. 2A to 2E for each process. Are shown. FIG. 3 is a flowchart of the manufacturing process of the method of the present invention according to the present embodiment, and steps # 1 to # 7 in the following sentence represent steps of the flowchart shown in FIG. To do.

First, as shown in FIG. 2A, N-type impurity ions are implanted with a resist 21 formed in a predetermined region on the P-type semiconductor substrate 1 to form a first drain drift region 4 (step # 1). ). At this time, as ion implantation conditions according to Step # 1, for example, phosphorus ions are implanted at an implantation energy of about 40 to 100 keV and a dose amount of about 3 × 10 ^{12 to} 7 × 10 ¹² / cm ² . As a result, the first drain drift region 4 is formed from the substrate surface to the depth d1.

  Next, as shown in FIG. 2B, after removing the resist 21, N-type impurity ions are implanted with the resist 22 formed so as to mask at least a part of the first drain drift region 4. Thus, the second drain drift region 5 is formed (step # 2). At this time, a part of the first drain drift region 4 is exposed without being masked, and impurity ions according to step # 2 are also implanted into the region.

As ion implantation conditions for step # 2, for example, phosphorus ions are implanted at an implantation energy of about 80 to 200 keV and a dose of about 7 × 10 ¹² to 2 × 10 ¹³ / cm ² . In step # 2, ion implantation is performed under conditions of higher energy and higher dose than in step # 1. Thereby, the second drain drift region 5 having a higher concentration of N than the first drain drift region 4 is formed from the substrate surface to d2 deeper than the formation depth d1 of the first drain drift region 4. The second drain drift region 5 is formed in contact with a part of the first drain drift region 4.

  Next, as shown in FIG. 2C, after removing the resist 22, a pattern in which a part of the second drain drift region 5 and a predetermined region separated from the first drain drift region 4 are exposed. N-type impurity ions are implanted with the resist 23 formed, thereby forming the drain region 7 and the source region 6 (step # 3).

As ion implantation conditions for step # 3, for example, arsenic ions are implanted with an implantation energy of about 20 to 50 keV and a dose of about 2 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² . In step # 3, ion implantation is performed under a higher dose condition than in step # 2. As a result, a high concentration N-type drain region 7 is formed in the second drain drift region 5. Further, a high concentration N-type source region 6 is formed at a position separated from the first drain drift region 4.

  Next, as shown in FIG. 2D, after removing the resist 23, the gate insulating film 2 is formed on the upper surface of the substrate 1, and the gate electrode 3 is formed thereon (step # 4). Specifically, after the gate insulating film 2 is formed, a conductive material film made of, for example, a polysilicon film is formed on the entire surface, and then the conductive material film is formed on the drain region 7 side of the source region 6. The gate electrode 3 is formed by patterning so as to remain from above the end portion to above the end portion on the source region 6 side of the first drain drift region 4.

  Next, after the first insulating film 9 is formed on the upper surface of the semiconductor substrate 1 including the upper layer of the gate electrode 3 (step # 5), the source region 6 and the drain region 7 are opened so that the upper surfaces are partially exposed. (Step # 6). Then, after a conductive material film such as Al is formed on the first insulating film 9, the wiring layer is patterned and connected to the source region 6 and the drain region 7 as shown in FIG. 8 is formed (step # 7).

  Through such steps # 1 to # 7, a semiconductor device having a high electric field relaxation effect not only in the direction parallel to the substrate surface of the semiconductor substrate 1 but also in the direction perpendicular thereto can be realized. Specifically, with respect to the direction parallel to the substrate surface, electric field relaxation can be realized in two stages of the first drain drift region 4 and the second drain drift region 5, while on the other hand, with respect to the direction perpendicular to the substrate surface. The electric field can be relaxed in the region of the depth d2 of the second drain drift region 5. As a result, it is possible to realize a semiconductor device having a higher breakdown voltage than the conventional one. In addition, since the electric field concentration in the channel can be reduced by the configuration of the device of the present invention, it is possible to manufacture a semiconductor device having a shorter gate length than the conventional one.

  In the above-described embodiment, the drift region is formed only on the drain region 7 side and not on the source region 6 side. However, in steps # 1 and # 2, impurity ions are also formed on the source region 6 side. The source drift region 11 may be formed by performing the implantation (see FIG. 4). In this case, the gate electrode 3 is formed from the upper end of the source drift region 11 on the drain region 7 side to the upper end of the first drain drift region 4 on the source region 6 side. 4 can also have the effect of increasing the breakdown voltage, as in FIG. In addition, since the drift region 11 is also provided on the source region 6 side, it is possible to reduce the electric field concentration on the source region 6 side immediately below the gate electrode 3.

[Second Embodiment]
A first embodiment of the device and method of the present invention (hereinafter referred to as “this embodiment” as appropriate) will be described with reference to FIGS.

  FIG. 5 is a schematic sectional view of the apparatus of the present invention. In addition, about the component same as 1st Embodiment, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

  The inventive device 10 a shown in FIG. 5 includes an N-type first drain drift region 4 and a second drain drift region 5 on a P-type semiconductor substrate 1. And the drain region 7 comprised with the conductive material film | membrane doped to high concentration N type so that the 2nd drain drift region 5 may be contacted is provided. As in the first embodiment, the second drain drift region 5 is formed at a higher concentration than the first drain drift region 4 and deeper in the depth direction.

  Further, an N-type source drift region 11 is formed apart from the first drain drift region 4, and a conductive material film doped to a high concentration N-type so as to be in contact with the source drift region 11. A configured source region 6 is provided.

  Then, a gate insulating film 2 is formed on the semiconductor substrate 1, and further on the upper layer, from the upper end of the source drift region 11 on the drain region 7 side, to the end of the source drift region 11 of the first drain drift region 4. A gate electrode 3 is formed over the portion.

  A first insulating film 9 is formed on the upper layer of the gate insulating film 2 outside the gate electrode 3 formation. Then, the conductive material film is formed so as to penetrate the first insulating film 9 over a part of the second drain drift region 5 and a part of the source drift region 11, so that the second drain drift is formed. A drain region 7 connected to the region 5 and a source region 6 connected to the source drift region 11 are formed.

  In the case of such a configuration, as in the first embodiment, two drain drift regions having different concentrations are formed in a direction parallel to the substrate surface of the semiconductor substrate 1, so that the electric field in this direction is generated by both drain drift regions 4 and 5. Has the effect of being relaxed in two stages. The first drain drift region 4 located immediately below the gate electrode 3 is formed shallow as in the prior art, and only the second drain drift region 5 formed outside the region directly below the gate electrode 3 is formed deep. Thus, it is possible to enhance the electric field relaxation effect in the direction perpendicular to the substrate surface while suppressing punch-through. In particular, by deeply forming the second drain drift region 5 having a higher concentration than the first drain drift region 4, the electric field relaxation effect in the direction perpendicular to the substrate surface can be further enhanced.

  In the case of the configuration of FIG. 5, the drain region 7 can be realized by a conductive material film formed on the upper layer of the semiconductor substrate 1. That is, since the area of the second drain drift region 5 can be reduced as compared with the first embodiment in which the drain region 7 is formed in the second drain drift region 5, a high breakdown voltage semiconductor device can be reduced. This can be realized with a device size of a scale.

  Hereinafter, the manufacturing process when manufacturing the inventive device 10a according to the present embodiment will be described. FIG. 6 schematically shows a schematic cross-sectional structure diagram in each process when the apparatus 10a of the present invention is manufactured using the method of the present invention, and is divided into FIGS. 6 (a) to 6 (g) for each process. Are shown. FIG. 7 is a flowchart of the manufacturing process of the method of the present invention according to the present embodiment, and steps # 11 to # 22 in the following sentence represent steps of the flowchart shown in FIG. To do.

First, as shown in FIG. 6A, N-type impurity ions are implanted in a state where a resist 31 is formed in a predetermined region on the P-type semiconductor substrate 1 to form the first drain drift region 4 and the first diffusion region 11a. Form (step # 11). At this time, as ion implantation conditions according to Step # 11, for example, phosphorus ions are implanted with an implantation energy of about 40 to 100 keV and a dose of about 3 × 10 ^{12 to} 7 × 10 ¹² / cm ² . As a result, the first drain drift region 4 is formed from the substrate surface to the depth d1.

  In step # 11, the first diffusion region 11 a is also formed on the semiconductor substrate 1 so as to be separated from the first drain drift region 4. That is, the first drain drift region 4 and the first diffusion are performed by performing the ion implantation according to step # 11 in a state where the resist 31 patterned so as to expose a plurality of spaced apart regions on the semiconductor substrate 1 is formed. Region 11a is formed.

  Next, as shown in FIG. 6B, the surface of the semiconductor substrate 1 is thermally oxidized to form a gate insulating film 2 with a thickness of about 20 to 60 nm (step # 12).

  Next, as shown in FIG. 6C, the gate electrode 3 is formed on the upper layer of the gate insulating film 2 (step # 13). Specifically, for example, after a conductive material film made of, for example, a polysilicon film is formed on the entire surface, the conductive material film is applied from above the end of the first drain drift region 4 on the first diffusion region 11a side. The gate electrode 3 is formed by patterning so as to remain over the end of the first diffusion region 11a on the first drain drift region 4 side.

  Next, as shown in FIG. 6D, N-type impurity ions are implanted using the gate electrode 3 as a mask to form the second drain drift region 5 and the second diffusion region 11b (step # 14).

As ion implantation conditions for step # 14, for example, phosphorus ions are implanted with an implantation energy of about 80 to 200 keV and a dose of about 7 × 10 ¹² to 2 × 10 ¹³ / cm ² . In step # 14, ion implantation is performed under conditions of higher energy and higher dose than in step # 11 and with energy lower than that required for penetrating the gate electrode 3. Thereby, the second drain drift region 5 having a higher concentration of N than the first drain drift region 4 is formed from the substrate surface to d2 deeper than the formation depth d1 of the first drain drift region 4. The second drain drift region 5 is formed in contact with a part of the first drain drift region 4. Further, in a region separated from the first drain drift region 4, the second diffusion region 11b is formed in contact with a part of the first diffusion region 11a. The source drift region 11 in FIG. 5 is formed by the first diffusion region 11a and the second diffusion region 11b.

  Next, as shown in FIG. 6E, after the first insulating film 9 is formed on the upper surface of the semiconductor substrate 1 including the upper layer of the gate electrode 3 (step # 15), the source drift region 11 and the second drain are formed. Opening is performed so that a part of the upper surface of the drift region 5 is exposed (step # 16).

  Next, a conductive material film such as polysilicon is formed on the entire surface (step # 17). Thereby, the conductive material film is formed so as to be in contact with the second drain drift region 5 and the source drift region 11. Thereafter, as shown in FIG. 6F, after patterning the conductive material film and the first insulating film 9 (step # 18), a high-concentration N type impurity is implanted into the conductive material film (step # 18). # 19). In step # 19, impurity ions can be implanted using a resist used for patterning as a mask.

As the ion implantation conditions in Step # 18, for example, arsenic ions are implanted at an implantation energy of about 20 to 50 keV and a dose of about 2 × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² . In step # 19, ion implantation is performed under conditions of a higher dose than in step # 14. As a result, the drain region 7 is constituted by a conductive material film that is doped at a higher concentration than the region 5 in contact with the second drain drift region 5, and at a higher concentration than the region 11 in contact with the source drift region 11. The source region 6 is constituted by the doped conductive material film.

  Thereafter, as shown in FIG. 6G, after the second insulating film 13 is formed on the upper surface of the semiconductor substrate 1 including the upper layer of the gate electrode 3 (step # 20), the source drift region 11 and the second drain drift are formed. Opening is performed so that a part of the upper surface of the region 5 is exposed (step # 21). Then, a conductive material film such as Al is formed on the upper surface of the second insulating film 13 and patterned to form the wiring layer 8 connected to the source region 6 and the drain region 7 (step # 22). ).

  Through such steps # 11 to # 22, as in the first embodiment, a semiconductor device having a high electric field relaxation effect not only in a direction parallel to the substrate surface of the semiconductor substrate 1 but also in a direction perpendicular thereto. Can be realized. Specifically, with respect to the direction parallel to the substrate surface, electric field relaxation can be realized in two stages of the first drain drift region 4 and the second drain drift region 5, while on the other hand, with respect to the direction perpendicular to the substrate surface. The electric field can be relaxed in the region of the depth d2 of the second drain drift region 5. As a result, it is possible to realize a semiconductor device having a higher breakdown voltage than the conventional one. In addition, since the electric field concentration in the channel can be reduced by the configuration of the device of the present invention, it is possible to manufacture a semiconductor device having a shorter gate length than the conventional one.

  In the present embodiment, unlike the first embodiment, the high-concentration drain region 7 and the source region 6 can be constituted by the conductive material film on the upper layer of the semiconductor substrate 1. Therefore, it is possible to realize a high breakdown voltage semiconductor device with a small device size.

  Furthermore, in the ion implantation process according to step # 14, ion implantation can be performed using the already formed gate electrode 3 as a mask. That is, the formation width of the second drain drift region 5 is determined in a self-aligning manner. Thereby, it is possible to form the second drain drift region 5 at a predetermined position without considering the resist alignment accuracy.

  In the above-described embodiment, the conductive material film is formed and patterned in Steps # 17 and # 18, and then the impurity ion implantation is performed on the conductive material film in Step # 19. In step # 17, a conductive material film doped with N-type high concentration ions in advance may be formed. In such a case, the ion implantation step in step # 19 is not necessary.

[Another embodiment]
Another embodiment will be described below.

  <1> In each of the embodiments described above, the drain drift region has the two regions 4 and 5 having different concentrations and depths. However, the number of the drain drift regions is not limited to two. It may have three or more drain drift regions having different depths.

  <2> In each of the above embodiments, the drain region or the drain drift region is formed on the P-type semiconductor substrate 1, but the P-type well formed by implanting P-type impurity ions on the semiconductor substrate. The drain region or the drain drift region may be formed in the region. That is, the “P-type semiconductor substrate 1” in this specification is a description that naturally includes a well region doped in the P-type on the semiconductor substrate.

  <3> In each of the above embodiments, the case where an N-channel MOS transistor is configured on the P-type semiconductor substrate 1 has been described. However, by inverting each polarity, the P-channel MOS transistor is The configuration can be realized similarly.

Schematic cross-sectional structure diagram of a first embodiment of a semiconductor device according to the present invention Schematic cross-sectional view in each step when manufacturing the semiconductor device according to the present invention of the first embodiment The flowchart which shows the manufacturing process at the time of manufacturing the semiconductor device based on this invention of 1st Embodiment in process order. Another schematic sectional view of the first embodiment of the semiconductor device according to the present invention Schematic cross-sectional structure diagram of a second embodiment of a semiconductor device according to the present invention Schematic cross-sectional view in each step when manufacturing a semiconductor device according to the second embodiment of the present invention The flowchart which shows the manufacturing process at the time of manufacturing the semiconductor device which concerns on this invention of 2nd Embodiment in process order. Schematic cross-sectional structure diagram of a conventional semiconductor device

Explanation of symbols

1: Semiconductor substrate 2: Gate insulating film 3: Gate electrode 4: First drain drift region 5: Second drain drift region 6: Source region 7: Drain region 8: Wiring layer 9: First insulating film 10, 10a: Book Semiconductor device according to invention 11: Source drift region 11a: First diffusion region 11b: Second diffusion region 13: Second insulating film 21, 22, 23, 31: Resist 100: Semiconductor device of conventional configuration

Claims (8)

A first drain drift region of a second conductivity type different from the first conductivity type formed on the semiconductor substrate of the first conductivity type;
The second conductivity type second layer having a deeper bottom surface than the first drain drift region and being continuous with the first drain drift region and having a higher concentration than the first drain drift region. A drain drift region; and
A drain region of the second conductivity type formed in contact with the second drain drift region and having a higher concentration than the second drain drift region;
A source region of the second conductivity type formed on the semiconductor substrate spaced apart from the first drain drift region;
A gate insulating film formed on an upper layer of the semiconductor substrate;
A gate electrode formed in an upper layer of the gate insulating film from above the end of the source region on the first drain drift region side to above the end of the first drain drift region on the source region side. A semiconductor device. A first drain drift region of a second conductivity type different from the first conductivity type formed on the semiconductor substrate of the first conductivity type;
The second conductivity type second layer having a deeper bottom surface than the first drain drift region and being continuous with the first drain drift region and having a higher concentration than the first drain drift region. A drain drift region; and
A drain region of the second conductivity type formed in contact with the second drain drift region and having a higher concentration than the second drain drift region;
A source drift region of the second conductivity type formed on the semiconductor substrate apart from the first drain drift region;
A source region of the second conductivity type having a higher concentration than the source drift region formed in contact with the source drift region;
A gate insulating film formed on an upper layer of the semiconductor substrate;
A gate electrode formed in an upper layer of the gate insulating film from above the end of the source drift region on the first drain drift region side to above the end of the first drain drift region on the source drift region side; A semiconductor device comprising:   The semiconductor device according to claim 2, wherein the source region is a conductive material film doped to the second conductivity type formed in contact with the upper layer of the source drift region.   4. The semiconductor device according to claim 1, wherein the second drain drift region is formed at a position outside a region immediately below the gate electrode. 5.   The semiconductor device according to claim 1, wherein the drain region is an impurity diffusion region formed in the second drain drift region.   5. The conductive material film doped in the second conductivity type, wherein the drain region is formed in contact with the upper layer of the second drain drift region. 6. A semiconductor device according to 1. A method of manufacturing a semiconductor device according to claim 1,
A first step of implanting the second conductivity type impurity ions into a predetermined region of the semiconductor substrate to form the first drain drift region;
After completion of the first step, impurity ions of the second conductivity type are implanted into a predetermined region of the semiconductor substrate at a higher concentration and higher energy than in the first step, and continue to the first drain drift region. A second step of forming the second drain drift region having a bottom surface deeper than the first drain drift region;
After completion of the second step, impurity ions of the second conductivity type having a concentration higher than that of the second step are implanted into a predetermined region in the second drain drift region and a predetermined region separated from the first drain drift region. A third step of forming the drain region and the source region;
A fourth step of forming the gate insulating film on the semiconductor substrate after completion of the third step;
After the fourth step, the gate electrode is formed on the gate insulating film upper layer from above the end of the source region on the drain region side to above the end of the first drain drift region on the source region side. And a method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 3,
A first step of implanting impurity ions of the second conductivity type into a predetermined region of the semiconductor substrate to form a first diffusion region spaced apart from the first drain drift region and the first drain drift region;
A second step of forming the gate insulating film on the semiconductor substrate after completion of the first step;
After completion of the second step, the gate insulating film upper layer is formed from above the end of the first drain drift region on the first diffusion region side to above the end of the first diffusion region on the first drain drift region side. A third step of forming a gate electrode;
After completion of the third step, the second conductivity type impurity ions are implanted at a higher concentration and higher energy than in the first step using the gate electrode as a mask, continuing to the first drain drift region, and A fourth step of forming the second drain drift region having a deeper bottom surface than the first drain drift region, and a second diffusion region continuous to the first diffusion region;
After completion of the fourth step, a first insulating film is formed on the entire surface, and then a part of the source drift region formed by the first and second diffusion regions and the upper surface of the second drain drift region. A fifth step of opening so that the upper surface of the part is exposed;
After completion of the fifth step, a conductive material film doped in the second conductivity type at a higher concentration than the impurity ions implanted in the fourth step is formed on the entire surface, and then a patterning process is performed to perform the second step. And a sixth step of forming the drain region by the conductive material film in contact with the drain drift region and the source region by the conductive material film in contact with the source drift region, respectively. A method for manufacturing a semiconductor device.

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