JPH09293860A - Semiconductor integrated device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated device, and its manufacture, which comprises a pile up diffusion layer wherein formation of a contact at a micronized semiconductor integration device is easy, a diffusion layer is shallow and is of low resistance, and injection control into a channel is easy. SOLUTION: Multiple element separation insulation films (element separation insulation part) 2A and 2B which form an element area R3 are provided in a substrate 1, and, a source diffusion layer (source area) 5A and a drain diffusion layer (drain area) 5B for a carrier are provided in the element area R3, and further, conductive pile up diffusion layers (development layer) 18A and 18B which are piled upward while contacting to either the source diffusion layer 5A or the drain diffusion layer 5B and developed up to the position over the element separation insulation films 2A and 2B are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device and a method for manufacturing the same, and more particularly to a MOSFET device and a compound semiconductor FET device having a stacked diffusion layer.

[0002]

2. Description of the Related Art A compound semiconductor FET represented by GaAsFET, including MOS field effect transistors (hereinafter collectively referred to as MOSFET) such as NMOSFET, PMOSFET, and complementary CMOSFET.
As the degree of integration increases, the miniaturization of constituent parts according to the scaling law is progressing. When forming the source / drain diffusion layer regions of the MOSFET to be small, it is required to simultaneously reduce the photoresist alignment margin in order to form the contact hole at a preferable position on the diffusion layer.

Further, as elements are miniaturized in MOSFETs, for example, the short channel effect becomes remarkable,
In order to suppress such a short channel effect, it is considered effective to make the source and drain diffusion layers shallow. For example, in order to form a shallow junction depth between the source and drain diffusion layers, a method of performing an excimer laser annealing process of irradiating an excimer laser beam and heating after the ion implantation process has been proposed. According to this, when the wafer is irradiated with the excimer laser light, only the extreme surface layer of the wafer is heated in a short time, so that a shallow junction is formed.

It is preferable that the source / drain diffusion layers are formed shallow and the resistance of the source / drain diffusion layers is lowered. As a method therefor, a salicide process of forming a metal silicide layer (TiSi ₂ layer) made of a refractory metal such as titanium on the surface layers of the source and drain diffusion layers has been disclosed (IEEE TRAN).
SACTIONS ON ELECTRONON DEV
ICE Vol. 38, NO. 2, FEB 199
1). In this method, a compound of titanium and silicon is generated on the surface layer of the source / drain diffusion layer to reduce the resistance of the source / drain diffusion layer.

Further, in order to prevent punch through which occurs due to the short channel effect due to the miniaturization of semiconductor elements,
It is known that retrograde wells are used to increase the impurity concentration in a portion slightly deeper than the channel.

[0006]

However, when forming contact holes on the minute source / drain diffusion layers of the miniaturized MOSFETs as described above, it is technically necessary to make the alignment margin of the photoresist small. And there was a cost problem. Therefore, if the source and drain diffusion layers are small and the photoresist alignment margin is large, contact holes may be formed in regions other than the diffusion layer, and good conduction between the diffusion layer and the contact can be obtained. Not only that, but when the etching of the interlayer insulating film is started at the position on the element isolation insulating film, the element isolation insulating film is also etched with the formation of the contact hole, which causes a problem that current leakage occurs.

Further, in order to suppress the short channel effect which becomes remarkable as the element of the MOSFET is miniaturized, it is effective to make the source and drain diffusion layers shallow as described above. If the layer is formed of a shallow diffusion layer, the resistance value of the source / drain diffusion layer becomes high, which causes a problem that the current driving function of the MOS transistor deteriorates. That is, there is a trade-off between making the source and drain diffusion layers shallow (making the junction depth shallow) and reducing the resistance value of the source and drain diffusion layers, and it is difficult to achieve both at the same time.

For example, since the excimer laser annealing process is a high temperature annealing process, better crystals are formed in the source / drain diffusion layers than the rapid thermal annealing (RTA) process, and the source / drain diffusion layers are thereby formed. Although the resistance was slightly low, there was a limit in achieving a practical low resistance value.

Further, according to the salicide process for forming a metal silicide layer (TiSi ₂ layer) made of a refractory metal, which is disclosed as a method for reducing the resistance of the source / drain diffusion layers, the source / drain diffusion layers have a low resistance. However, there is a problem that the titanium silicide layer is likely to penetrate, resulting in current leakage.
For this reason, the depth of the source / drain diffusion layer must be deep enough not to penetrate the titanium silicide layer.
Therefore, there is a limit to how shallow the source / drain diffusion layer can be. As described above, the conventional methods and configurations have difficulty in forming the source and drain diffusion layers to be thin and have low resistance.

In the conventional manufacturing method, the MOSFET is
When the impurities are injected into the channel, the impurities are simultaneously injected into the portion other than the channel. Therefore, in order to prevent punch through caused by the short channel effect,
In the case of increasing the impurity concentration in a portion slightly deeper than the channel, this processing is simultaneously performed in the source and drain diffusion layers in the conventional manufacturing method. As a result, the impurity concentration near the junction at the bottom of the source / drain changes, and as a result, the source / drain changes shallower than necessary, which causes the above-described leakage current. As described above, in the conventional manufacturing method, it is difficult to individually control the impurity profile in the channel and the impurity profile in the source and the drain.

When accelerated diffusion becomes remarkable due to crystal defects generated at the time of implanting impurities, a high concentration of implanted impurities diffuses rapidly and reaches the channel, and the impurity concentration of the channel is changed to change the transistor characteristics. There was also a drawback that it deteriorated.

Furthermore, in the conventional manufacturing method, the processing of the gate electrode is performed by the lithography technique.
According to such a technique, the minimum processing line width at the time of resist molding is determined by the wavelength of light of the exposure apparatus. Therefore, when the gate electrode is manufactured by using the resist formed by the lithography technique as a mask, there is a problem that the minimum line width is limited.

The present invention has been made to solve the above-mentioned problems and drawbacks of the prior art, and the purpose thereof is to facilitate the formation of a contact to a miniaturized semiconductor integrated device, to make a diffusion layer shallow, and It is an object of the present invention to provide a semiconductor integrated device having a stacked diffusion layer and a method for manufacturing the same, which has a low resistance and facilitates control of injection into a channel.

[0014]

In order to solve the above-mentioned problems, a semiconductor integrated device according to the present invention comprises a plurality of element isolation insulating portions for forming an element region in a substrate, and a carrier is formed in the element region. A semiconductor integrated device having a source region and a drain region, wherein a conductive spreading layer that is stacked in contact with one of the source region and the drain region and is spread to a position on the element isolation insulating portion is provided. It is characterized in that it is equipped with.

A semiconductor integrated device according to the present invention is a field effect semiconductor integrated device, wherein an element isolation insulating film is applied as the element isolation insulating part, and a source diffusion layer and a drain diffusion layer are applied as the source region and the drain region. When a stacked diffusion layer is applied as the development layer, or particularly when the field effect semiconductor integrated device is any one of NMOSFET, PMOSFET, and complementary MOSFET using a silicon-based substrate, the area becomes smaller due to miniaturization. The contacts to the source diffusion layer and the drain diffusion layer are made via the stacked diffusion layers, a large alignment margin of the photoresist is secured, and the contacts are surely formed in the source and drain regions.

When the field effect semiconductor integrated device according to the present invention uses a compound semiconductor as a substrate, a minute semiconductor integrated device applicable to an ultra-high frequency region is realized, in particular, a metal is formed on the spread layer or the stacked diffusion layer. With the structure in which the system high melting point layer is formed, an increase in parasitic resistance is prevented.

Further, the semiconductor integrated device according to the present invention comprises a plurality of element isolation insulating films for forming an element region in a silicon substrate, and a carrier source diffusion layer and a carrier diffusion layer in the element region. , MO having a channel connected to the source diffusion layer and the drain diffusion layer
The SFET integrated device is configured by implanting impurities for adjusting transistor characteristics only in the channel. With this configuration, the impurity profile of the channel is controlled and formed independently of the impurity profiles of the source diffusion layer and the drain diffusion layer, and the device characteristics are adjusted without affecting the source diffusion layer and the drain diffusion layer.

Further, a method of manufacturing a semiconductor integrated device according to the present invention is a method of manufacturing a semiconductor integrated device having a gate electrode, in which a portion of the constituent layer covering the gate region is formed by opening a portion where the gate electrode is formed. Is provided, a step of providing a side wall on the side wall of the groove, and a step of burying a gate electrode in a void formed by the side wall are included in the above order. With this configuration, an arbitrary minute gate length is formed by changing the side wall width.

Further, the method for manufacturing a semiconductor integrated device according to the present invention includes a step of forming a plurality of element isolation insulating films and a step of forming a well in a region between the element isolation insulating films by implanting impurities. A manufacturing method,
After the well is formed, a step of forming an insulating film in a region other than the region where the stacked diffusion layer is spread over the element isolation insulating film, and a diffusion layer by implanting impurities into the substrate in the region where the insulating film is not formed. A step of forming a deposited layer on the diffusion layer, a step of polishing the deposited layer using an insulating film in a region other than the stacked diffusion layer forming region as a stopper to form a stacked diffusion pre-layer, A step of removing an insulating film in the gate region adjacent to the pre-stacked diffusion layer, a step of forming a sidewall insulation film on a side wall of the pre-stacked diffusion layer, and a lower end of a void formed by the side wall insulation film A step of injecting impurities into the channel portion in the substrate, and a step of forming a gate insulating film on the substrate at the lower end of the void formed by the sidewall insulating film,
A step of forming a gate deposition layer on the gate insulating film; a step of polishing the gate deposition layer using an insulating film in a region other than the stacked diffusion layer forming region as a stopper to form a pole material; It comprises a step of injecting impurities into the layer and the pole material to form a stacked diffusion layer and a gate electrode.

Therefore, according to the method of manufacturing a semiconductor integrated device, the insulating film formed outside the region where the stacked diffusion layer is formed serves as a mask, impurities are implanted into the substrate to form the diffusion layer, and the diffusion layer is formed on the diffusion layer. The deposited layer formed on the substrate is polished to be a stacked diffusion pre-layer, and then the sidewall insulating film formed on the sidewall of the stacked diffusion pre-layer is used as a mask to inject impurities into the channel portion and gate insulation on the channel. A film is provided, the gate deposition layer formed on the gate insulating film is polished into a pole material, and then impurities are injected into the pre-stack diffusion layer and the pole material to form the stack diffusion layer and the gate electrode. .

By thus forming the stacked diffusion layer and the gate electrode by polishing, the gate step is removed at the same time. Further, the gate length to be formed is controlled by adjusting the sidewall wall dimension, and thus the gate electrode is shaped to be equal to or less than the limit minimum value of the resist line width by the lithography technique.

When a refractory metal silicide layer is further formed on the stacked diffusion layer and the gate electrode subsequent to the above steps, the parasitic resistance value can be suppressed to a low value and the leakage current can be suppressed.

When the method for manufacturing a semiconductor integrated device of the present invention is one in which the stacked diffusion layer and the gate electrode are formed of a crystalline or polycrystalline or amorphous silicon film, stable conductivity is low. Realized at cost.

Further, according to the method of manufacturing a semiconductor integrated device of the present invention, the stacked diffusion layers and the gate electrodes are made of a refractory metal, a refractory metal silicide, a laminated film of silicon and a refractory metal, or silicon and a refractory metal silicide. In the case of using a laminated film, the resistance of the stacked diffusion layer and the gate electrode can be reduced without the silicidation reaction step.

[0025]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a schematic cross-sectional view illustrating a semiconductor integrated device S at a stage before a wiring process is performed, which is an embodiment of the semiconductor integrated device according to the present invention. As shown in FIG. 1, a semiconductor integrated device S according to the present invention is characterized by including a stacked diffusion layer, and an LO layer is formed on the surface of the semiconductor substrate 1 made of a silicon substrate.
An element region R3 is formed between two adjacent element isolation insulating films 2A and 2B of a plurality of element isolation insulating films (element isolation insulating portions) formed by the COS method.

The well 3 is formed in the element region R3 below the two element isolation insulating films 2A and 2B in the semiconductor substrate 1, and the two element isolation insulating films 2 on the surface of the semiconductor substrate 1 are formed.
A gate insulating film 10 is formed between A and 2B at a distance from the element isolation insulating film 2, and a gate electrode 12 is disposed above and in contact with the gate insulating film 10. In contact with the outer periphery of the gate electrode 12, the sidewall insulating films 9A and 9B
Are formed.

A source diffusion layer (source region) 5A is formed in the well 3 in a region from the element isolation insulating film 2A to a position just before the gate insulating film 10, and in the well 3,
A drain diffusion layer (drain region) 5B is formed in a region extending from the element isolation insulating film 2B to just before the gate insulating film 10. Further, low-concentration impurity implantation regions 6A and 6B protruding from the source diffusion layer 5A and the drain diffusion layer 5B to the gate insulating film 10 are formed, and a channel 20 is formed between the low-concentration impurity implantation regions 6A and 6B.

The concentration of impurities in the channel 20 is adjusted so that the device characteristics such as the threshold voltage are set to desired values. This impurity concentration is, separately from the impurity concentration of the source diffusion layer 5A or the drain diffusion layer 5B,
It has been adjusted to an independent value.

An insulating film 4A is deposited on the element isolation insulating film 2A, and the sidewall insulating film 9 is formed from the insulating film 4A along the element isolation insulating film 2A and the source diffusion layer 5A.
Filling the space up to A, stacking diffusion layer (expansion layer) 1
8A are formed. The stacked diffusion layer 18A is connected to the source diffusion layer 5A in the region indicated by R1. Therefore, the region indicated by R2 from the insulating film 4A to the sidewall insulating film 9A is formed larger than R1.

Similarly, an insulating film 4B is deposited on the element isolation insulating film 2B, and a space extending from the insulating film 4B to the sidewall insulating film 9B along the element isolation insulating film 2B and the drain diffusion layer 5B is filled. Thus, a stacked diffusion layer (developing layer) 18B is formed.

Therefore, the contact hole connected to the source diffusion layer 5A has only to be connected to the region R2 having a larger area. Therefore, the alignment margin of the photoresist becomes large, and the source diffusion is caused by the miniaturization of the element. Layer 5
Even if the area A is miniaturized, contact holes can be easily formed. The same applies to the contact hole connected to the drain diffusion layer 5B.

Further, since the gate electrode 12 can be formed to have an arbitrary size by adjusting the size of the sidewall insulating films 9A and 9B, the gate electrode 12 is shaped to be equal to or less than the limit minimum value of the resist line width by the lithography technique. can do.

Next, a method of manufacturing a semiconductor integrated device according to the present invention will be described with reference to FIGS. In the method for manufacturing a semiconductor integrated device according to the present invention, as a first step, as shown in FIG.
As shown in FIG. 1, a device isolation insulating film 2 is formed on a wafer 1 which is a semiconductor substrate, for example, a silicon wafer, by LOCO.
It is formed using the S method. The LOCOS film thickness is, for example, 300
The element is separated by adjusting to nm.

Next, as the second step, well implantation is performed to form the well 3 as shown in FIG.

As a third step, a silicon oxide film, for example, of about 150 nm is deposited on the entire surface of the wafer 1 by the CVD method or the like, and only the portion of the deposited silicon oxide film where a stacked diffusion layer to be described later is formed is formed by the lithography technique. Then, the insulating films 4A, 4B, and 4C are removed by using a dry etching technique or the like as shown in FIG.
The insulating film 4C becomes a constituent layer that covers the gate region.

As the fourth step, as shown in FIG.
The insulating films 4A, 4B, and 4C formed in the third step are used as implantation masks, or the dry etching resists superimposed in the third step are added to these insulating films 4A to 4C to serve as implantation masks, sources, Impurity implantation for forming the drain diffusion layer is performed by an ion implantation method. For example, in the case of NMOS, As
Is implanted with energy of about 50 KeV, and in the case of PMOS, BF ₂ is implanted with energy of about ₂₀ KeV to form the source and drain diffusion layers 5A and 5B, respectively.

At this time, in order to avoid the deterioration of the transistor characteristics due to hot carriers, it is possible to provide a low-concentration impurity-implanted region for relaxing the electric field at the drain end. In this case, low-concentration implantation is performed obliquely so that the low-concentration impurity implantation regions 6 (shown in FIG. 6) are formed at the source and drain ends.

Next, as a fifth step, as shown in FIG. 7, for example, polysilicon (deposited layer) 7 is deposited on the entire surface of the wafer 1 by a CVD method or the like to form a stacked diffusion layer. The film thickness of the polysilicon 7 to be deposited is such that the steps of the insulating films 4A to 4C formed in the third step are buried, and for example, about 200 nm is deposited.

As the sixth step, as shown in FIG.
Using the insulating films 4A to 4C formed in the third step as stoppers, the polysilicon 7 deposited in the fifth step is polished to form pre-diffusion layers 8A and 8B.

As the seventh step, as shown in FIG.
Only the insulating film 4C formed in the gate electrode formation portion formed in the third step is removed by a lithography technique and a dry or wet etching technique.

As an eighth step, as shown in FIG. 10, sidewall insulating films 9A and 9B made of, for example, a silicon oxide film are formed on the sidewalls of the pre-diffusion layers 8A and 8B by an etch back method. In this case, the gate length Lt is determined by the width of the sidewall insulating films 9A and 9B to be formed, but the gate length Lt should not be smaller than the effective gate length Le. For example, the sidewall width is formed to be about 0.15 μ.

In the ninth step, using the pre-stacked diffusion layers 8A and 8B formed in the sixth step as an implantation mask, impurities are implanted only into the channel portion to suppress punch-through and adjust the threshold voltage.

Next, as a tenth step, as shown in FIG. 11, a gate insulating film 10 is formed on the formation portion of the gate electrode by thermal oxidation or the like to a thickness of about 6 nm.

Next, as an eleventh step, as shown in FIG. 12, for example, polysilicon (gate deposition layer) 11 for forming a gate electrode is deposited on the entire surface of the wafer 1 by a CVD method or the like. The thickness of the deposited polysilicon 11 is
It suffices if the steps of the pre-diffusion layers 8A and 8B formed in the sixth step are filled up, and for example, about 200 nm is deposited.

Next, as a twelfth step, as shown in FIG. 13, the insulating films 4A, 4B and the side wall insulating films 9A, 9B formed in the eighth step are used as stoppers to deposit in the eleventh step. The polysilicon 11 thus formed is polished to form an electrode material 22. At this time, the sidewall insulating film 9A, the
9B is also slightly polished so that the insulating separation between the subsequently formed stacked diffusion layer and the gate electrode is effectively performed.

Next, as a thirteenth step, impurities are implanted into the pre-diffusion layers 8A and 8B and the pole material 22. For example, in the case of NMOS, arsenic As is about 50 KeV, PM
In the case of OS, boron B is ion-implanted with energy of about 5 KeV.

In the fourteenth step, activation annealing of the impurities implanted up to the thirteenth step is performed. The activation annealing is performed by rapid thermal annealing (RTA) at 1000 ° C. for about 10 seconds. As a result, the stacked diffusion pre-layers 8A and 8B serve as the stacked diffusion layers 18A and 18B, and the pole material 22 serves as the gate electrode 12, whereby the semiconductor integrated device S as shown in FIG. 1 is manufactured. In the subsequent steps, an interlayer insulating film, contacts, wirings, etc. are formed in the same manner as in the past, and a MOS transistor is manufactured.

14 to 16 show another embodiment.
The process up to the 13th step of the above-mentioned embodiment is the same, and the description thereof is omitted. As a first step, as shown in FIG. 14, a titanium film 13 is formed on the entire surface of the wafer 1 by, for example, about 30 nm.
It is deposited by a sputtering method.

As a second step, as shown in FIG. 15, this is subjected to a first heat treatment at about 600 degrees Celsius to cause a silicidation reaction only on the stacked diffusion layers 18A, 18B and the gate electrode 12 to form C49 titanium. Silicide 1
4 is formed.

In the third step, as shown in FIG. 16, unreacted titanium except on the stacked diffusion layers 18A and 18B and on the gate electrode 12 is removed by a wet etching method using, for example, ammonia / hydrogen peroxide, and then, C4
9 titanium silicide 14 to C54 titanium silicide 15
The second heat treatment at about 800 degrees Celsius is performed to cause the phase transition to the.

In the subsequent steps, an interlayer insulating film, contacts, wirings, etc. are formed in the same manner as in the conventional case, and a MOS transistor is manufactured.

According to the above-described manufacturing method, impurity implantation is performed with the gate region masked by the insulating film to form the source and drain diffusion layers. Therefore, the impurity is not implanted into the channel when the diffusion layer is formed. After the source and drain diffusion layers are formed, a deposited layer is formed, and this is polished to form a layer before stacking diffusion.At this stage, the source and drain diffusion layers are sealed inside and used for subsequent ion implantation. It will not be affected. Then, after the sidewall insulating film is formed on the side wall of the pre-stacked diffusion layer, impurities are injected into the channel portion to create device characteristics such as threshold voltage, but the source and drain diffusion layers are closed from the outside. Therefore, the source and drain diffusion layers are not affected by this impurity implantation operation.

As a result, a sufficient alignment margin for forming the contact hole can be secured, and the contact hole can be easily formed in the stacked diffusion layer.
Good contact with the source and drain diffusion layers is possible. Further, the source and drain diffusion layers are not made shallower than necessary, accelerated diffusion of impurities is prevented, transistor characteristics are not deteriorated, and punch through is suppressed.

Although the above is one embodiment of the present invention, the present invention is not limited to this, and other configurations are possible. For example, although the stacked diffusion layers are made of polysilicon in the above-described embodiment, a refractory metal can be used as long as it is a material that can ensure the selection ratio with the insulating film in polishing.

Furthermore, the present invention can be applied to the manufacture of CMOS transistors. For CMOS transistors, lithographic techniques are used to perform impurity implantation using NMO.
It may be formed for each of S and PMOS.

The insulating film used in the third and eighth steps is not limited to the silicon oxide film, and an insulating film such as a silicon nitride film can be used.

Further, although the insulating film used for element isolation is also formed by the LOCOS method in the above embodiment, other element isolation techniques such as the trench method may be applied.

The refractory metal used for forming the silicide is not limited to titanium, and a refractory metal such as cobalt, nickel or platinum may be used.

[0059]

According to the first aspect of the present invention, the semiconductor integrated device is formed by stacking the conductive spreading layer in contact with the source region or the drain region upward and spreading the conductive spreading layer up to a position on the element isolation insulating portion. As a result, it is possible to prevent a reduction in the alignment margin for forming the contact hole in the diffusion layer, the area of which is reduced due to the miniaturization. That is, by forming a development layer having an area R2 larger than the area R1 in contact with the diffusion layer, a sufficient alignment margin can be secured, and a contact hole can be easily formed on the development layer. It is possible to realize good contact of

In the field effect semiconductor integrated device according to the second aspect of the present invention, the stacked diffusion layer is formed so as to be spread over the element isolation insulating film to form a contact hole in a minute diffusion layer in a lithography process. , A sufficient alignment margin can be secured.

A field effect semiconductor integrated device according to claim 3 of the present invention is an NMOSFET and a PM based on a silicon substrate.
Since it is an OSFET or a complementary MOSFET,
The effects of the present invention can be realized for all MOSFETs.

Since the field effect semiconductor integrated device according to claim 4 of the present invention uses a compound semiconductor as a substrate,
The effects of the present invention can be realized for all compound semiconductor FETs.

In the semiconductor integrated device according to the fifth aspect of the present invention, since the refractory silicide is formed on the stacked diffusion layer, there is an effect that parasitic resistance can be prevented from increasing.

In the semiconductor integrated device according to the sixth aspect of the present invention, the impurity for self-aligning the transistor characteristics is injected only into the channel of the MOSFET having the channel connected to the source diffusion layer and the drain diffusion layer. Therefore, the punch-through stopper and the threshold voltage can be created with high accuracy, and the impurity implantation does not reach the source diffusion layer and the drain diffusion layer. Therefore, it is possible to eliminate the increase of the leak current which accompanies it. Further, it is possible to prevent deterioration of device characteristics due to accelerated diffusion of impurities into the channel.

According to a seventh aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated device, which comprises a step of forming a groove by opening a portion of a constituent layer covering a gate region where a gate electrode is formed, and a sidewall on a side wall of the groove. Since the step of forming the gate electrode and the step of burying the gate electrode in the void formed by the sidewall are performed in this order, the minimum line width (gate length) in forming the gate electrode is the resolution limit of lithography. It is possible to manufacture semiconductors with a gate length less than the resolution limit by preventing the dependence. This speeds up the LSI,
Low power consumption can be achieved.

In the method for manufacturing a semiconductor integrated device according to the eighth aspect of the present invention, an insulating film is formed outside the region where the stacked diffusion layers are formed, and then the diffusion film is formed by implanting impurities into the substrate using the insulating film as a mask. Then, after forming a deposited layer on this diffusion layer, polishing is performed to form a stacked diffusion front layer, and then a sidewall insulating film is formed on the sidewall of the stacked diffusion diffusion layer, and impurities are implanted into the channel portion to After forming a gate insulating film on the above, further forming a gate deposition layer, polishing this to form a pole material, then injecting impurities into the pre-stack diffusion layer and the pole material to form the stack diffusion layer and gate electrode Therefore, the semiconductor integrated device according to claim 1, 2, 3, 4, or 6 can be manufactured by this manufacturing method.

Furthermore, since the stacked diffusion layer and the gate electrode are formed by polishing, the gate step can be removed at the same time. Therefore, the condition of the depth of focus in the lithography process in the interlayer process such as the contact hole and the aluminum wiring is relaxed, thereby enabling finer processing.

Further, since the gate length can be controlled by the sidewall wall, the gate length can be independently controlled with respect to the effective gate length determined by the lateral diffusion of impurities when the source / drain diffusion layers are formed. The gate capacitance can be reduced as compared with the case of manufacturing a semiconductor having the same gate length. This has the advantage that the gate delay can be reduced and a high speed and low power consumption semiconductor device can be manufactured.

In the method for manufacturing a semiconductor integrated device according to the ninth aspect of the present invention, the refractory metal silicide layer is formed on the stacked diffusion layer and the gate electrode subsequent to the step of the eighth aspect. According to the manufacturing method, the semiconductor integrated device according to the fifth aspect can be manufactured.

In the method for manufacturing a semiconductor integrated device according to the tenth aspect of the present invention, since the stacked diffusion layer and the gate electrode are formed of a silicon film of crystalline, polycrystalline or amorphous, the cost is low. Stable conductivity can be realized.

A method of manufacturing a semiconductor integrated device according to an eleventh aspect of the present invention is a method of manufacturing a refractory metal, refractory metal silicide, silicon / refractory metal laminated film, or silicon / refractory metal silicide laminated film. Since the stacked diffusion layer and the gate electrode are formed, the resistance of the stacked diffusion layer and the gate electrode can be reduced without involving the silicidation reaction step, so that the semiconductor integrated device can be manufactured by a simpler process. Saves money, time and time.

Further, since the manufacturing method according to the present invention can be easily carried out in the conventional semiconductor manufacturing line, there is an advantage that the effect can be obtained without a significant increase in cost.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of an embodiment of a semiconductor integrated device according to the present invention.

FIG. 2 is a cross-sectional view showing element isolation formation in an embodiment of a method for manufacturing a semiconductor integrated device according to the present invention.

FIG. 3 is a cross-sectional view showing well formation in the method of manufacturing the semiconductor integrated device shown in FIG.

4 is a cross-sectional view showing formation of an insulating film in a region other than the stacked diffusion layers in the method for manufacturing the semiconductor integrated device shown in FIG.

5 is a cross-sectional view showing the formation of source / drain diffusion layers in the method of manufacturing the semiconductor integrated device shown in FIG.

FIG. 6 is a cross-sectional view showing formation of a low-concentration impurity implantation region in the method for manufacturing the semiconductor integrated device shown in FIG.

7 is a cross-sectional view showing deposition of polysilicon for forming a stacked diffusion layer in the method for manufacturing the semiconductor integrated device shown in FIG.

8 is a cross-sectional view showing the formation of stacked diffusion pre-layers in the method for manufacturing the semiconductor integrated device shown in FIG.

9 is a cross-sectional view showing the removal of the insulating film in the gate region in the method for manufacturing the semiconductor integrated device shown in FIG.

10 is a cross-sectional view showing formation of a sidewall insulating film in the method of manufacturing the semiconductor integrated device shown in FIG.

11 is a cross-sectional view showing formation of a gate insulating film in the method of manufacturing the semiconductor integrated device shown in FIG.

12 is a cross-sectional view showing deposition of polysilicon for forming a gate electrode in the method for manufacturing the semiconductor integrated device shown in FIG.

FIG. 13 is a cross-sectional view showing a pole material in the method for manufacturing the semiconductor integrated device shown in FIG.

FIG. 14 is a cross-sectional view showing titanium film formation in another embodiment of the method for manufacturing a semiconductor integrated device according to the present invention.

15 is a diagram showing a method of manufacturing the semiconductor integrated device shown in FIG.
It is sectional drawing which shows C49 titanium silicide formation.

16 is a diagram showing a method of manufacturing the semiconductor integrated device shown in FIG.
It is sectional drawing which shows C54 titanium silicide formation.

[Explanation of symbols]

S ... Semiconductor integrated device, 1 ... Wafer (semiconductor substrate), 2 ... Element isolation insulating film (element isolation insulating part), 3 ...
Wells, 4A, 4B ... Insulating films, 5A ... Source diffusion layers (source regions), 5B ... Drain diffusion layers, 6A, 6
B ... Low-concentration impurity implantation region, 7 ... Polysilicon (deposited layer), 9A, 9B ... Sidewall insulating film, 10 ...
... Gate insulating film, 12 ... Gate electrode, 13 ... Titanium film, 14 ... C49 Titanium silicide, 15 ... C54
Titanium silicide, 18A, 18B ... Stacked diffusion layer (spread layer), 11 ... Polysilicon (gate deposition layer),
20 ... Channel, 22 ... Pole material, R1, R2 ... Stacked diffusion layer size, R3 ... Element area.

Claims (11)

[Claims] 1. A semiconductor integrated device comprising a plurality of element isolation insulating portions for forming an element region in a substrate, and a source region and a drain region of carriers in the element region, the source region or the drain A semiconductor integrated device, comprising a conductive spreading layer that is stacked upward in contact with one of the regions and is spread to a position on the element isolation insulating portion. 2. The element isolation insulating part is an element isolation insulating film, the source region and the drain region are source diffusion layers and drain diffusion layers, the development layer is a stacked diffusion layer, and the semiconductor integrated device is The semiconductor integrated device according to claim 1, wherein the semiconductor integrated device is a field effect semiconductor integrated device. 3. The semiconductor integrated device according to claim 2, wherein the field effect semiconductor integrated device is one of an NMOSFET, a PMOSFET, and a complementary MOSFET formed of a silicon substrate. 4. The semiconductor integrated device according to claim 2, wherein the field effect semiconductor integrated device uses a compound semiconductor as a substrate. 5. The semiconductor integrated device according to claim 1, wherein a metallic refractory layer is formed on the spread layer or the stacked diffusion layer. 6. A plurality of element isolation insulating films for forming an element region in a silicon substrate, and a carrier source diffusion layer and a drain diffusion layer in the element region, and a source diffusion layer and a drain diffusion layer. A semiconductor integrated device having a channel connected to the semiconductor device, wherein impurities for adjusting transistor characteristics are implanted only in the channel. 7. A method of manufacturing a semiconductor integrated device having a gate electrode, which comprises: forming a groove by opening a portion of a constituent layer covering a gate region where a gate electrode is formed; and forming a groove on a side wall of the groove. A method of manufacturing a semiconductor integrated device, comprising: a step of providing a wall; and a step of burying a gate electrode in a void formed by the side wall, in the order described above. 8. A method of manufacturing a semiconductor integrated device, comprising: a step of forming a plurality of element isolation insulating films; and a step of forming a well in a region between the element isolation insulating films by impurity implantation. A step of forming an insulating film in a region other than a region where a stacked diffusion layer is spread over the isolation insulating film, a step of forming a diffusion layer by implanting impurities into a substrate in a region where the insulating film is not formed, A step of forming a deposited layer on the diffusion layer, a step of polishing the deposited layer using an insulating film in a region other than the stacked diffusion layer formation region as a stopper to form a stacked diffusion pre-layer, and a step of forming the stacked diffusion pre-layer A step of removing an insulating film adjacent to the gate region, a step of forming a sidewall insulating film on a side wall of the pre-diffusion layer, and a step of forming the sidewall insulating film. A step of injecting an impurity into the channel portion in the substrate at the lower end of the void portion, a step of forming a gate insulating film on the substrate at the lower end of the void portion formed by the sidewall insulating film, and a gate on the gate insulating film A step of forming a deposited layer; a step of polishing the gate deposited layer using an insulating film in a region other than the stacked diffusion layer forming region as a stopper to form a pole material; and an impurity in the stacked diffusion pre-layer and the pole material. A method of manufacturing a semiconductor integrated device, comprising the steps of implanting to form a stacked diffusion layer and a gate electrode. 9. A method of manufacturing a semiconductor integrated device, which is characterized in that, following the step of claim 8, a refractory metal silicide layer is formed on the stacked diffusion layer and the gate electrode. 10. The method for manufacturing a semiconductor integrated device according to claim 8, wherein at least one of the stacked diffusion layer and the gate electrode is a crystalline, polycrystalline, or amorphous silicon film. . 11. A refractory metal, a refractory metal silicide, or a laminated film of silicon and a refractory metal, wherein at least one of the stacked diffusion layer and the gate electrode is formed.
10. A method of manufacturing a semiconductor integrated device according to claim 8, wherein a laminated film of silicon and refractory metal silicide is used.