JPH08306798A - Semiconductor device and its fabrication - Google Patents

Abstract

PURPOSE: To enhance the drain-source breakdown strength without increasing the contact resistance by connecting the lightly doped drain-source region of a high breakdown strength MOS transistor directly with a drain-source electrode and composing the drain-source electrode of a conductor containing polysilicon. CONSTITUTION: The drain-source of an MOS transistor is constituted only of a lightly doped second conductivity type drain-source region 15 and a drain- source electrode 38 is connected not through a heavily doped second conductivity region but directly the second conductivity type drain-source region 15. The drain-source electrode 38 is composed not of Al but of a second conductivity type conductor layer 49 containing polysilicon. With such structure, fine patterning of MOS transistor can be attained while preventing the contact resistance from increasing between the drain-source region and the drain-source electrode and high breakdown strength is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOS transistor and its manufacturing method. More specifically, the present invention relates to a semiconductor device having a high breakdown voltage MOS transistor suitable for use in, for example, a boost portion of a DRAM, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a DRAM, in order to apply a sufficiently high voltage to a capacitor of a memory cell and write data surely, the voltage applied to a word line is boosted to a voltage higher than a power supply voltage. There is. FIG. 21 shows an example of a bootstrap word line drive circuit for applying a boosted voltage to a word line. In the figure, first and second N-type M
The OS transistors 551 and 552 are connected in series, and the drain d of the third N-type MOS transistor 553 is connected.
₃ is connected to the gate g _{1 of the} transistor 551 at the node A.

A boosted voltage V ₀ from a booster circuit (not shown) is applied to the drain d _{1 of the} transistor 551 through a terminal 555, and a gate g _{3 of the} transistor 553 is supplied with power from a power source (not shown). Voltage V _CC is applied via terminal 556. An output signal of a decoder (not shown) is applied to the source s _{3 of the} transistor 553 via the terminal 557. The source s ₃ and the terminal 557 are the node B
Connected by. Gate g of transistor 552
₂ is connected to the reset signal line RL via the terminal 558. The source s ₁ of the transistor 551 and d _{2 of the} transistor 552 are connected to each other at the node D, and the node D is connected to the word line WL via the terminal 559. The source s _{2 of the} transistor 552 is grounded.

According to the output signal of the decoder, the source s
The potential of ₃ (node B) becomes V _CC , and the transistor 55
3 is turned on, the drain d _{3 of the} transistor 553
The potential of the (node A) becomes V _CC -V _th (V _th is the threshold voltage of the transistor 553). Therefore, the transistor 55
1 is turned on, the transistor 553 is turned off, and the drain d ₃ is in a floating state. Since the potential of the node A becomes the voltage V _r boosted to the boosted voltage V ₀ or higher by the gate capacitance coupling of the transistor 551, the boosted voltage V ₀ at the node D is applied to the word line WL without voltage drop. To be done. For example, V _CC = 5V, V
₀ = 7.5V, a V _r = 14V.

Since a voltage V _r obtained by boosting the power supply voltage V _CC is applied to the drain d ₃ of the transistor 553, a sufficient breakdown voltage is required for the diffusion layer forming the drain d ₃ . If the diffusion layer forming the drain d ₃ does not have a sufficient breakdown voltage, the potential of the node A gradually decreases, and the voltage applied to the word line WL cannot be maintained at V ₀ .

As a method of preventing the potential of the node A from decreasing,
Although it is conceivable to increase the thickness of the gate oxide film of the transistor 553, this is contrary to the recent tendency of thinning the gate oxide film with the miniaturization of semiconductor devices. Therefore, as described later, the present invention proposes to apply a high breakdown voltage transistor to the transistor to which the voltage V _r is applied. However, there are many word line driving circuits in a semiconductor memory device, and if a conventionally known high breakdown voltage transistor is used, the occupied area is large, which causes an increase in the chip area.

As a conventional example, for example, the LD shown in FIG.
There is a high breakdown voltage MOS transistor having a D structure. The drain d _{3 of the} transistor 553 is formed by a relatively low concentration and wide N-type layer 553d, and the breakdown voltage is increased by widening the depletion layer generated at the junction between the N-type layer 553d and the P-type semiconductor substrate 600. It is possible. Also, the drain electrode 6
Since 01 is usually made of aluminum (Al), the drain d ₃ is a relatively high-concentration N ⁺ -type layer 553e at the portion connected to the drain electrode 601 so that the contact resistance does not increase. In FIG. 22, 602 is a field oxide film, 603 is a gate oxide film, and 604 is BPS.
It is a G interlayer insulating film.

As a method of manufacturing the above-mentioned conventional example, there are generally first and second methods. According to the first method, a preformed N ⁺ layer 553e Against the drain electrode 60
A contact hole for 1 is formed. On the other hand, according to the second method, ion implantation is performed through the contact hole for the drain electrode 601 to form the N ⁺ type layer 553e in a self-aligned manner.

[0009]

FIG. 23 is a diagram for explaining the first method. In the figure, L ₁ is a gate g ₃
And the N ⁺ type layer 553e, L ₂ is a distance at which the BPGS interlayer insulating film 604 and the N ⁺ type layer 553e overlap, and L ₃ is a distance corresponding to the width of the contact hole for the source electrode 601. is there. The withstand voltage of the drain d ₃ is L ₁
Is determined. However, if the N-type layer 553d directly contacts the Al drain electrode 601, the contact resistance becomes too large. Therefore, it is necessary to provide the N ⁺ -type layer 553e for contact with the drain electrode 601. There is a limit to the reduction of L ₃ of. In addition, if the contact hole is not formed with a margin of L _2, the drain electrode 601 is directly connected to the N-type layer 553.
Since there is a possibility of contact with d, there is a limit in reducing L ₂ . Therefore, conventionally, in order to secure the breakdown voltage of the drain d ₃ which is determined by L ₁ , the element spreads laterally by a distance of L ₁ + L ₂ + L ₃ . That is, there is a limit to the reduction of the area occupied by the high voltage MOS transistor.

FIG. 24 is a diagram for explaining the second method. In the figure (a), an N-type layer 553s is formed,
A state in which contact holes are formed in the BPSG interlayer insulating film 604 and the gate oxide film 603 is shown. FIG. 2B shows a step of forming an N ⁺ type layer 553e and an N ⁺ type layer 553s forming the source s ₃ by performing ion implantation after forming the resist layer 605. During this ion implantation,
Due to the alignment margin of the resist layer 605, the impurity ions are also implanted into the portion indicated by the “x” mark in FIG. Therefore, if the pretreatment with the HF-based etchant is performed before the step of forming the Al layer forming the drain electrode 601, the etching rate of the ion-implanted portion is higher than that of the other portions, and therefore, FIG. The step 610 shown in FIG. If there is such a step 610, it is easy to cause a disconnection in a wiring layer formed thereafter,
Not preferred. In addition, compared to the first method, the N ⁺ type layer 55
Since 3e is formed in a self-aligned manner, there is an advantage that L ₂ can be reduced, but L ₁ + L
There is a limit to the reduction of the area occupied by the high voltage MOS transistor in order to secure ₂ + L ₃ . Also, the second method requires more steps than the first method.

According to the present invention, a high breakdown voltage transistor is applied to a semiconductor memory device, and further, the occupied area is reduced so as not to increase the chip area and the number of steps of the semiconductor memory device, and the drain / source electrodes are formed. High breakdown voltage MO that enables high breakdown voltage of the drain / source without increasing contact resistance with the diffusion layer forming the drain / source
A semiconductor device having an S transistor and a manufacturing method thereof are realized.

[0012]

The above-mentioned problem is solved by claim 1.
A semiconductor substrate, an element isolation region, a first diffusion region and a second diffusion region having a conductivity type opposite to that of the semiconductor substrate;
A semiconductor device having a high breakdown voltage MOS transistor and a memory cell, which comprises a first electrode formed on the first diffusion region, a second electrode formed on the second diffusion region, and a gate electrode. The impurity concentration of the first diffusion region is lower than that of the second diffusion region, and at least the first electrode is made of polycrystalline silicon having an impurity concentration higher than that of the first diffusion region. Another MOS having a gate electrode connected to the first electrode of the high breakdown voltage MOS transistor, the first electrode being applied with a voltage higher than the voltage applied to the second electrode. This is achieved by a semiconductor device including a transistor and configured such that a boosted voltage is applied to one of a source electrode and a drain electrode of the other MOS transistor.

The above problem is a method of manufacturing a semiconductor device having at least a high breakdown voltage MOS transistor and a MOS transistor forming a memory cell on a semiconductor substrate according to a sixth aspect of the present invention, wherein a field is selectively formed on the semiconductor substrate. A step of forming an oxide film, a step of sequentially forming a gate oxide film and a gate electrode in a region on the semiconductor substrate defined by the field oxide film, and a step of first ion implantation for forming the semiconductor on both sides of the gate electrode. A step of forming an impurity region having a conductivity type opposite to that of the substrate, and M forming the memory cell.
Covering the impurity region of the OS transistor and one impurity region of the high breakdown voltage MOS transistor with a mask layer;
Second ion implantation is performed using the field oxide film, the gate electrode of the high breakdown voltage MOS transistor and the mask layer as a mask to change the impurity concentration of the other impurity region of the high breakdown voltage MOS transistor to the impurity concentration of the one impurity region. A method of manufacturing a semiconductor device including a step of further increasing the temperature and a step of directly forming an electrode made of a conductor containing polycrystalline silicon having an impurity concentration higher than that of the one impurity region on at least the one impurity region. Also achieved by.

According to the present invention, the relatively low concentration drain / source region of the high breakdown voltage MOS transistor is drain / source region.
Since it is directly connected to the source electrode, it is possible to miniaturize the MOS transistor. Since a conductor containing polycrystalline silicon is used for the drain / source electrode, a contact between the drain / source region and the drain / source electrode is made. It is possible to prevent an increase in resistance and realize a high breakdown voltage.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a high breakdown voltage M used in the present invention.
It is a principle explanatory view of an OS transistor. In the figure, 1 is a first conductive type semiconductor substrate, 13 is a gate oxide film, 14 and a gate electrode, 15 is a second conductive type drain / source region having a relatively low impurity concentration, and 16 is a relatively high impurity concentration. Two-conductivity type source / drain regions, 28 is a source / drain electrode contact hole, 29 is a drain / source electrode contact hole, 35 is a source / drain electrode, 38 is a drain / source electrode, and 27 is an interlayer insulating film. Source / drain electrode 35 and drain / source electrode 38
Is formed of a conductor layer 49 containing polycrystalline silicon of the second conductivity type and having an impurity concentration higher than that of the drain / source region 15 of the second conductivity type. The first and second conductivity types are opposite conductivity types.

The drain / source of the MOS transistor is a drain / source region 1 of the second conductivity type having a relatively low concentration.
The drain / source electrode 38 is directly connected to the second conductivity type drain / source region 15 without the relatively high concentration second conductivity type region. Therefore, the L ₂ required by the conventional method becomes unnecessary, and the MOS is correspondingly required.
The transistor can be miniaturized.

Although the drain / source electrode 38 is directly connected to the relatively low concentration second conductivity type drain / source region 15, the drain / source electrode 38 is not Al but the second.
Since the conductive type conductive layer 49 includes polycrystalline silicon, the contact resistance does not increase. Further, since the second conductivity type drain / source region 15 having a relatively low concentration is thin, forming an Al electrode right above causes a problem of Al spike, but since the drain / source electrode 38 does not use Al, a spike problem occurs. Does not occur.

Further, as compared with the contact between Al and Si, the contact between polycrystalline silicon and Si can be contacted with a low impurity concentration. Since the withstand voltage of the transistor increases as the impurity concentration decreases, the present invention makes it easier to increase the withstand voltage of the transistor as compared with the conventional example.

Second Constituting Drain / Source Electrode 38
When the conductive type conductive layer 49 containing polycrystalline silicon is formed, the impurities in the conductive layer 49 diffuse into the second conductive type drain / source region 15 having a relatively low concentration shallower than the depth thereof due to solid phase diffusion. To do. This makes it possible to reduce the contact resistance. Further, since the boundary between the second conductivity type drain / source region 15 having a relatively low concentration and the portion having a high concentration due to the solid-phase diffusion is gentle, a structure having a higher breakdown voltage than that of the conventional one is realized. It

FIG. 2 is a diagram showing the characteristics of the high breakdown voltage MOS transistor used in the present invention in comparison with the conventional example. In the figure, the vertical axis represents the impurity concentration on a log scale, and the horizontal axis represents the x direction in FIGS. The broken lines I and II show the characteristics of the conventional example manufactured by the first and second methods, respectively, and the alternate long and short dash line III shows the characteristics of the high withstand voltage MOS transistor according to the present invention.

Therefore, according to the present invention, the area occupied by the multi-voltage MOS transistor is reduced, and the drain / source is not increased without increasing the contact resistance between the drain / source electrode and the diffusion region constituting the drain / source. It is possible to increase the withstand voltage.

[0022]

FIG. 3 shows a first embodiment of the semiconductor device according to the present invention.
Will be explained together. FIG. 1A is a sectional view of the semiconductor device, and FIG. 1B is a circuit diagram thereof. A P-type semiconductor substrate 1 made of silicon or the like is formed with a plurality of elements such as N-type MOS transistors described later. The bootstrap word line drive circuit 2 for applying a voltage to the word line WL includes three MOS transistors 3 to 5 described later.
The first MOS transistor 3 and the second MOS transistor 4 are connected in series, and the drain layer 15 of the third MOS transistor 5 is connected to the gate electrode 7 of the first MOS transistor 3.

The first MOS transistor 3 is a semiconductor substrate.
A gate electrode formed on the plate 1 via a gate oxide film 6.
Formed on the semiconductor substrate 1 on both sides of the pole 7 and the gate electrode 7.
Was N ⁺And N^-Source layer 8 of LDD structure and drain
And the in-layer 9.

The second MOS transistor 4 is formed by the gate electrode 11 provided on the semiconductor substrate 1 with the gate oxide film 10 interposed therebetween, and the source layer 12 and the drain layer 113 of the LDD structure formed on both sides of the gate electrode 11. ing. Since the drain layer 113 is provided integrally with the source layer 9 of the first MOS transistor 3, the first and second MO transistors are formed.
The S transistors 3 and 4 are connected in series.

The third MOS transistor 5 has a gate electrode 14 formed on the gate oxide film 13, an N ^-- type conductive layer 15 is provided on the substrate 1 on one side, and an LDD is provided on the other side. The conductive layer 16 having the structure is formed. The N ^{− type} conductive layer 15 is connected to the gate electrode 7 of the first MOS transistor 3 by a wiring electrode (not shown).

Stacked capacitor type DRAM cell 17
The fourth MOS transistor 18 included in the insulating film 20 is formed in the same manner as the three MOS transistors 3 to 5 described above.
Gate electrode 21 formed on the semiconductor substrate 1 via
When, N-type provided on both sides or N ^- type conductive layer 22,
23. One conductive layer 22 is connected to the bit line BL, and the gate electrode 21 is connected to the word line WL. A capacitor 19 of the DRAM cell 17 is provided on the other conductive layer 23 through a contact hole 34 described later. The capacitor 19 includes a storage electrode 24 made of polycrystalline silicon doped with N-type impurity ions such as phosphorus (P), a dielectric film 25 made of SiO ₂ , and a counter electrode made of polycrystalline silicon containing N-type impurity ions. It is formed by sequentially stacking the electrode 26, and a voltage of V _CC / 2 is applied to the counter electrode 26.

First to fourth MOS transistors 3 to 5, 1
Contact holes 28 to 33 for exposing the conductive layers 8, 9, 15, 16 and the like are formed in the interlayer insulating film 27 made of PSG or the like formed on the surface 8. Interlayer insulation film 27
On top of each of the source layers 9, 12 and drain layers 8, 13
Electrodes 35 to 40 made of polycrystalline silicon in which impurities of the same polarity are diffused are formed to fill the contact holes 28 to 33. Also, like these, the fourth MOS
An electrode 41 is formed on the one conductive layer 22 of the transistor 18.

Reference numeral 42 is the first to third MOS transistors.
Selective oxidization method around 3-5 and around DRAM17
Is a field oxide film formed by. In this example
And when writing data to the DRAM cell 17,
First, in the gate electrode 14 of the third MOS transistor 5,
Power supply voltage V_CCIs applied. Third MOS transistor 5
N⁺Output signal of a decoder (not shown) on the conductive layer 16
Is input, the potential of the conductive layer 16 becomes V_CCbecome.
By this, N^-The potential of the conductive layer 15 is V_CC-V_th(V
_thIs the gate threshold voltage) and the first MOS transistor
Switch 3 turns on and the third MOS transistor 5
Off, N^-The type conductive layer 15 is the first MOS transistor.
Boosted potential V due to capacitive coupling of ₀More
Boosted to high. Therefore, the boosted voltage V₀Voltage drop
The drain layer 9 of the first MOS transistor 3 without
It is applied to the word line WL.

As a result, the boosted voltage V is applied to the gate electrode 21 of the fourth MOS transistor 18 via the word line WL.
₀ is applied. The fourth MOS transistor 18 selected by the bit selection signal from the bit line BL is turned on, the capacitor 19 connected to the fourth MOS transistor 18 accumulates charges, and data is written in the DRAM cell 17.
When the boosted voltage V ₀ higher than the power supply voltage V _CC is applied to the drain layer 8 of the first MOS transistor 3, the first MO transistor 3
The gate electrode 7 of the S-transistor 3 is boosted by capacitive coupling and has a potential of about twice V ₀ . Therefore, the double boosted voltage is also applied to the N ^{− type} conductive layer 15 of the third MOS transistor 5. However, the conductivity type 15 of the third MOS transistor 5 is reduced in concentration to N
^Since it is a negative type, it has a high breakdown voltage with respect to the semiconductor substrate 1.

Moreover, since the N ^-- type conductive layer 15 is composed of a layer having a low concentration and not a conductive layer having a high concentration, the area of the element does not increase. Moreover, N ^- and type conductive layer 15 of the electrode 38 of polycrystalline silicon comprising the polar impurities the N ^- because it formed on the conductive layer 15, the impurity in the electrode 38 by annealing N ^- type The contact resistance can be reduced by shallowly diffusing into the conductive layer 15.

FIG. 4 is a graph showing the relationship between the dose of polycrystalline silicon and the contact resistance between the electrode 38 and the N ^--type conductive layer 15. In the figure, the vertical axis represents the resistance on the log scale, and the horizontal axis represents the dose amount on the log scale. FIG.
Has a thickness of the polycrystalline silicon electrode 38 of 2000 Å, N ⁻
The contact resistance is obtained when the impurity dose amount of the type conductive layer 15 is 1 × 10 ¹³ / cm ^{2 and} the polycrystalline silicon dose amount is 1 × 10 ¹⁵ / cm ² or more. It turns out that is very small.

FIGS. 5 and 6 are enlarged views showing the essential parts of the first embodiment of the high breakdown voltage MOS transistor. In this embodiment, the N ⁺ -type conductive layer 16 is LDD as shown in FIG.
It has a structure and is composed of an N ⁺ type portion 16 ₁ and an N ⁻ type portion 16 ₂ . The impurity concentration of the N ⁺ -type portion 16 ₁ N ^- is greater than the mold section 16 _2, N ^- impurity concentration of the mold portion 16 ₂ N ^- type conductive layer 15 to be substantially the same. Further, as shown in FIG. 6, N ^- Part 16
₂ partially overlaps with the gate electrode 14.

The dose of P ions in the N ^--type conductive layer 15 is 1 × 10 ³ / cm ² , the thickness of the polycrystalline silicon electrode 38 is 2000 Å, and the dose of P ions in polycrystalline silicon is 1 ×. Under the condition of 10 ¹⁵ / cm ² and the distance D between the gate electrode 14 and the contact hole 29 shown in FIG. 5 of 1 μm, the breakdown voltage of 20 V could be secured in the drain of the MOS transistor.

Next, taking the formation method of the first and third MOS transistors 3 and 5 as an example, the low concentration drain layer 1 is formed.
An example of a method of manufacturing a semiconductor device having the semiconductor layer 5 and the high-concentration source layer 16 will be described. First, a first embodiment of the semiconductor device manufacturing method according to the present invention will be described. As shown in FIG. 7A, after forming the field oxide film 42 by the LOCOS method around the first and third transistor formation regions T ₁ and T ₂ of the semiconductor substrate 1, the gate oxide films 6 and 13 are heated. It is formed by an oxidation method. After that, a polycrystalline silicon film containing impurities is formed and patterned by a photolithography method, and a gate made of polycrystalline silicon is formed in the center of each transistor formation region T ₁ , T ₂ via gate oxide films 6, 13. The electrodes 7 and 14 are formed.

Then, N-type impurity ions such as P are implanted and diffused on both sides of the gate electrodes 7 and 14 in a self-aligned manner to form a low-concentration conductive layer 43. The impurity dose amount in this case is 10 ¹³ to 10 ¹⁴ / cm ² , and the N ^{− type} conductive layer 4
3 is formed. After that, as shown in FIG.
The SiO ₂ film 44 is formed on the entire surface by the D method to a thickness of about 1000Å. Further, if one conductive layer 43 in the third transistor formation region T ₂ and its surroundings are covered with a resist 45 and the SiO ₂ film 44 is selectively removed by the reactive ion etching (RIE) method, it is covered with the resist 45. The remaining portion of the SiO ₂ film 44 remains, and the sidewalls 46 of the remaining SiO ₂ film 44 are formed beside the gate electrodes 7 and 14 as shown in FIG. 7C.

Next, using the SiO ₂ film 44 and the sidewall 46 as a mask, arsenic (As) ions are added to the semiconductor substrate 1.
Then, a high concentration layer of about 10 ²⁰ / cm ³ is formed in a region not covered with the SiO ₂ film 44, and the conductive layer 43 has an LDD structure. In this case, the conductive layer 43 covered with the SiO ₂ film 44 is kept in a low concentration state as shown in FIG. 7D.

After that, as shown in FIG.
An O ₂ film 47 is formed, and the SiO ₂ film 47 and the SiO ₂ film 44 are patterned by a photolithography method to form a contact hole 28 as shown in FIG. 8B.
To 31 are formed on the conductive layer 43.

Next, after a polycrystalline silicon film 49 having a thickness of about 2000 Å is formed on the entire surface, P ions are added at 1 × 10 5.
Implant at a dose of ¹⁵ / cm ² . Further, the polycrystalline silicon film 49 is selectively etched by the photolithography method, and as shown in FIG.
The polycrystalline silicon film 49 is left in the first region.

In this state, the conductive layer 43 formed in the first transistor formation region T ₁ has an LDD structure, one of which constitutes the drain layer 8 shown in FIG. 3 and the other of which constitutes the source layer 9. Further, among the conductive layers 43 formed in the third transistor formation region T ₂ , the one covered with the SiO ₂ film 44 and having a low concentration is the N ^{− type} conductive layer 1.
5 and the other forms a conductive layer 16 having an LDD structure. Further, the polycrystalline silicon film 49 left in the contact holes 28 to 31 is used as the electrodes 35 to 38.

In the subsequent heating process such as thermal oxidation or annealing, the electrodes 35 to 38 are heated, and the impurities contained therein are contained in the source layer 9, the drain layer 8 and the conductive layer 15,
16 and these electrodes and electrodes 35-38 due to shallow diffusion to
The contact resistance with

Therefore, the boosted voltage V₀Higher voltage than
The one conductive layer 15 of the third MOS transistor 5
N^-Type has low contact resistance with the electrode 38
And good contact can be achieved. By the way, the third MOS transistor
N of the transistor 5^-The type conductive layer 15 is made of SiO₂Through the membrane 44
7C, the resist 45 is removed as shown in FIG.
SiO as a mask ₂Patterning the film 44 results in half
SiO remaining on the conductor substrate 1₂Perimeter of membrane 44 is vertical
And a step is formed. Therefore, SiO₂The membrane 44
If it is thick, disconnection of wiring or error during processing may occur in the subsequent process.
Inconvenience such as the occurrence of etching residue may occur.

A second embodiment of the method of manufacturing a semiconductor device according to the present invention, which solves this problem, will be described with reference to FIG. FIG. 9A shows the resist 45 from the process of FIG.
Shows a state in which is removed. Next, as shown in FIG.
When etching the second SiO ₂ film 44b by RIE after laminating the second SiO ₂ film 44b to a thickness of 1000Å on the entire, SiO ₂ remaining on the source layer 15
The side edge of the film 44 becomes gentle as shown in FIG. 9C, and the step coverage is improved. In this case, the sidewalls 46 on both sides of the gate electrodes 7 and 14 are doubly formed, but the thickness thereof is the first and second SiO 2.
_It can be easily controlled by adjusting the film thickness of the _two films 44 and 44b.

After that, the side wall 46 and the SiO ₂
Impurity ions are implanted and diffused using the films 44 and 44b as masks, and the conductive layer 43 of LDD structure and the conductive layer 43 of low concentration coexist as shown in FIG. 9D as in the case of FIG. 7D. . According to the second embodiment of the method of manufacturing a semiconductor device, the second embodiment of the high breakdown voltage MOS transistor according to the present invention is manufactured. FIG. 10 shows an essential part of the second embodiment of the high breakdown voltage MOS transistor. In this embodiment, the N ⁻ type portion 16 ₂ of the N ⁺ type conductive layer 16 is formed under the sidewall 46.

Next, a third embodiment of the high breakdown voltage MOS transistor will be described with reference to FIG. In the figure, those parts which are the same as those corresponding parts in FIG. 3 are designated by the same reference numerals, and a description thereof will be omitted. In this embodiment, FIG. 12 where the distance d ₁ between the contact hole 28 and the gate electrode 14 is set smaller than the distance d ₂ between the contact hole 29 and the gate electrode 14, the distance d ₂ and N The relationship with the breakdown voltage on the ^{− type} conductive layer 15 side is shown. From the figure, it can be seen that the withstand voltage is 20 V when d ₂ is about 0.8 μm or more.

FIG. 13 is a diagram for explaining the fourth and fifth embodiments of the high breakdown voltage MOS transistor. In the figure,
The same parts as those in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. FIG. 13A shows a cross section of the fourth and fifth embodiments,
9B and 9C show the planes of the fourth and fifth embodiments, respectively. As shown in FIG. 13B, in the fourth embodiment, the contact hole 29 is composed of a plurality of holes. On the other hand, FIG.
As shown in (c), in the fifth embodiment, the contact hole 2
9 is composed of a single hole larger than that in the fourth embodiment. In the fifth embodiment, a larger contact area can be obtained than in the fourth embodiment.

When the electrodes 38 and the like are formed of polycrystalline silicon, the manufacturing process can be simplified if they are formed in the same process as the conductive layer of the semiconductor device. Therefore, in the second embodiment of the semiconductor device according to the present invention, the polycrystalline silicon layer forming the electrode 38 is also used as the conductive layer in the DRAM. FIG. 14 shows an essential part of the second embodiment of the semiconductor device. The same parts as those in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. For example, the storage electrode 24 and the electrode 38 of the DRAM may be formed of the same polycrystalline silicon layer, and the bit line BL and the electrode 38 of the DRAM may be formed of the same polycrystalline silicon layer.

In the description of the above embodiments, the example in which the power supply voltage V _CC is directly applied to the memory cell section has been described, but a voltage other than V _CC is applied to the memory cell section by internally stepping down or boosting the voltage. Even in such a case, needless to say, if a high breakdown voltage transistor portion to which a high voltage obtained by boosting the voltage is applied is provided in addition to the memory cell portion, the same configuration and the same effect as the above embodiment can be obtained.

Next, a first embodiment of a method of manufacturing a high voltage MOS transistor will be described with reference to FIG. In FIG.
The same parts as 8 and 8 are denoted by the same reference numerals, and the description thereof will be omitted. In this embodiment, as shown in FIG.
As described with reference to (a), the field oxide film 42 is formed by the LOCOS method, the gate oxide film 13 is formed by the thermal oxidation method, and the polycrystalline silicon film is formed and patterned to form the gate electrode 14. A low-concentration conductive layer 43 is formed by ion implantation.

After that, as shown in FIG.
As described with reference to (c), the resist 45 is formed on the conductive layer 43 on the side to which a high voltage is applied. Ion implantation is performed using the field oxide film 42, the gate electrode 14 and the resist 45 as a mask to form a conductive layer 43 (source layer 16) having an LDD structure.

The formation of the interlayer insulating film, the formation of the contact hole and the formation of the electrode may be performed in the same manner as in FIGS. 7 and 8, and the description thereof will be omitted. Next, a second embodiment of a method of manufacturing a high breakdown voltage MOS transistor will be described with reference to FIG.
7, those parts which are the same as those corresponding parts in FIGS. 7 and 8 are designated by the same reference numerals, and a description thereof will be omitted.

In this embodiment, after the structure shown in FIG. 15A is obtained, the SiO ₂ oxide film 44 is formed on the entire surface and RI is formed.
By etching the SiO ₂ oxide film 44 by the E method, sidewalls 46 are formed on the side surfaces of the gate electrode 14 as shown in FIG. Further, a resist 45 is formed on the conductive layer 43 on the side to which a high voltage is applied. Ion implantation is performed using the field oxide film 42, the sidewalls 46, the gate electrode 14 and the resist 45 as a mask to form a conductive layer 43 (source layer 16) having an LDD structure.

Next, a third embodiment of a method of manufacturing a high voltage MOS transistor will be described with reference to FIG. In FIG.
The same parts as 8 and 8 are designated by the same reference numerals, and the invention is omitted. In this embodiment, the resist 45 shown in FIG.
Instead of this, the SiO ₂ oxide film 44 is used as a part of the mask to form the conductive layer 43 (source layer 16) having the LDD structure.

Next, a fourth embodiment of a method of manufacturing a high voltage MOS transistor will be described with reference to FIG. In FIG.
The same parts as 8 and 8 are denoted by the same reference numerals, and the description thereof will be omitted. In this embodiment, the SiO ₂ oxide film 44 shown in FIG.
Side walls 46 are formed on the side surfaces of the gate electrode 14 when etching is performed by the RIE method. Therefore, LDD
When forming the conductive layer 43 (source layer 16) of the structure,
The sidewalls 46 are also used as part of the mask.

Next, a third embodiment of the semiconductor device manufacturing method according to the present invention will be described with reference to FIG. In FIG.
The same parts as 7 and 8 are designated by the same reference numerals, and the description thereof will be omitted. In this embodiment, as shown in FIG. 19A, after the gate electrode 14 of the high breakdown voltage MOS transistor 5 and the gate electrode 21 of the MOS transistor 18 of the DRAM cell 17 are formed, the SiO ₂ oxide film 44 is formed on the entire surface. . MOS that constitutes a memory cell by photolithography technology
SiO ₂ oxide film 44 on the transistor 18 and on the conductive layer 43 (drain layer 15) of the high breakdown voltage MOS transistor 5.
As shown in FIG. 19B, ion implantation is performed using the SiO ₂ oxide film 44 as a mask, leaving only the above, to form a conductive layer 43 (source layer 16) having an LDD structure. The side wall 46 left on the side surface of the gate electrode 14 when the SiO ₂ oxide film 44 is etched by the RIE method is also used as a part of the mask as in the case of FIG.

Next, a fourth embodiment of the semiconductor device manufacturing method according to the present invention will be described with reference to FIG. In the figure, those parts which are the same as those corresponding parts in FIGS. 3 and 9 are designated by the same reference numerals, and a description thereof will be omitted. In this embodiment, as shown in FIG. 20 (a), SiO ₂
After the oxide film 44 is etched by the RIE method, a SiO ₂ film 44b is further laminated and this SiO ₂ film 44b is deposited by the RIE method.
_{The two} layers 44b are etched. As a result, FIG.
As shown in (b), the side edges of the SiO ₂ oxide film 44 remaining on the conductive layer 43 (source layer 16) and the gate electrode 14 are smoothed, and both sides of the gate electrode 21 are also smoothed. Therefore, it is possible to prevent inconveniences such as disconnection of wiring in the subsequent steps and etching residue during effective processing.

The etching of the oxide film directly exposes the substrate surface to the etching, so that the junction leak is increased due to contamination, surface damage and the like. Therefore, it is desirable not to etch the oxide film in the memory cell portion of the DRAM where a minute leak current may cause deterioration of the characteristics. The third and fourth embodiments of the method for manufacturing a semiconductor device described above require a step of covering the memory cell portion with a resist when etching the SiO ₂ oxide film 44. However, at the same time, since the conductive layer 43 (drain layer 15) of the high breakdown voltage MOS transistor 5 is also covered with the resist, the number of steps is not increased. Note that the conductive layers 22 and 23 in the memory cell portion have the same relatively low impurity concentration as the conductive layer 43 (drain layer 15), but high-concentration ion implantation induces crystal defects and causes junction leakage. This is rather a desirable condition.

In each of the above embodiments, the electrode formed on the low-concentration conductive layer is made of polycrystalline silicon, but amorphous silicon or refractory metal silicide may be used instead of polycrystalline silicon. The refractory metal contained in the refractory metal silicide includes tungsten (W), molybdenum (Mo), tantalum (Ta), titanium (Ti).
Etc. Further, a polycide film in which a refractory metal silicide such as tungsten silicide is laminated on a polycrystalline silicon film may be used as an electrode on the conductive layer. Further, an Al wiring layer may be formed on the electrode made of polycrystalline silicon or polycide, and “AL” in FIG. 1 indicates the Al wiring layer. To form the polycide film, for example, after depositing a refractory metal film having a film thickness of 0.1 μm on a polycrystalline silicon film having a film thickness of 0.1 μm, for example, P ions are applied from above the refractory metal film. It may be implanted at a dose of about 10 ¹⁵ / cm ² .

[0058]

According to the present invention, since the relatively low concentration drain / source region of the high breakdown voltage MOS transistor is directly connected to the drain / source electrode, the MOS transistor can be miniaturized. Since a conductor containing polycrystalline silicon is used for the source electrode, the drain /
This is extremely useful in practice because it can prevent an increase in contact resistance between the source region and the drain / source electrode and realize a high breakdown voltage.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating the principle of a high breakdown voltage MOS transistor used in the present invention.

FIG. 2 is a diagram showing characteristics of a high voltage MOS transistor used in the present invention in comparison with a conventional example.

FIG. 3 is a cross-sectional view and a circuit diagram showing a first embodiment of a semiconductor device according to the present invention.

[FIG. 4] Impurity dose amount of polycrystalline silicon, electrode and N ⁻
It is a figure which shows the relationship with a contact resistance with a type | mold conductive layer.

FIG. 5 is an enlarged cross-sectional view showing a main part of a first embodiment of a high breakdown voltage MOS transistor.

FIG. 6 is an enlarged sectional view showing a main part of a first embodiment of a high breakdown voltage MOS transistor.

FIG. 7 is a cross-sectional view illustrating the first embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view illustrating the first embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 9 is a cross-sectional view illustrating a second embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 10 is a sectional view showing an essential part of a second embodiment of a high breakdown voltage MOS transistor.

FIG. 11 is a sectional view showing an essential part of a third embodiment of a high breakdown voltage MOS transistor.

FIG. 12 is a diagram showing the relationship between the distance d ₂ and the breakdown voltage on the N ⁻ type conductive layer side.

13A and 13B are a sectional view and a plan view of a main part for explaining a fourth and a fifth embodiments of the high breakdown voltage MOS transistor.

FIG. 14 is a sectional view showing an essential part of a second embodiment of a semiconductor device according to the present invention.

FIG. 15 is a first method of manufacturing a high voltage MOS transistor.
It is sectional drawing explaining an Example.

FIG. 16 is a second method of manufacturing a high voltage MOS transistor.
It is sectional drawing explaining an Example.

FIG. 17 is a third method of manufacturing a high voltage MOS transistor.
It is sectional drawing explaining an Example.

FIG. 18 is a fourth method of manufacturing a high voltage MOS transistor.
It is sectional drawing explaining an Example.

FIG. 19 is a sectional view for explaining the third embodiment of the method for manufacturing the semiconductor device according to the present invention.

FIG. 20 is a cross-sectional view illustrating the fourth embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 21 is a circuit diagram showing an example of a boot strap word line drive circuit.

FIG. 22 is a cross-sectional view showing an example of a conventional high breakdown voltage MOS transistor having an LDD structure.

FIG. 23 is a cross-sectional view illustrating an example of a conventional method for manufacturing a high voltage MOS transistor.

FIG. 24 is a cross-sectional view illustrating another example of the conventional method for manufacturing a high breakdown voltage MOS transistor.

[Explanation of symbols]

1 Semiconductor Substrate 2 Boost Circuit 3 First MOS Transistor 4 Second MOS Transistor 5 Third MOS Transistor 6,13 Gate Oxide Film 7,14 Gate Electrode 8 Source Layer 9 Drain Layer 15 N ^- Type Conductive Layer 16 LDD Structure conductive layer 35-38 electrode 44 SiO ₂ film

Claims (8)

[Claims] 1. A semiconductor substrate (1) and an element isolation region (4)
2), a first diffusion region (15) and a second diffusion region (16) of opposite conductivity type to the semiconductor substrate, and a first electrode (38) formed on the first diffusion region. A semiconductor device having a high voltage MOS transistor and a memory cell (18, 19) comprising a second electrode (35) formed on the second diffusion region and a gate electrode (14), The impurity concentration of the first diffusion region (15) is lower than that of the second diffusion region (16), and the impurity concentration of at least the first electrode (38) is higher than that of the first diffusion region (38). Of a conductor (49) containing polycrystalline silicon, a voltage higher than that applied to the second electrode (35) is applied to the first electrode (38), and the high breakdown voltage MOS transistor (5) ) First electrode (3
Another MOS having a gate electrode (7) connected to 8)
A semiconductor device comprising a transistor (3), wherein a boosted voltage (V ₀ ) is applied to one of a source electrode and a drain electrode of the other MOS transistor (3). 2. A plurality of elements are formed on the semiconductor substrate (1), and the conductor (49) containing polycrystalline silicon is the same layer as the conductive layer of at least one element. Semiconductor device. 3. The voltage applied to the node connecting the first electrode (38) of the high voltage MOS transistor (5) and the gate electrode (7) of the other MOS transistor (3) is the voltage ( The semiconductor device according to claim 1, which is higher than V ₀ ). 4. The other of the source electrode and the drain electrode of the other MOS transistor (3) is connected to the word line (WL) of the memory cell (18, 19).
The semiconductor device according to claim 1 or 3. 5. The memory cell (18, 19) comprises one MOS transistor (18) and one capacitor (1).
The semiconductor device according to claim 4, which comprises 9). 6. An M constituting at least a high breakdown voltage MOS transistor (5) and a memory cell on a semiconductor substrate (1).
A method of manufacturing a semiconductor device having an OS transistor (18), comprising selectively forming a field oxide film (4) on a semiconductor substrate (1).
2) and forming a gate oxide film (13, 2) in the region on the semiconductor substrate defined by the field oxide film.
0) and a gate electrode (14, 21) are sequentially formed, and impurity regions (43, 15, 16, 2) of opposite conductivity type to the semiconductor substrate are formed on both sides of the gate electrode by the first ion implantation.
2, 23) and the impurity regions (43, 22, 23) of the MOS transistors constituting the memory cell and one of the impurity regions (43, 15) of the high breakdown voltage MOS transistors are mask layers (45,
44) and a second step using the field oxide film, the gate electrode (14) of the high breakdown voltage MOS transistor and the mask layer as a mask.
Ion implantation is performed to increase the impurity concentration of the other impurity region (43, 16) of the high breakdown voltage MOS transistor higher than the impurity concentration of the one impurity region (43, 15), and at least the one impurity region (43 43, 15) directly forming an electrode (38) made of a conductor (49) containing polycrystalline silicon with an impurity concentration higher than that of the one impurity region (43, 15). Device manufacturing method. 7. In the step of covering with the mask layer (45, 44), the mask layer is formed on the entire surface of the semiconductor substrate (1) and selectively etched to form the gate electrode of the high breakdown voltage MOS transistor. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the sidewall (46) of the mask layer is left on at least the other impurity region (43, 16) on the side surface of (14). 8. In the step of covering with the mask layer (45, 44), a second mask layer (44b) is further laminated on the mask layer, and selective etching is performed, so that a side edge portion of the mask layer is formed. , A gate electrode (2) of a MOS transistor that constitutes the sidewall (46) and the memory cell.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the portions on both sides of 1) are made gentle.