JP2000307104A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve characteristics in breakdown strength. SOLUTION: A gate oxide film 10 formed on a semiconductor substrate 1, a selective oxide film 9 which is thicker than the gate oxide film 10, a gate electrode 11 which is so formed as to partially bridge the selective oxide film 9 and as to be formed on the gate oxide film 10, and low-concentration source/ drain regions 13 and 14 and high-concentration source/drain regions 15 and 16 so formed on a substrate surface layer as to adjoin the gate electrode 11, are provided. Here, first impurity regions 13A and 14A of the low-concentration source/drain regions 13 and 14 which are formed at the position of a substrate surface layer receded from the end part of the selective oxide film 9, and second impurity regions 13B and 14B which are so formed as to adjoin the vicinity of the border line between the gate oxide film 10 and the selective oxide film 9 and are lower in concentration than the first impurity regions 13A and 14A, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a high voltage MOS transistor structure and an improved technique of the method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 7 is a sectional view for explaining a basic structure of a conventional semiconductor device.

Reference numeral 51 denotes a semiconductor substrate of one conductivity type, for example, a P-type. On this substrate 51, an element isolation film (not shown) and first and second gate insulating films 52 and 53 are formed. From the first gate insulating film 52 to the second gate insulating film 5
3 is a gate electrode patterned so as to straddle a part of the gate electrode 3. 55 is a low-concentration source / drain region; 56 is a high-concentration source / drain region;
It has a D (Lightly Doped Drain) structure. For convenience, only the drain region side is shown. Further, reference numeral 57 denotes a source / drain electrode contact-connected to the source / drain region 56.

[0004]

The inventor of the present invention has identified the location of the electric field concentration at each voltage Vgs in the semiconductor device by device simulation. As a result, it has been found that different withstand voltage characteristics are exhibited depending on the setting conditions of the concentration distribution of the low concentration source / drain regions 55. That is, as shown in FIGS. 8A and 8B, when the surface concentration of the source / drain region 55 is lower (for example, about 5 × 10 ¹⁶ / cm ³ ), the substrate current Is
ub has two peaks (do) as the voltage Vgs increases.
Double hump structure) (see FIG. 8A). FIG. 8A is a characteristic diagram (Vds = 60 V) showing the substrate current Isub with respect to the voltage Vgs at the above concentration.
(B) is a characteristic diagram showing the current Ids with respect to the voltage Vds.

First, the first peak (1) of the substrate current Isub shown in FIG. 8A occurs when an electric field is generated from the drain region 55 toward the gate electrode 54 when the voltage Vgs <the voltage Vds. Fig. 7
This is the first area (1) shown in FIG.

When voltage Vgs = voltage Vds, there is no potential difference between drain region 55 and gate electrode 54, and substrate current Isub is minimized.

Further, when the voltage Vgs> the voltage Vds, the first carrier shown in FIG.
The resistance of the region (1) becomes smaller, and the voltage applied to the depletion layer in the second region (2) shown in FIG. 7 increases due to the resistance division, and the electric field in the second region (2) shown in FIG. Becomes dominant. Therefore, at this time, the substrate current Isub rises again, and reaches the second peak (2) of the substrate current Isub shown in FIG.

When the concentration distribution of the low-concentration source / drain region 55 is lower, the first peak (1) of the substrate current Isub is low, and the drain breakdown voltage in the region where the voltage Vgs is low is reduced. Effective, but the substrate current I
Since the second peak (2) of sub is relatively high, there is a problem that the withstand voltage is not provided in a region where the voltage Vgs is high.

The source / drain region 55 has a relatively high surface concentration (for example, 1 × 10 ¹⁷ / cm 3).
If it is about ^3), the substrate current Isub, as shown in FIG. 9 (a), can be a single peak where the certain voltage Vgs peak, that the voltage Vgs does not have drain breakdown voltage in a low region problem was there. FIG. 9A is a characteristic diagram (Vds = 60 V) showing the substrate current Isub with respect to the voltage Vgs at the above concentration, and FIG. 9B is a characteristic diagram showing the current Ids with respect to the voltage Vds. When the low-concentration source / drain region 55 has a lower concentration, the low-concentration source / drain region 55 has no withstand voltage in a region where the voltage Vgs is high (see region (I) in FIG. 8B). When the drain region 55 has a relatively high concentration, there is no withstand voltage in the region where the voltage Vgs is low (FIG. 9).
(See region (b) in (b)).

Accordingly, it is an object of the present invention to provide a semiconductor device which optimizes the concentration distribution of a low-concentration source / drain region in accordance with the above-mentioned electric field concentration place at each voltage Vgs, and a method of manufacturing the same. .

[0011]

Accordingly, in the semiconductor device according to the present invention, as shown in FIG. 6, a gate oxide film 10 formed on a semiconductor substrate 1 and a gate oxide film 10 having a larger thickness than the gate oxide film 10 are selected. An oxide film 9; a gate electrode 11 formed on the gate oxide film 10 and partially formed on the selective oxide film 9; and a gate electrode 11 formed on the surface of the substrate so as to be adjacent to the gate electrode 11. The low concentration source / drain regions 13 and 14 and the high concentration source / drain regions 15
16, wherein the low-concentration source / drain regions 13 and 14 are formed in the first impurity region 1 formed at a substrate surface position receded from an end of the selective oxide film 9.
3A, 14A, the gate oxide film 10 and the selective oxide film 9
And the second impurity regions 13B and 14B having a lower concentration than the first impurity regions 13A and 14A.

Then, as shown in FIG. 1, the first impurity is ion-implanted into the surface layer of the semiconductor substrate using the first resist film 3 as a mask, as shown in FIG. Using 5 as a mask, a second impurity is ion-implanted and diffused into the surface layer of the substrate. Next, as shown in FIG. 3, the surface of the substrate is thermally oxidized using a silicon nitride film 8 having an opening formed on the substrate 1 as a mask to form a selective oxide film 9 on the substrate 1, and thereafter, as shown in FIG. The gate oxide film 1 is thermally oxidized on the substrate surface except for the selective oxide film 9 as shown in FIG.
0 is formed. Subsequently, after forming a conductive film on the entire surface,
This conductive film is patterned so that the gate electrode 11 extends from the gate oxide film 10 to a part of the selective oxide film 9.
To form Further, the selective oxide film 9 and the gate electrode 1
After the third impurity is ion-implanted into the surface of the substrate using the mask 1 as a mask, the first, second and third impurities ion-implanted into the surface of the substrate are subjected to annealing as shown in FIG. The diffused low-concentration source / drain regions 13A, 14A and 13B, 14B having the first and second impurity concentration distributions and the high-concentration source / drain regions 15, 16 having the third impurity concentration distribution are formed. Forming step.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings.

In FIG. 6, reference numeral 1 denotes a semiconductor substrate of one conductivity type, for example, a P-type (concentration: about 3 × 10 ¹⁴ / cm ³ ), and an element isolation film (not shown) 9) and a gate oxide film 10 is formed, and 11 is a gate electrode formed by patterning on the gate oxide film 10. Reference numerals 13 and 14 denote low-concentration source / drain regions, and 15 and 16 denote high-concentration source / drain regions, which constitute a semiconductor device (MOS transistor) having an LDD (Lightly Doped Drain) structure.

A feature of the present invention is that the low-concentration source / drain regions 13 and 14 are formed in first impurity regions 13A and 14A formed at substrate surface positions receding from the ends of the selective oxide film 9. And second impurity regions 13B, 14B formed adjacent to the boundary between gate oxide film 10 and selective oxide film 9 and having a lower concentration than first impurity regions 13A, 14A. With this configuration, the low-concentration source / drain regions are formed corresponding to the electric field concentration locations at each voltage Vgs, so that various withstand voltages can be handled. That is, the first region (1) of the related art (FIG. 7) is formed by the low-concentration second impurity regions 13B and 14B (surface concentration: about 5 × 10 ¹⁶ / cm ³ ) to reduce the Vg.
s withstand voltage, and the second region (2) has a lower concentration of the first impurity region 1 higher than the second impurity regions 13B and 14B.
3A, 14A (surface concentration: about 1 × 10 ¹⁷ / cm ³ )
And has a high Vgs breakdown voltage.

More specifically, the first impurity regions 13A, 1
The diffusion depth Xj of 4A is about 1.5 μm,
By setting the diffusion depth Xj of the impurity regions 13B and 14B to about 0.5 μm,
B, 14B can realize a surface relaxation type (resurf) structure, and can have high withstand voltage characteristics. Such a resurf technique is disclosed in Japanese Patent Application Laid-Open No. 9-139438.

Hereinafter, a method for manufacturing the semiconductor device will be described.

First, in FIG. 1, the substrate 1 (concentration:
After forming the dummy oxide film 2 on about 3 × 10 ¹⁴ / cm ³ ), the first resist film (the first impurity region 13
A first impurity (for example, phosphorus ions or arsenic ions) may be ion-implanted using the masks 3 (for forming A and 14A) 3 to form a first ion-implanted layer 4. In this step, for example, phosphorus ions are implanted at an acceleration voltage of about 100 KeV and an implantation amount of 5 × 10 ¹² / cm ² .

As shown in FIG. 2, the second resist film 5 (for forming the second impurity regions 13B and 14B) is used as a mask to form a second impurity (for example, arsenic ion,
Phosphorus ions may be used. ) Is ion-implanted to form a second ion-implanted layer 6. In this step, for example, arsenic ions are accelerated to about 2 × 10 ¹² / cm 2 at an acceleration voltage of about 160 KeV.
Ion implantation is performed with an implantation amount of ² .

Next, as shown in FIG. 3, the surface of the substrate is thermally oxidized using a silicon nitride film 8 having an opening formed on the pad oxide film 7 on the substrate 1 as a mask to selectively oxidize the substrate 1. A film 9 and an element isolation film are formed. Before the heat treatment, a diffusion step for forming a low-concentration layer is performed, and the first and second ion-implanted layers 4 and 6 are diffused into the substrate to form the first and second ion-implanted layers.
And the second ion-implanted layers 4A and 6A (low-concentration source / drain regions 13 and 14 described later).

Further, as shown in FIG. 4, the surface of the substrate is thermally oxidized to form a gate oxide film 1 on the substrate region other than the selective oxide film 9.
0 is formed. Subsequently, a conductive film (for example, a phosphorus-doped polysilicon film or a laminated film including the polysilicon film and a tungsten silicide film may be formed) on the entire surface, and then the conductive film is patterned to form the gate oxide film 10. Then, a gate electrode 11 is formed so as to extend over a part of the selective oxide film 9. Further, a third impurity (for example, arsenic ion or phosphorus ion) may be ion-implanted into the surface of the substrate using the selective oxide film 9 and the gate electrode 11 as a mask to form a third ion-implanted layer 12. In this step, for example, arsenic ions are implanted at an acceleration voltage of about 80 KeV and an implantation amount of 6 × 10 ¹⁵ / cm ² .

Thereafter, as shown in FIG. 5, the first and the first ions implanted into the surface layer of the substrate are subjected to an annealing treatment.
The low-concentration source / drain region 13 having the first and second impurity concentration distributions by diffusing the second and third impurities.
A, 14A (surface concentration: about 1 × 10 ¹⁷ cm ³ ) and 13B, 14B (surface concentration: about 5 × 10 ¹⁶ / c)
m ³ ) and high-concentration source / drain regions 15 and 16 having a third impurity concentration distribution (concentration: approximately 5 × 10 ²⁰
/ Cm ³ ).

Then, as shown in FIG. 6, source / drain electrodes 17 and 18 are formed to be in contact with the high-concentration source / drain regions 15 and 16 via an interlayer insulating film (not shown) formed on the entire surface to form a semiconductor. The device is completed.

As described above, in the present invention, each voltage V
gs corresponding to the location of the electric field concentration.
The formation of the drain regions 13 and 14 can cope with various breakdown voltages. Incidentally, the withstand voltage, which was about 80 V in the conventional configuration, could be increased to about 95 V in the configuration of the present invention.

In the description of the present embodiment, an N-channel MOS is formed on a P-type semiconductor layer (substrate or well region, etc.).
Although an example in which a transistor is formed has been introduced, the same applies to the case where a P-channel MOS transistor is formed on an N-type semiconductor layer (substrate or well region or the like) substrate.

Further, in the description of the present embodiment, the gate electrode 1 is formed on both sides of the source / drain region via the selective oxide film 9.
1 but one (for example, on the drain region side)
The gate electrode 11 may be formed only through the selective oxide film 9.

[0027]

According to the present invention, the low-concentration source / drain regions are composed of the first impurity region and the second impurity region corresponding to the electric field concentration place at each voltage Vgs, so that various withstand voltages can be obtained. Can respond to. Further, by adopting the resurf structure, it is possible to further increase the breakdown voltage.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a sectional view showing a conventional semiconductor device.

FIG. 8 is a diagram for explaining a conventional problem.

FIG. 9 is a diagram for explaining a conventional problem.

Claims (5)

[Claims] A first insulating film formed on the semiconductor substrate; a second insulating film having a thickness greater than the first insulating film; and a second insulating film formed on the first insulating film; A source electrode having an LDD structure including a gate electrode formed so as to partially extend over the second insulating film and a low-concentration and high-concentration impurity region formed on a surface layer of the substrate adjacent to the gate electrode.
A semiconductor device having a drain region, wherein the low-concentration source / drain region is formed in a first impurity region formed at a substrate surface position receded from an end of the second insulating film; A semiconductor device formed so as to be adjacent to a boundary line between a film and a second insulating film and comprising a second impurity region having a lower concentration than the first impurity region. 2. The semiconductor according to claim 1, wherein said second impurity region formed below said second insulating film is formed shallower than said first impurity region. apparatus. 3. A step of ion-implanting a first impurity into a surface layer of a semiconductor substrate using a first resist film as a mask, and a step of ion-implanting a second impurity into a surface layer of the substrate using a second resist film as a mask. Forming an oxidation-resistant film having an opening on the substrate, and thermally oxidizing the substrate surface using the oxidation-resistant film as a mask to form a selective oxidation film on the substrate; and thermally oxidizing the substrate surface. Forming a gate oxide film in a substrate region other than the selective oxide film, and forming a conductive film on the entire surface and patterning the conductive film so as to extend from the gate oxide film to a part of the selective oxide film. A step of forming a gate electrode on the substrate; a step of ion-implanting a third impurity into a substrate surface layer using the selective oxide film and the gate electrode as a mask; A low-concentration source / drain region having first and second impurity concentration distributions by diffusing first, second and third impurities; and a high-concentration source / drain region having a third impurity concentration distribution. Forming a semiconductor device. 4. The low-concentration source / drain region comprises:
A first impurity region formed at a substrate surface position receded from an end of the second insulating film;
4. The semiconductor according to claim 3, wherein the semiconductor is formed so as to be adjacent to a vicinity of a boundary with the insulating film, and is formed of a second impurity region having a lower concentration than the first impurity region. Device manufacturing method. 5. The semiconductor device according to claim 3, wherein the second impurity region formed below the second insulating film is formed shallower than the first impurity region. 13. The method for manufacturing a semiconductor device according to item 5.