JPH0651812A - Programmable controller - Google Patents

Abstract

PURPOSE:To shorten scan time by reducing the amount of a user program and labor at the time of programming. CONSTITUTION:When a table registering instruction in the user program is executed, a main processing part 1 copies a look-up table, which stores plural comparative values stored in a RAM 13 and the addresses of a sub routine program while making them correspondent, to a DP-RAM 25 of a sub processing part 2 and informs the copy and next, when a comparing instruction is executed, a comparing request is transmitted to the sub processing part 2. At the sub processing part 2, normal processing is interrupted by interruption processing, and the input value from an input i/f 24 is compared with each comparative value in the look-up table. When they are coincident, the address of the sub routine corresponding to the relevant comparative value is stored in the DP- RAM 25, and a sub routine executing request is transmitted to the main processing part 1. The main processing part 1 branches the request to the sub routine by the interruption processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller (hereinafter referred to as PC) which executes a user program in which a plurality of comparison processes are incorporated.

[0002]

2. Description of the Related Art Conventionally, in a PC, when a user program is being executed and an input value and a counter value are compared with each other and conditional processing based on the comparison result is executed, a comparison instruction or a subroutine program branch instruction is executed. And relay contacts are combined in the user program.

[0003]

However, in such a conventional PC, when an application including a large number of comparison conditions is executed, a user program is combined with a comparison instruction or a subroutine branch instruction for all the comparison conditions. Since it has to be programmed, there is a problem in that the amount of user programs increases and the effort of programming increases.

Further, since all instructions are always executed for each scan, this causes an increase in scan time. Further, since the input value and the comparison value are compared in the scan processing, if the scan time becomes long, There is a problem that an accurate response may not be obtained.

Therefore, an object of the present invention is to provide a PC which can shorten the scan time by reducing the amount of the user program and the labor at the time of programming.

[0006]

In order to achieve the above object, in the invention according to claim 1, an address of a subroutine program to be executed when an input value and a plurality of comparison values match, and the plurality of comparison values. A main processing unit having a table memory storing a look-up table stored in correspondence with each other, a program memory storing a user program incorporating a table registration command and a comparison start command, and a program memory storing the above subroutine program. And a sub processing unit having a dual port memory connected to the main processing unit and an input interface for receiving an input value. The main processing unit executes the table registration command in the user program to execute the sub processing. The above lookup table is stored in the dual port memory of the processing unit. When a comparison request is transmitted to the sub processing unit by executing the comparison start instruction in the user program, and a subroutine execution request is received from the sub processing unit, it is stored in the dual port memory by interrupt processing. When the sub-processing unit executes the subroutine program of the address, and the sub-processing unit receives the comparison request from the main processing unit, the lookup value stored in the dual port memory and the input value taken from the input interface by the interrupt processing are executed. Compare a plurality of comparison values in the table, and if the input value and the comparison value match, store the address of the subroutine program corresponding to the comparison value in the dual port memory,
It is characterized in that an execution request of the subroutine program is transmitted to the main processing unit.

According to another aspect of the present invention, a lookup table is stored in which the address of the subroutine program to be executed when the input value and the plurality of comparison values match and the plurality of comparison values are stored in correspondence with each other. Table memory, a program memory storing a user program in which a table registration command and a comparison start command are incorporated, and a main processing unit having a program memory storing the above subroutine program, and a dual port memory connected to the main processing unit. , And a sub-processing unit that has a hard counter that compares the input value that has counted the input pulse with a preset comparison value and outputs if the two values match. By executing the table registration command in the program, the dual port of the sub processing unit The lookup table is stored in the memory, the comparison request is transmitted to the sub processing unit by executing the comparison start instruction in the user program, and when the subroutine execution request is received from the sub processing unit, the interrupt processing is performed. When the sub-processing unit executes the subroutine program of the address stored in the dual-port memory, and the sub-processing unit receives a comparison request from the main processing unit, the sub-processing unit compares the input value and the comparison value to the hard counter by interrupt processing. If both values match and there is an output from the hardware counter, the address of the subroutine program corresponding to the comparison value is stored in the dual port memory by interrupt processing, and the execution request of the subroutine program is issued. It is sent to the main processing unit above and is stored in the dual port memory. From 憶 look-up table reads the next comparison value and setting the hard counters.

According to another aspect of the present invention, a hard counter for comparing an input value obtained by counting the input pulse with a preset comparison value and outputting when both values match, the input value and a plurality of input values are output. A table memory storing a look-up table in which the address of the subroutine program to be executed when the comparison values match and the plurality of comparison values are stored, and a user program in which a comparison start instruction is incorporated are stored. And a program memory storing the above subroutine program. By executing a comparison start instruction in the above user program, the hardware counter is caused to execute a comparison process between the input value and the comparison value. If the values match and there is an output from the hard counter, the look-up of the above table memory is performed by the interrupt processing. The address of the subroutine program corresponding to the comparison value is read from the lookup table, the subroutine program of the address stored in the program memory is executed, and the next comparison value is read from the lookup table to the hard counter. It is characterized by setting.

[0009]

According to the first aspect of the present invention, the main processing section stores the lookup table in the dual port memory of the sub processing section by executing the table registration instruction, and issues a comparison request to the sub processing section by executing the comparison start instruction. Send. In response to the request, the sub processing unit compares the input value taken from the input interface by the interrupt processing with the plurality of comparison values in the lookup table stored in the dual port memory, and the input value and the comparison value match. In this case, the address of the subroutine program corresponding to the comparison value is stored in the dual port memory, and the subroutine execution request is transmitted to the main processing unit. The main processing unit executes the subroutine program of the address stored in the dual port memory in response to the subroutine execution request from the sub processing unit.

According to a second aspect of the present invention, in the above-mentioned first aspect of the invention, when the sub processing unit performs interrupt processing in response to a comparison request from the main processing unit, the hard counter compares the input pulse with the input value counted. Compare with the value,
If the two values match, the address of the subroutine program corresponding to the comparison value is stored in the dual port memory by interrupt processing, the subroutine execution request is sent to the main processing unit, and the next comparison value is sent from the lookup table. Read and set in hard counter.

According to the third aspect of the present invention, by executing the comparison start instruction in the user program, the hardware counter is caused to execute the comparison processing between the input value and the comparison value. The address of the subroutine program corresponding to the comparison value is read and the subroutine program at that address is executed, and the next comparison value is read from the lookup table and set in the hard counter.

[0012]

Embodiments of the PC according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the PC, P
In C, a main processing unit 1 and a sub processing unit 2 are configured via a CPU bus interface (i / f) 3.

The main processing section 1 includes an MPU 11 and a ROM 1
2 and RAM13, and ROM12 has MP
A system program and a subroutine program for operating U11 are stored, and a user program to be executed by the main processing unit 1 is read from a magnetic storage device (not shown) or the like and stored in the RAM 13. As will be described later in detail, a look-up table (see FIG. 2) in which the address of the subroutine program to be executed when a plurality of comparison values match the input value and the plurality of comparison values are set is stored. Has been done. The RAM 13 also works as a work area for the MPU 11. It should be noted that the user program of the main processing unit 1 incorporates one table registration command and one comparison command, as will be described later.

The sub processing unit 2 includes an MPU 21 and a ROM 2
2, a RAM 23, an input interface 24, and a dual port memory (DP-RAM) 25, and is connected to the internal bus i / f of the main processing unit 1 via the dual port memory 25 and the CPU bus i / f3. . R
The OM 22 stores a system program and a subroutine program of the MPU 21, and the RAM 23 stores a user program to be executed by the sub processing unit read from a magnetic storage device (not shown) or the like. Further, the RAM 23 functions as a work area of the MPU 21, and the input i / f 24 takes in input data from an I / O (not shown) as an input value. Unlike the main processing unit 1, this user program does not include a table registration command or comparison command.

FIG. 2 shows an example of the look-up table 4 stored in advance in the RAM 13 of the main processing section 1. The lookup table 4 is created in advance by the user and has a plurality of comparison values 1 to be compared with the input value.
, And the addresses A, B, C, ... Of the subroutine program to be executed when the input value and the comparison value 1, 2, 3 ,. There is.

Next, the operation of this embodiment will be described with reference to FIG.

FIG. 3 shows the operation of the main processor 1 and the sub processor 2 of this embodiment.

The main processing section 1 and the sub processing section 2 execute their respective user programs, and the main processing section 1
When normal commands other than table registration commands and comparison commands (hereinafter referred to as normal commands) are executed, normal processing corresponding to each command, that is, a command is sent to the terminal device to control the terminal device. While the above is performed (step 100 “Yes”, step 110), the sub-processing unit 2 performs the normal processing by executing the normal instruction because the user program has only the normal instruction (step 20).
0).

By the way, when the main processing unit 1 executes the table registration command (step 100 "No", 1
20 "table registration"), the main processing unit 1, RAM1
The lookup table stored in 3 is stored in the CPU bus i
Dual port memory 2 of sub processing unit 2 via / f3
5 is copied (step 130), the MPU 21 of the sub processing unit 2 is notified that the lookup table has been registered (step 110), and then the next instruction is executed.

If the next instruction is a normal instruction, the main processing section 1 performs normal processing (step 100 "Ye").
s ″, 110) and sequentially executes the user program to perform various normal processing. The sub-processing unit 2 continues the normal processing (step 200) up to this point.

On the other hand, when the main processing section 1 executes the comparison command (step 100 "No", 120 "comparison"), the main processing section 1 sends a comparison request to the sub processing section 2 (step 150). In the sub-processing unit 2, when the comparison request is received (step 210 “Yes”),
Then, it is determined whether or not a lookup table is registered in the dual port memory 25 (step 22).
0).

If the look-up table is not registered (step 220 "No"), the normal processing (step 200) is continued as it is, but in this case, the look-up table registration is notified (step 14).
0), since the look-up table is registered in the dual port memory 25 by the main processing unit 1 in step 130 (step 220), the sub processing unit 2 interrupts the normal processing by the interrupt processing and starts the comparison processing. (Step 230).

In the comparison processing, the MPU 21 inputs the i / f24.
Input value from all the comparison values in the lookup table 4 (see FIG. 2) registered in the dual port memory 25, and if there is a comparison value that matches the input value (step 240). ), The subroutine No. stored corresponding to the comparison value, that is, the address of the subroutine program to be executed when they match is stored in an arbitrary address of the dual port memory 25 (step 2
50), the subroutine execution request is transmitted to the main processing unit 1 together with the arbitrary address (step 260).

By the way, the main processing section 1 executes the next command after transmitting the comparison request in step 150,
1 because the table registration command and comparison command have already been executed
In the scan, normal processing is executed by executing a normal instruction (step 160 “No”, steps 100 and 11).
0).

When the input value and the comparison value do not match as a result of the comparison processing in the sub-processing unit 2, the sub-processing unit 2 does not send a subroutine execution request. Within this scan, the normal processing by the normal instruction execution is continued without performing any comparison processing or subroutine branch processing.

On the other hand, when there is a sub-routine execution request from the sub-processing unit 2 (step 160), the main processing unit 1 interrupts the normal processing by the normal instruction currently being executed by the interrupt processing, and along with the request. Subroutine N from the dual port memory 25 based on the sent address
Then, "o" is read, and the process branches to the subroutine execution process of that subroutine No (step 170). When the branched processing is completed, the main processing unit 1 returns to the original normal processing that has been performed so far and restarts the normal processing.

Therefore, according to the first embodiment, when there are a plurality of comparison processes, a subroutine No corresponding to the plurality of comparison values is registered in the look-up table and a plurality of comparison instructions or subroutine program branches are registered. Since the instructions are combined into one comparison instruction, it is possible to reduce the amount of the user program and the labor required for programming the user program.

Further, in the main processing section 1, a plurality of comparison processings are not executed, and in the user processing section 2, a plurality of comparison processings are performed, and as a result of the comparison processings, the input value and the comparison value are compared. Since the branch to the subroutine program is made by interrupt processing only when they match, when the match with the input value is not detected as a result of the comparison, the scan time is almost the same as when the comparison is not performed and the scan time is almost the same. Even if a match with the input value is detected as a result of comparison without affecting, the scan time can be shortened by not requiring time for comparison processing.

In this embodiment, R of the main processing section 1
Register the lookup table in AM13,
Although it has been described that the table registration command is executed to copy to the dual port memory 25 of the sub processing unit 2, the present invention is not limited to this, and the lookup table may be stored in the RAM 23 or the like of the sub processing unit 2 in advance. If
Since it is not necessary to incorporate the table registration instruction in the user program to be executed by the main processing unit 1 and only the comparison instruction is required, the processing for table registration in steps 120 to 140 shown in FIG. It is possible to reduce the amount of user program and the scan time in.

Next, a second embodiment of the present invention will be described.

FIG. 4 shows the configuration of the PC according to the second embodiment.

In the second embodiment, between the MPU 21 and the input i / f 24 in the sub processing unit 2 of the first embodiment,
The feature is that a hard counter 26 is provided. Therefore, the other constituent elements have almost the same functions as those of the first embodiment shown in FIG. 1, and therefore, the same numbers as those of the first embodiment are given and their explanations are omitted, and the construction of the hard counter 26 is explained. To do.

The hard counter 26 is provided with a compare register having a coincidence output, counts the pulses input through the input i / f 24, sets the count number as an input value in the compare register, and will be described later. The input value is compared with the comparison value set by the MPU 21 from the look-up table, and output is performed when the input value and the comparison value match.

Next, the operation of this embodiment will be described with reference to FIG.

FIG. 5 shows the operation of the main processor 1 and the sub processor 2 of the second embodiment. The operation of the first embodiment shown in FIG. 3 is the sub processor 2 of step 230.
The difference is that the hardware counter 26 performs the comparison processing after receiving the comparison request from the main processing unit 1 in FIG.

That is, in the second embodiment, when the sub-processing unit 2 receives the comparison request from the main processing unit 1 and the table is already registered (step 210 "Yes", 2).
20 “Yes”), the sub-processing unit 2 interrupts the normal processing currently being executed by the interrupt processing, and the hard counter 26
The input value, which is the number of input pulses, is compared with a comparison value preset as described later (step 23).
0).

Here, if the input value and the comparison value match (step 240 "Yes"), the hardware counter 26 outputs, and the subroutine number corresponding to the comparison value is output to the dual port by the interrupt processing. The main processing unit 1 stores the data in the memory 25 (step 250).
To the sub-routine execution request (step 260), and then the MPU 21 sets the next comparison value in the hard counter 26. That is, for example, referring to FIG. 2 and comparison value 2 are set next to comparison value 3 (step 2
70), the interrupt processing is terminated and normal processing is performed (step 20).
Return to 0).

In the case of the first comparison processing, since the comparison value is not set in the hard counter 26, the MPU 21 determines the comparison value based on the current input value set in the hard counter 26 before the comparison processing. The value that is greater than the input value and that is the closest comparison value is the dual port memory 25.
The lookup table stored in the table is searched and set. Then, in step 270, the next comparison value is set as described above by the interrupt processing at the time of coincidence output of the hard counter 26 and repeated until the end of the table. And set it so that when the end of the table is reached, it returns to the comparison value at the beginning. However, if a specific value (for example, "FFFF") is set in the subroutine No corresponding to the comparison value, it is possible to jump to the desired comparison value when updating.

Therefore, according to the second embodiment, as in the first embodiment described above, even if there are a plurality of comparison processes, they are combined into one comparison instruction by using the look-up table, so that the user program amount can be reduced. Also, the time and effort required for programming can be reduced.

Further, the comparison process is performed by the hard counter 26 in the user processing unit 2, and when the compare match output of the hard counter 26 is performed, a subroutine execution request is transmitted to the main processing unit 1 by the interrupt process, and the main processing unit 1 In this case, when the sub-routine execution request is received, the main processing unit 1 does not execute the comparison process or the sub-routine branch process for each scan because the process branches to the sub-routine by the interrupt processing, and the scan time in the main processing unit 1 is reduced. It is shortened.

Also in this embodiment, as in the first embodiment, the lookup table is registered in the RAM 13 of the main processing unit 1 and is copied to the dual port memory 25 by executing the table registration command. However, the present invention is not limited to this, and by storing the lookup table in the RAM 23 or the like of the sub processing unit 2 in advance, the table registration instruction is not required in the user program of the main processing unit 1, and as a result, FIG. Step 120-
The processing of 140 is also unnecessary, and the amount of user programs in the main processing unit 1 and the scan time can be further reduced.

Next, a third embodiment of the present invention will be described.

FIG. 6 shows the configuration of the PC according to the third embodiment. Unlike the first and second embodiments described above, this PC does not use the sub-processing unit and does not perform the main processing. It is configured so as to achieve the object of the present invention with only a part,
The processing is basically the same as that of the second embodiment using the hard counter in the sub processing unit.

That is, the PC according to the third embodiment is M
PU31, ROM32, RAM33, input i / f34,
The MPU 31 controls the entire main processing section, and the ROM 12 has an MPU 31.
A system program and a subroutine program to be executed by 31 are stored, and a user program in which one comparison command is incorporated into the RAM 33 and read from a magnetic file device (not shown), and the first and second embodiments. A lookup table similar to that (see FIG. 2) is stored.

The RAM 33 also functions as a work area for the MPU 31, and the input i / f 34 and the hard counter 36 have the same functions as the input i / f 24 and the hard counter 26 of the second embodiment shown in FIG.

Next, the operation of this embodiment will be described with reference to FIG.

FIG. 7 shows the operation of the PC according to the third embodiment. The PC executes the user program,
In the case of a normal command, a normal process corresponding to the command, that is, a command is sent to the terminal device to control the terminal device (step 300 “Yes”, step 3).
10).

On the other hand, if the comparison instruction is executed while executing the instruction in the user program (step 3
00 "No"), it is judged whether or not the table is registered (step 320), and if not registered, the next instruction is executed without performing the comparison process (step 320).
“No”, 300), in this case, since the lookup table is stored in the RAM 33 in advance (step 3
20 "Yes"), the MPU 31 sends a command to the hard counter 36 to compare the input value, which is the count number of the input pulse, with the comparison value previously set from the look-up table as described later (step 330). ).

Here, when the input value and the comparison value match and there is an output from the hardware counter 36 (step 3
40 “Yes”), the PC stores the subroutine No. corresponding to the comparison value by the interrupt process in the RAM 33 (Step 350) and executes the subroutine program of the subroutine No (Step 3).
60), and then the second comparison value to the hard counter 36
The setting is performed as in the case of the embodiment (step 270), and the process returns to the normal process (step 300). The procedure for setting the comparison value in the hard counter 36 is the same as that in the second embodiment, and the next comparison value is set only when the input value and the comparison value match.

Therefore, according to the third embodiment, as in the first and second embodiments described above, the amount of user program and the labor required for programming can be reduced, and the comparison process can be performed during the user program. Instead, the hardware counter 36 performs interrupt processing, and when the hardware counter 36 outputs a compare match, the subroutine is executed by interrupt processing. Therefore, the PC does not perform comparison processing or subroutine branch processing every scan. Scan time in PC is shortened.

[0052]

As described above, according to the first aspect of the present invention, when there are a plurality of comparison processes, the subroutine program to be executed when the input value and the comparison value match in the lookup table. Since the addresses are registered in association with the plurality of comparison values and the plurality of comparison instructions and the subroutine program branch instructions are combined into one comparison instruction, the amount of user program and the time and effort for creating the user program can be reduced.

Further, the main processing unit does not execute the comparison process, but the user processing unit performs the comparison process so that the subroutine program is executed by the interrupt process only when the input value and the comparison value match. Therefore, the scan time can be shortened without requiring the time for comparison processing.

According to the invention described in claim 2,
Similar to the invention described above, even when there are a plurality of comparison processes, by combining them into one comparison instruction using a look-up table, it is possible to reduce the amount of user program and labor at the time of programming, and to perform the comparison process. The sub-processing unit sends a subroutine execution request to the main processing unit when the hard counter in the user processing unit outputs a compare match output from the hard counter. The main processing unit receives the sub-routine execution request and executes a subroutine by interrupt processing. To run
The main processing unit does not execute the comparison process every scan, and the scan time in the main processing unit is shortened.

According to the third aspect of the present invention, as in the first and second aspects of the present invention, it is possible to reduce the amount of user program and the time and effort required for programming, and at the same time, perform hardware processing by interrupt processing. By using the compare match output of the counter, the comparison process is not executed every scan, and the process branches to the subroutine program by the interrupt process only when the input value and the comparison value match, so that the scan time in the PC is shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of a PC according to the present invention.

FIG. 2 is an explanatory diagram showing a lookup table.

FIG. 3 is a flowchart showing the operation of the first embodiment.

FIG. 4 is a block diagram showing the configuration of a second embodiment.

FIG. 5 is a flowchart showing the operation of the second embodiment.

FIG. 6 is a block diagram showing the configuration of a third embodiment.

FIG. 7 is a flowchart showing the operation of the third embodiment.

[Explanation of symbols]

1 Main Processing Unit 2 User Processing Unit 3 Main Processing Unit 4 Lookup Table 12 ROM (Program Memory) 13 RAM (User Program Memory, Table Memory) 24 Input Interface (i / f) 25 Dual Port Memory (DP-RAM) 26 Hard counter

Claims (3)

[Claims] 1. A table memory storing a look-up table in which an address of a subroutine program to be executed when an input value and a plurality of comparison values match and the plurality of comparison values are stored, and table registration. A main processing section having a program memory storing a user program in which an instruction and a comparison start instruction are incorporated, and a program memory storing the above subroutine program; and a dual port memory connected to the main processing section,
And a sub processing unit having an input interface for receiving an input value. The main processing unit stores the lookup table in a dual port memory of the sub processing unit by executing a table registration command in the user program. , When the comparison request is transmitted to the sub processing unit by executing the comparison start instruction in the user program and the subroutine execution request is received from the sub processing unit, the address stored in the dual port memory is processed by the interrupt processing. When the sub-processing unit executes the subroutine program and the comparison request is received from the main processing unit, the sub-processing unit stores a plurality of the input values taken from the input interface by the interrupt processing and the look-up table stored in the dual port memory. Compare with the comparison value of and compare with the input value When the two match, the address of the subroutine program corresponding to the comparison value is stored in the dual port memory, and an execution request of the subroutine program is transmitted to the main processing unit. . 2. A table memory storing a look-up table in which an address of a subroutine program to be executed when the input value and a plurality of comparison values match and the plurality of comparison values are stored, and table registration. A main processing section having a program memory storing a user program in which an instruction and a comparison start instruction are incorporated, and a program memory storing the above subroutine program; and a dual port memory connected to the main processing section,
And a sub-processing unit having a hard counter that compares the input value counted by the input pulse with a preset comparison value and outputs if the two values match, the main processing unit is the user program. The lookup table is stored in the dual port memory of the sub-processing unit by executing the table registration command in the sub-processing unit, and the comparison request is transmitted to the sub-processing unit by executing the comparison start command in the user program. When a subroutine execution request is received from the unit, the subroutine program of the address stored in the dual port memory is executed by interrupt processing, and the sub processing unit receives the comparison request from the main processing unit. Interrupt processing causes the hardware counter to execute a comparison process between the input value and the comparison value, and both values are If there is an output from the hardware counter, the address of the subroutine program corresponding to the comparison value is stored in the dual port memory by the interrupt process, and the execution request of the subroutine program is sent to the main processing unit. A programmable controller, wherein the next comparison value is read from a look-up table stored in the dual port memory and set in a hard counter. 3. A hard counter which compares an input value counted by an input pulse with a preset comparison value and outputs when the two values match, and the input value and a plurality of comparison values match each other. In the case, a table memory storing a look-up table in which the address of the subroutine program to be executed and the plurality of comparison values are stored in correspondence with each other, a user program memory storing a user program in which a comparison start instruction is incorporated, It has a program memory storing the above subroutine program, and by executing the comparison start instruction in the above user program,
When the hard counter is made to perform a comparison process between the input value and the comparison value, and when both values match and there is an output from the hard counter, an interrupt process corresponds to the comparison value from the lookup table of the table memory. Programmable, characterized in that the address of the subroutine program is read, the subroutine program of the address stored in the program memory is executed, and the next comparison value is read from the lookup table and set in the hard counter. ·controller.