KR100382939B1 - Communication control method and apparatus for slave cpu - Google Patents

Abstract

The present invention relates to a technique for enabling a slave CPI to boot and perform a desired operation using a dual port memory in a system in which the host CPI and the slave CPI operate together. In the present invention, the host CPI resets the slave CPI and sets the boot mode of the slave CPI through the dual port memory so that the slave CPI can boot using the dual port memory. A first process of storing; A second step in which the host CPI releases the reset state of the slave CPI, the slave CUI sets a predetermined region of the dual port memory as a boot start address, starts a booting operation, and then starts an application to perform a requested operation; Process; If there is a program code or data to be additionally transmitted from the host CPI in order to continue to perform the required task is achieved by a third process of receiving the program code or data through the dual port memory to perform the task.

Description

COMMUNICATION CONTROL METHOD AND APPARATUS FOR SLAVE CPU}

The present invention relates to a technique for enabling a slave CPI to boot and perform a desired operation using a dual port memory in a system in which a host CPU and a slave CPU operate together. The present invention relates to a slave CPI communication control method and device which enables a slave CPI to perform a desired operation as well as booting using only a dual port memory without using a separate memory.

Parallel processing system using host CPI and Slave CPI is widely used in many fields. In this structure, there are a number of conventional methods in which two CPIs exchange data. Examples include serial communication, shared memory, and dual port memory (e.g., dual port RAM). There is a way to use it.

1 shows a serial communication system according to the prior art, in which a host CPI 11 and a slave CPI 12 each have a flash memory and SRAMs 11A, 11B, and 12A, 12B, and each serial line. It communicates data and control signals through

In the case of such a communication method, since the data is transmitted between the host CPI 11 and the slave CPI 12 through a serial line, the number of transmission lines is significantly reduced compared to the parallel transmission method, but per unit time. The disadvantage is that the amount of information that can be transmitted is small. In addition, since serial communication is performed based on the communication protocol, accurate agreement between the two parties must be made about the transmission speed.

2 illustrates a conventional communication system using a shared memory, in which the host CPI 21 and the slave CPI 22 perform data communication using the flash memory and the SRAMs 23A and 23B which are shared memories. .

In the case of such a communication method, the data transmission rate is much better than that of the serial communication method, but it requires a lot of data transmission lines. In addition, since the flash memory and the SRAMs 23A and 23B cannot be used exclusively by any one of CIF, a certain hardware agreement between the two CFUs 21 and 22 is required. That is, while the host CPI 21 reads / writes the flash memory and the SRAMs 23A and 23B, the slave CPI 22 is not allowed to access, and conversely, the slave CPI 22 The host CPI 21 is not allowed access while the device reads / writes the flash memory and the SRAMs 23A and 23B.

3 shows a conventional communication system using a dual port memory, in which the host CPI 31 and the slave CPI 32 each have a flash memory and SRAMs 31A, 31B and 32A and 32B. The data is communicated via the port memory 33.

4 shows an example in which the two CPIs 31 and 32 communicate through the dual port memory 33. The slave CPU 32 reads the boot code from the flash memory 32A to start booting and starts an application to perform a desired task. In this case, the slave CPU may not need to receive additional data from the host CPU 31. In this case, work alone.

However, if the slave CPI 32 needs to receive additional data from the host CPI 31, it informs the host CPI 31 of the fact. Accordingly, the host CPI 31 stores the requested data in the dual port memory 33 and notifies the slave CPI 32 of the moment when the storage operation is completed. Accordingly, the slave CPI 32 reads data from the dual port memory 33.

In the case of such a communication method, the two CPIs 31 and 32 can communicate data in parallel through the dual port memory 33 as well as operate completely independently. In other words, protocol problems with shared memory do not occur seriously.

In other words, the dual port memory 33 can read / write data arbitrarily through the two ports, so that the two CPIs 31 and 32 can easily exchange data if they have a software agreement with each other. do. For example, half of the memory areas of the dual port memory 33 are used when the host CPI 31 passes data to the slave CPI 32, and the other half of the dual port memory 33 is slave CUI 32 by the host CPI 31. If you agree to use it when handing over data, you can send and receive data without any conflict.

However, in this communication method, since dual port memory (RAM) is additionally used, there is a disadvantage in that a corresponding cost is added.

Accordingly, it is an object of the present invention to provide a method and apparatus for controlling communication of a slave CPI that enables the dual port RAM to be used not only for data communication but also for booting, exchanging program codes, or performing other desired tasks. Is in.

1 is a serial communication block diagram according to the prior art.

2 is a conventional communication block diagram using a shared memory;

3 is a conventional communication block diagram using a dual port memory;

4 is a signal flow diagram of a communication method using a dual port memory in the prior art.

5 is a communication control block diagram of a slave CPU using the dual port memory of the present invention.

6 is a diagram illustrating control signals for booting and exchanging program codes and data in the present invention;

7 is an explanatory diagram of control signal communication for booting and exchanging program code and data in the present invention;

8 is a table showing a boot method according to the boot mode in the present invention.

9 is a signal flowchart of a communication method of a slave CPI in accordance with the present invention;

*** Description of the symbols for the main parts of the drawings ***

51: host CPI 51A: flash memory

51B: SRAM 52: Slave CPI

53: dual port memory

In the communication control method of the slave CPI according to the present invention, the host CPI resets the slave CPI and sets the boot mode of the slave CPI through the dual port memory so that the slave CPI can boot using the dual port memory. And a first step of storing code required for booting; A second step in which the host CPI releases the reset state of the slave CPI, the slave CUI sets a predetermined region of the dual port memory as a boot start address, starts a booting operation, and then starts an application to perform a requested operation; Process; In order to continue to perform the requested work, a third process of checking whether there is a program code or data to be additionally transmitted from the host CPI is performed and receiving the program code or data through the dual port memory to perform a task. Is done.

FIG. 5 is a block diagram showing an embodiment of a slave CPI communication control apparatus according to the present invention. As shown therein, the boot mode is changed through the dual port memory 53 after the slave CPI 52 is reset. A host CPU (51) for storing the code required for booting and transferring the program code or data required during the operation through the dual port memory (53); A flash memory 51A and an SRAM 51B for booting and performing a task of the host CPI 51; The boot code is read from the dual port memory 53 to start booting, the application is started by performing an operation by executing an application, and the necessary program code or data is transferred from the host CPI 51 through the dual port memory 53. A slave CPI 52 received; Transfers various codes or data transmitted from the host CPI 51 to the slave CPI 52, or performs a task of the slave CPI 52 to a dual port memory 53 used as a storage space of a program code. With reference to Figures 5 to 9 attached to the operation of the present invention as described above in detail as follows.

The dual port memory (eg, dual port RAM) 53 is used as a space for storing the boot code and program code for the slave CPI 52 as well as exchanging data between the host CUI 51 and the slave CPI 52. do. Accordingly, the slave CPI 52 may boot using the boot code stored in the dual port memory 53 by the host CPI 51, and the host CFI 51 may control the boot time at this time. Can be. The slave CPI 52 may request a host CFI 51 through the dual port memory 53 for necessary program codes while performing a desired operation after booting.

FIG. 6 shows various control signals used for data exchange between the host CPI 51 and the slave CPI 52, and transmission of boot codes and program codes for the Slave CPI 52. These are general SRAMs. Is the same as the control signal, and common CFI oils use these control signals.

That is, the control signal output from the host CPI 51 to the dual port memory 53 includes a chip select signal CS_N, a write strobe signal WR_N, an out enable signal OE_N, an address signal ADDR, and data. (DATA), and the control signal outputted to the slave CPI 52 side includes a reset signal RESET for inducing booting of the slave CPI 52, a boot mode selection signal (BOOT_MODE), and an interrupt signal (INTR_TO_SLAVE). There is an interrupt signal (INTR_TO_HOST) that the slave CPU 52 outputs to the host CPU 51 side.

Meanwhile, a booting process using the dual port memory 53 and a program code and data exchange process between the two CPIs 51 and 52 will be described with reference to FIGS. 7 and 9 as follows.

The host CPI 51 outputs the reset signal RESET to the slave CPI 52 so that the slave CPI 52 is in the reset state (S1).

Thereafter, the host CPI 51 sets a boot mode by outputting a boot mode selection signal BOOT_MODE to the dual port memory 53 so that the slave CPI 52 can boot using the dual port memory 53. The code required for booting is then stored in the dual port memory 53 (S2, S3).

Subsequently, when the host CPI 51 blocks the reset signal RESET outputted to the slave CPI 52, the reset state of the slave CPI 52 is canceled. The booting operation is started by setting the area of the dual port memory 53 as the boot start address.

For reference, there may be various methods for setting the boot address as the storage area of the dual port memory 53 according to the boot mode of the slave CPU 52. As a representative example, a method of manipulating a memory address during booting may be used. Can be mentioned.

The slave CPI 52 appropriately allocates an area of the dual port memory 53 to a program code area and a data area to perform a booting operation and to start an application. (S5)

When the slave CPI 52 continues to perform a desired task after completing a booting operation, when there is no need to receive additional program code or data from the host CPI 51, the operation is performed by itself. S6, S7)

However, when the slave CPU 52 continues to perform a desired task, if there is a program code or data to be additionally transmitted from the host CPU 51, the host CPU 51 requests the required data. S8)

Accordingly, the host CPI 51 stores the requested code and data DATA in the dual port memory 53 and notifies the slave CPI 32 of the moment the storage operation is completed. S10)

Accordingly, the slave CPI 52 may continue to perform a desired operation by reading a program code or data requested by the slave CPU 52 from the dual port memory 53.

If the slave CPI 52 can predict the necessary code or data in advance, the host CUI may be requested in advance, thereby minimizing a delay time.

8 shows an example of setting a boot memory according to the boot mode input of the slave CPU (52). In other words, 8-bit, 16-bit, and 32-bit external flash memories are used according to the boot modes "00", "01", and "10". In addition, the slave CPU 52 can boot using the dual port memory 53, in which case the boot mode is set to " 11 ". At this time, the bus size of the external flash memory allocated to the slave CPU 52 may be set, or the slave CPU 5 may be inputted through two input pins called “BOOT-MODE” to indicate that the dual port memory 53 is currently in the boot mode. ).

As described in detail above, the present invention does not simply use the dual port RAM for data communication, but may be used to perform booting, exchanging program codes, or performing a desired task. It is possible to reduce the size and to optimize the design area.

Claims (8)

A first step of the host CPI setting the boot mode of the slave CPI using the dual port dual port memory; A second step of the host CPI booting the slave CPI to perform an application task; If there is a program code or data to be additionally transmitted from the host CPI in order to perform the operation communication of the slave CPI, characterized in that the third step of receiving a program code or data through the dual port memory to perform a task Control method. The method of claim 1, wherein the first step comprises the steps of: the host CPI resets the slave CPI; Setting a boot mode of the slave CPI via a dual port memory; And storing the code necessary for booting in the dual port memory. The method of claim 1, wherein the second process is initiated by the host CPI being released from the reset state of the slave CPI. 2. The slave of claim 1, wherein the slave CPI further comprises a step of manipulating a memory address at boot time to set a boot address as a storage area of the dual port memory according to a boot mode. CFIU's communication control method. The method of claim 1, wherein the second process allocates an area of the dual port memory to a program code area and a data area to perform a booting operation. A host CPI 51 which resets the Slave CPI 52 and sets a boot mode of the Slave CAPI 52 through the dual port memory 53 and stores a code necessary for booting; The boot code is read from the dual port memory 53 to start booting, the application is started by performing an operation by executing an application, and the necessary program code or data is transferred from the host CPI 51 through the dual port memory 53. A slave CPI 52 received; Configured as a dual port memory 53 which transmits the boot code or data transmitted from the host CPI 51 to the slave CPI 52 or is used as a program code storage space for the operation of the slave CPI 52. A communication control device of a slave CPI. 7. The slave control device of claim 6, wherein the dual port memory (53) is configured as a dual port RAM. 7. The slave control system of claim 6, wherein the dual port memory (53) is configured to operate by dividing the program code area and the data area.