JPH064687A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To prevent errorneous writing into an important data area so as to prevent the destruction of important data when a single chip microcomputer runs away. CONSTITUTION:A write signal control part 124 is provided for the single chip microcomputer. An area discrimination circuit 151 in which a write inhibition address area is previously set and which usually judges whether a write destination address is a write inhibition area or not at the time of writing into a memory, is provided for the write signal control part. At the time of writing the address discriminated to be the write inhibition area, writing is inhibited by permitting output EQ152 to fix the output of AND 154 to '0' via.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-chip microcomputer, and more particularly to a single-chip microcomputer which controls writing to an address area in which important data is stored to prevent data destruction at the time of computer runaway.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing the configuration of a conventional single-chip microcomputer. The single-chip microcomputer 600 is a central processing unit (CP
U) 610 and micro program storage unit (μROM)
611 and interrupt request control unit (INTC) 6
12, watchdog timer (WDT) 613, W
WDT output terminal (WD which outputs the signal from DT613
TO) 614, reset control unit 615, reset input terminal 616 thereof, input / output unit 618, internal read-on memory (ROM) 619, internal random access memory (RAM) 620, and the interior interconnecting these. And a bus 621. Further, as the memory used in the single-chip microcomputer 600, the above-mentioned R is used.
In addition to the OM 619 and the RAM 620, it can be connected to the outside through the input / output unit 618, but for the sake of simplification of the following description, the description will be limited to the internal memory, but it will be described below. The memory is exactly the same as inside.

Next, the operation will be described. CPU610
Sequentially reads the instruction code of the execution program previously written in the ROM 619 via the bus 621, and executes the instruction operation according to the microflow defined in advance in the μROM 611 according to the instruction code.
Various operation instructions are generally used as instruction operations,
There are various write commands, read commands, transfer commands, bit manipulation commands, etc.
An operation when a write command to 20 is executed will be described as an example. The CPU 610 reads, as an instruction code, a series of instruction codes including a write instruction code, an address, and write data from the ROM 619, and the μRO
According to M611, an address and data are output to the bus 621 at a predetermined timing, and at the same time, a MEMWR signal 622 is output at a predetermined timing to write predetermined data to a predetermined address of the RAM 620.

In addition to the above-mentioned program execution processing, the CPU 610 receives an interrupt signal from the INTC 612,
It also performs a predetermined interrupt processing operation.
In this way, the CPU 610 executes the operation, but due to some factors such as noise from the outside, the instruction code of the address to be originally read cannot be read correctly, and as a result, the program cannot be executed normally and the single-chip microcomputer 600 runs out of control. there is a possibility. As means for avoiding or detecting such a situation, some means are generally taken in a single-chip microcomputer.

One is called an opcode trap function, and FIG. 7 shows an example of the processing flow. C
When the PU 610 reads the instruction code, the μRO is always
It branches to the entry address of M611. Here, the read instruction code is checked to determine whether it is a defined code. If it is determined to be a defined instruction code, the specified μRO according to the instruction code
It branches to the address of M611 and performs processing according to the contents of the branch destination. If it is determined that the instruction code is an undefined instruction code, the routine branches to an operation code trap routine of the μROM 611 and executes a predetermined process such as an interrupt process.

The second means is a watchdog timer function. A configuration diagram of the WDT 613 is shown in FIG. W
The DT 613 is counted in a certain cycle by the internal clock f _CLK , and is reset by the WDTCLR signal output when the CPU 610 executes a special instruction, and the A timer 810 is counted in a certain cycle by the internal clock f _CLK. 810 overflow signal OV
B timer 811 reset by FA 810, A
Overflow signal OVFB811 of B timer 811 set by OVFA 810 output from timer 810
Flip-flop (FF) 812 reset by
And an inverter (IN
V) 813. The OVFA 810 is output to the INTC 612 as an interrupt signal INTWDT 623, and the output signal of the INV 813 is output to the outside via the WDTO output terminal 614.

Next, the operation of the WDT will be described with reference to the timing charts of FIGS. First, FIG. 9 shows a timing chart when the single-chip microcomputer 600 is operating normally. The A timer 810 always counts up with the internal clock f _CLK . The execution program is designed in advance so that if the program is executed in a normal routine, WDTCLR is always issued before the A timer 810 overflows. That is, as long as the program is executed in the normal routine, the A timer 810 is always cleared before overflow, and the FF 812 is not set and the output of the INV 813, that is, WDTO.
The output through the output terminal 614 is always fixed at "1" and the level does not change, and the INTWDT623 signal is "0".
A fixed interrupt does not occur, and the program normally executes according to the original design flow.

Next, the operation when the single-chip microcomputer 600 runs out of control will be described with reference to the timing chart of FIG. If program execution deviates from the normal routine due to some reason
The special instruction for generating the WDTCLR signal, which should be executed at the timing before the timer 810 overflows, is not correctly executed at the originally intended timing, and the A timer 810 eventually overflows to generate the OVFA 810. The OVFA 810 sets the FF 812 and clears the B timer 811 at the same time, and the INTVDT 623
As an interrupt signal to INTC612. FF8
When 12 is set, the output of the FF 812 changes from "0" to "1". Accordingly, the output of the INV 813 that receives the output of the FF 812 changes from "1" to "0", and the value is output to the outside via the WDTO output terminal 614. After the output level of the WDTO output terminal 614 has changed from "1" to "0", the B timer 811 cleared by the OVFA 810 continues to output "0" until the OVFB 811 is output until the B timer 811 counts up with f _CLK. .

B timer 811 overflows and OVF
When B811 is output, FF81 is output by OVFB811.
2 is reset, the output of the FF 812 changes from “1” to “0”, and then the INV 813 changes from “0” to “1” and the level of the WDTO output terminal 614 also changes from “0” to “1”. To do. In this case, as a means for detecting and recovering from the runaway, the interrupt processing by the INTWDT623 interrupt signal is executed, or the WDTO output terminal 614 is connected to the RESET input terminal 616, so that the output of the WDTO output terminal 614 is changed from "1" for a certain period. By changing to "0", an external reset is applied, and by performing a system reset of the entire single-chip microcomputer 600 through the reset control unit 615, normal operation is restored.

[0010]

In such a conventional single-chip microcomputer, the program runaway detection is performed by the operation code trap function when the read instruction is an undefined instruction or as a result of the runaway of the WDT. Judgment is made depending on whether the WDT overflows due to the fact that the clear signal generation instruction is not executed at the correct timing. Therefore, if the instruction code read at the time of runaway is garbled to another instruction code that is tentatively defined, the operation code trap function does not work and the abnormal operation different from the programmed content until the WDT overflows. Will be done.
In particular, if a write command is issued to the RAM or the like connected to the inside or outside of the single-chip microcomputer during this abnormal operation, the data in the RAM may be destroyed, and if the important data is temporarily stored. If it was stored, there was a serious problem that the data became unusable and the reliability of the system deteriorated. An object of the present invention is to provide a single chip microcomputer that prevents data destruction during runaway.

[0011]

According to the present invention, a write-destination address discriminating section is composed of a write-prohibited address area designating section and a discriminating section. If it is in the write-inhibited address area, the write signal from the central processing unit is inhibited and the timer reset signal to the watchdog timer is output.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 to 4 show an embodiment of the present invention. Figure 1
FIG. 1 is a block diagram of a single-chip microcomputer 100, and this single-chip microcomputer 1
00 is CPU 110, μROM 111, INTC
112, WDT 113, a WDTO output terminal 114 for outputting the output signal of the WDT 113 to the outside, a reset control section 115, a RESET input terminal 116, an input / output section 118, a ROM 119, a RAM 120, an internal bus 121, The write control unit 124 controls a write signal from the CPU 110 to the RAM 120.
Incidentally, 117 is an internal reset signal, 122 is the CPU 110.
From the write signal (MEMWR) output from the write control unit 124, 123 is the INTWDT signal, 12
5 is the RAM 120 output from the write control unit 124
Is a write signal to (RAMWR). Further, as the memory used in the single-chip microcomputer, in addition to the ROM 119 and the RAM 120, it can be connected to the outside through the input / output unit 118. However, for simplification of the following description, the internal memory is representatively shown. Although the description will be limited to, the same applies to the externally connected memory.

Next, the operation will be described. CPU110
Sequentially reads the instruction code of the execution program written in advance in the ROM 119 via the bus 121, and executes the instruction operation according to the microflow defined in advance in the μROM 111 according to the instruction code.
Various operation instructions are generally used as instruction operations,
There are various write commands, read commands, transfer commands, bit manipulation commands, etc.
An operation when a write command to 20 is executed will be described as an example. The CPU 110 reads, as an instruction code, a series of instruction codes including a write instruction code, an address, write data, and the like from the ROM 119, and μRO
According to the microprogram of M111, the address and data are output to the bus 121 at a predetermined timing, and at the same time, M and M are output at a predetermined timing.
The EMWR signal 122 is output. If the MEMWR 122 is writable via the write control unit 124, then R
The AMWR 125 is output and the predetermined data is written to the predetermined address of the RAM 120. In addition to the program execution processing described above, the CPU 110 also has the INTC1
The interrupt signal from 12 also performs a predetermined interrupt processing operation.

FIG. 2A shows an internal block diagram of the write controller 124. The write control unit 124 determines an address latch unit 150 that latches the address of the bus 121 according to an address latch signal output by the CPU 110 when the write cycle is activated, and whether the latch address output from the address latch unit 150 is a write enable / disable region. Area determination unit 151 and output EQ of this area determination unit 151
It is composed of an INV 153 that inputs 152, an AND gate (AND) 154 that takes a logical product of the output of the INV 153 and the MEMWR 122, and an AND 155 that takes a logical product of the EQ 152 and the MEMWR 122. Also, A
The output of ND155 is WDT113 as WAWR126.
Is output to.

A detailed block diagram of the area discriminating section 151 is shown in FIG. The area discriminating unit 151 is made up of a total of 3 bits, that is, the EN bit which is the write prohibition designation function enable bit reset by the internal reset 117 is 1 bit and the write inhibit address area which is reset by the internal reset 117 is 2 bits. Address bank setting register 200 and address latch unit 15
A gate (EXNOR) 201 that outputs the inverted output of the exclusive OR of the most significant output of 0 and the first bit of the address bank setting register 200, and the output of the second most significant bit of the address latch unit 150 and the address bank. An EXNOR 202 for outputting an inverted output of an exclusive OR with the 0th bit of the setting register 200, an output of the EXNOR 201 and the EXNOR 202, and an AND of the EN bit output of the address bank setting register 200
And 203. The output of this AND203 is EQ
It is output as 152. Here, writing to the address bank setting register 200 is performed by a special instruction different from a normal write instruction.

FIG. 3 shows a detailed block diagram of the WDT 113. The WDT 113 includes an A timer 310 that counts in a certain fixed cycle by the internal clock f _CLK , and the A timer 310.
A gate (OR) 314 that takes the logical sum of the overflow signal OVFA 310 of the timer 310 and the WAWR 126 that is output from the write control unit 124, and a logical sum of the WDTCLR signal that is output when the CPU 110 executes a special instruction and the OR 314. An OR 315, a B timer 311 which is counted in a constant cycle by the internal clock f _CLK , and is reset by the output signal INTWDT123 of the OR 314; It is composed of an INV 313 which receives the output of the FF 312 as an input. The A timer 310 is reset by the output of the OR 315. Further, the output signal INTWDT123 of the OR 314 is output to the INTC 112 as an interrupt signal, and INVDT
The output signal of 313 is output to the outside via the WDTO output terminal 114.

Next, the operation will be described. First, FIG.
In (b), the area for storing important data that should prevent data destruction during runaway is designated as the address bank setting register 20.
It is specified by the 0th bit and the 1st bit of 0. Now, as an example, the address width is described as an 8-bit 256-byte space, and the space specified by the 0th bit and the 1st bit of the address bank setting register 200 is shown in Table 1 below.
It is divided into four streets.

[Table 1]

In this state, the internal reset 117
The EN bit is initialized to "0" by
Since the output EQ152 of D203 is always "0", the MEMWR signal 122 becomes valid as it is and is output as the RAMWR125 signal regardless of the address area specified according to Table 1, and is output as the RAMWR125 signal. Writing to the area becomes possible. As an example, assume that the write control address space is set to 40H to 7FH according to Table 1. CPU11
It is assumed that 0 performs predetermined processing according to the execution program and writes important data in the address area of 40H to 7FH at a certain point. Immediately after writing the important data, the EN bit is set to "1" by the program.
Set to. After that, if the normal program processing is performed again and it becomes necessary to write again in the area of 40H to 7FH, the EN bit is reset to "0", then writing is performed, and after the writing is completed, the EN bit is set to "1" again. Set to ".

As long as the program proceeds by repeating the above operation, the output EQ152 of the area discriminating circuit 151.
Remains fixed at "0" and does not change. As mentioned above,
If the single chip microcomputer 100 is programmed so that the write command to the write protected address area is not executed when the single chip microcomputer 100 is operating normally, the output WAWR 126 from the write controller 124 remains fixed at "0". Therefore, the level of INTWDT123 which is the output of OR314 in FIG. 3 is OVFA31.
Determined by 0. The A timer 310 always counts up with the internal clock f _{CLK as the} program progresses. The execution program is designed in advance so that if the program is executed in a normal routine, WDTCLR is always issued before the A timer 310 overflows. That is, as long as the program is executed in the normal routine, the A-timer 310 is always cleared by WDTCLR before it overflows. Therefore, INTWDT123 of the output of OR314 is fixed at "0" and FF312 is not set and That is, the output level via the WDTO output terminal 114 is always fixed at "1" and the level does not change, and the program carries out a normal execution operation according to the original design flow. That is, the operation during normal execution of the program is the same as the operation of the conventional example shown in FIG.

Next, the operation at the time of runaway will be described with reference to the timing chart of FIG. It is assumed that the CPU 110 has runaway for some reason while the EN bit is set to "1". At that time, the CPU 110
When the instruction read from the OM 119 is an undefined instruction code, the runaway is detected by the operation code trap as described in the conventional example. However, if the instruction code read at the time of runaway is defined, the operation code trap function does not work. At this time, if a write command is erroneously executed to the write-protected address area, if the area determining unit 151 determines that the address is a write-protected address, the output EQ15 of the area determining unit 151 is output.
2 outputs "1". Then, the INV 153 to which the EQ 152 is input outputs “0” and outputs the write signal RAMWR 125 to the RAM 120 and the AND 154.
ME from the CPU 110 to fix the output of
Since the write signal RAMWR125 to the RAM 120 remains "0" regardless of the level of the MWR signal 122, even if the write command is executed, the RAM 120 is actually
The data is protected without being written to.

Further, when a write command to a write-prohibited address is executed, the output EQ152 of the area discriminating section 151.
ANDWR output of AND155 and MEMWR122
26 becomes "1" and is output to the WDT 113. WAW
When R126 becomes "1", the output of OR314 shown in FIG. 3 is set to "1" and FF312 is set, and at the same time, B timer 311 is cleared and A timer 31 through OR315 is used.
Clear 0 and INTC as INTWDT123
It is output to 112. When the FF312 is set, its output changes from "0" to "1", the INV313 that receives the output of the FF312 changes from "1" to "0", and its level is output to the outside through the WDTO output terminal 114. Then, after a certain period of time, the B timer 311
Overflows and outputs OVFB311, FF3
12 is reset and the output of FF312 is "0" again.
Further, the output of the INV 313, that is, the output level of the WDTO output terminal 114 changes from "0" to "1".

As a means for detecting and recovering from a runaway, interrupt processing by the INTWDT123 interrupt signal is performed as in the conventional example, or WDTO output terminal 114 is set to RESE.
By connecting to the T input terminal 116, the output of the WDTO output terminal 114 changes to “0” for a certain period of time, and an external reset is applied, and an internal reset signal 117 output from the reset control unit 115 causes the entire single chip microcomputer 100 to operate. Perform a system reset of to restore normal operation. In this case, E
The case where the runaway occurs when the N bit is in the "1" state has been described, but when the runaway occurs when the EN bit is in the "0" state, the data in the RAM 120 is naturally not guaranteed. As a method to avoid this, EN
Data can be protected by backing up the data in the RAM 120 when the bit is "1".

A block diagram of the address discrimination circuit 151 in the second embodiment of the present invention is shown in FIG. The address discrimination circuit 151 includes a discrimination operation permission register 510 including a discrimination operation permission bit EN bit which is reset by the internal reset signal 117, and a writing including two bits of 0th bit and 1st bit which are also reset by the internal reset signal 117. Prohibited upper limit address setting register 511
And a write-inhibit lower limit address setting register 512 consisting of 2 bits of 0th bit and 1st bit which are similarly reset by the internal reset signal 117.

Further, a gate (NO) for inverting the logical product of the inverted signal of the first bit output of the upper limit address setting register 511 and the most significant bit output of the address latch 150 section.
R) 513 and the first upper limit address setting register 511
EXNOR 514 which performs exclusive OR inversion of the bit and the most significant bit output of the address latch unit 150, the inversion of the 0th bit of the upper limit address setting register 511, and the output of the upper 2nd bit of the address latch unit 150 EXNOR 516 that takes the exclusive OR of the NOR 515 that takes the product inversion and the 0th bit of the upper limit address setting register and the output of the upper 2nd bit of the address latch unit 150
AND 517 that takes the logical product of the outputs of EXNOR 514 and NOR 515, and EXNOR 514 and EXNOR 5
AND518 which takes the logical product of 16 outputs, and NOR51
3 and AND517, and OR519 which takes the logical sum of each output of AND518.

Further, NOR 520 which takes the logical OR of the inversion signal of the first bit output of the lower limit address setting register 512 and the most significant bit output of the address latch unit 150.
EXNOR 521 that performs an exclusive OR inversion of the first bit of the lower limit address setting register 512 and the most significant bit output of the address latch unit 150, and the output of the 0th bit of the lower limit address setting register 512 and the address latch unit 150. NOR 522 that performs logical OR inversion with the inversion signal of the output of the upper 2nd bit, and lower limit address setting register 5
EXNOR52 which performs exclusive OR inversion of the 0th bit of 12 and the output of the upper 2nd bit of the address latch unit 150
3, AND 524 which takes the logical product of the outputs of EXNOR 521 and NOR 522, EXNOR 521 and EXNOR
AND 525 that takes the logical product of the outputs of 523 and NOR5
OR526 which takes the logical sum of 20 and each output of AND525
And the logical product of the output of the EN bit of the determination operation permission register 510, the output of OR519, and the output of OR526 A
It is composed of ND527. Here, the determination operation permission register 510, the upper limit address setting register 511,
Writing to the lower limit address setting register 512 is performed by a special instruction different from a normal write instruction.

Next, the address discrimination operation will be described.
First, the address discrimination operation is performed by setting the EN bit of the discrimination operation permission register 510 to "1". If the EN bit is "0", then AN
The output level of D527, that is, EQ125 is OR51.
9, fixed to "0" regardless of the value of OR526. If the EN bit is set to "1", the level of EQ125 is determined by the values of OR519 and OR526. Here, as a result of the upper limit address discrimination, the OR 519 becomes “1” if the upper limit setting address is equal to the target address or if the target address is smaller than the upper limit setting address,
Otherwise, it becomes "0". Further, the OR 526 operates so that if the lower limit setting address and the target address are equal to each other or if the target address is larger than the lower limit setting address, the OR 526 becomes "1", and otherwise it becomes "0". Therefore, the value of AND527, that is, the level of EQ125 is EN
If the bit is "1" and the target address is smaller than the upper limit address setting value and larger than the lower limit address setting value, it becomes "1", and otherwise it becomes "0".

Next, the upper limit address determination method will be described. First, in order to determine the size of an address, the addresses are compared in order from the most significant bit. That is, if the most significant bit of the set address is larger than the most significant bit of the target address, it can be determined at this point that the set address is larger than the target address regardless of the size of the address bits below it, and the If the most significant bit of the target address is larger than the upper bit, it can be determined that the target address is larger than the set address regardless of the size of subsequent address bits. If the most significant bit of the set address and the most significant bit of the target address are equal, the size of the address is discriminated by comparing the size of the bit one bit below the most significant bit. In this case as well, the same magnitude discrimination as that performed for the most significant bit is performed, and thereafter, the magnitude comparison from the upper bit to the lower bit is repeated successively until the magnitude discrimination is completed.

Next, the address discrimination circuit 151 shown in FIG.
The detailed operation of the address discrimination in the above will be described. The NOR 513 and the EXNOR 514 compare the most significant bits of the set address and the target address. NOR51
5 and EXNOR 516 compare the upper 2nd bit. If the first bit of the upper limit address setting register 511 is larger than the most significant bit of the address latch unit 150,
That is, when the first bit of the upper limit address setting register is "1" and the most significant bit output of the address latch unit 150 is "0", the output of the NOR 513 is "1" regardless of the magnitude of the second upper bit OR519. The output becomes "1". On the contrary, if the most significant bit of the address latch unit 150 is larger than the first bit of the upper limit address setting register 511, the output of the NOR 513 becomes “0”, and EXN
Since the output of OR514 becomes "0", EXNOR514
The outputs of the AND 517 and AND 518 each of which has one of the inputs become "0", so that the output of the OR 519 becomes "0".

If the first bit of the upper limit address setting register 511 and the most significant bit output of the address latch section 150 are equal, the output of the NOR 513 remains "0".
At this time, EXNOR output becomes "1", and AND517,
The outputs of AND518 are NOR515 and EXNO, respectively.
It is determined by the output of R516, that is, the magnitude of the upper 2nd bit of the address. If the 0th bit of the upper limit address setting register 511 is the upper 2 bits of the address latch unit 150,
When the output of the NOR 515 is larger than the output of the 1st bit, the output of the AND 517 is "1" and the output of the OR 519 is "1".

If the 0th bit of the upper limit address setting register 511 is equal to or smaller than the output of the upper 2nd bit of the address latch 150, the output of the OR 515 is "0", and the output of the AND 517 is also "0". Becomes EX if the most significant bit and the second bit are equal
Since the outputs of the NOR 514 and the EXNOR 516 are both "1", the output of the AND 518 that receives the respective outputs is "1", and the output of the OR 519 is "1". The address latch unit 150 has the same highest-order bit and the 0th bit of the upper limit address setting register 511.
If the output of the upper 2nd bit of the copy is large, NOR51
5, the output of EXNOR 516 becomes "0", so N
The output of each of OR513, AND517, and AND518 becomes "0", and the output of OR519 becomes "0".

As described above, when the address value set by the upper limit address setting register 511 is equal to the value of the target address, or when the target address value is smaller than the address value set by the upper limit address setting register 511. When the determination is made, the output of OR519 becomes "1", and AND527, that is, EQ152 is determined by the output level of OR526 which is the lower limit address determination result.

Next, a method of determining the lower limit address for determining the output level of the OR 526 will be described. The determination of the lower limit address can be performed in exactly the same way by reversing the relationship between the set address and the target address in the determination of the upper limit address. That is, NO in the upper limit address determination
NOR520 and NO corresponding to R513 and NOR515
An address size determination is performed by setting a signal to be inverted by the input signal in R522 from the value of the address setting register to the output value of the address latch unit 150 which is the target address, and the output level of the OR526 is determined. As described above, the address discrimination circuit 151 uses the EQ.
The output level of 152 is determined.

Next, the single-chip microcomputer 10 of the present invention incorporating the area discriminating circuit 151 described above.
The operation of 0 will be described. First, the upper limit address register 511 and the lower limit address setting register 512 set the write-protected address area. Now, assuming that the address width is 8 bits, the write prohibited address setting area can be set in 10 ways shown in Table 2. The upper limit address setting register 511 and the lower limit address setting register 512 are set according to Table 2. For example, set the upper limit address setting register 511 to 10B and the lower limit address setting register 5
Suppose 12 is set to 01B. Then, the write prohibited address range is set to 40H to BFH.

[0034]

[Table 2]

The difference between this embodiment and the first embodiment is that in the first embodiment, the address that can be set cannot be specified only for a certain block specified by a bank, whereas in this embodiment, the upper limit is set. The lower limit address can be set arbitrarily. In this case, for the sake of explanation, the upper limit address setting register and the lower limit address setting register are each set to 2
Although it is configured with bits, if the bit widths of the upper limit address setting register and the lower limit address setting register are increased here, more detailed address area setting can be performed, and if the internal address bus widths are equal, the address area setting is 1 It can be done in address units. In this way, the address area is set and the result of the address discrimination operation is output EQ15.
The operations after the second level is determined are the same as those in the first embodiment.

[0036]

As described above, according to the present invention, by controlling writing to an arbitrarily set address area, even if the single-chip microcomputer runs out of control, important data is designated in advance in the write-inhibited address area. By doing so, it is possible to prevent data destruction during a runaway.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a single-chip microcomputer of the present invention.

FIG. 2 is a circuit diagram of a write control unit and an address discrimination circuit in the first embodiment of the present invention.

FIG. 3 is a circuit diagram of WDT.

FIG. 4 is a timing chart in the first embodiment of the present invention.

FIG. 5 is a circuit diagram of an address discrimination circuit according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional single-chip microcomputer.

FIG. 7 is a flowchart of an opcode trap.

FIG. 8 is a circuit diagram of a conventional WDT.

FIG. 9 is a conventional timing chart during normal operation.

FIG. 10 is a timing chart of a conventional abnormal operation.

[Explanation of symbols]

 100 Single Chip Microcomputer 110 CPU 111 μROM 112 INTC 113 WDT 115 Reset Control Unit 118 Input / Output Unit 119 ROM 120 RAM 121 Internal Bus 124 Write Control Unit

Claims (1)

[Claims] 1. A single-chip microcomputer having a central processing unit, a microprogram storage unit, a watchdog timer, a write destination address area determination unit, and an input / output unit, wherein the write destination address determination unit is a write unit. It is composed of a prohibited address area designating section and a discrimination section, and checks whether the write destination address at the time of executing the write command from the central processing unit is a write prohibited address. A single-chip microcomputer configured to inhibit a write signal and output a timer reset signal to the watchdog timer.