JPH0645393A - Bonding pad electrode and manufacture thereof - Google Patents

Abstract

PURPOSE:To eliminate influence of charge to be stored on a surface of a wafer transiently by etching by a dry etching unit at the time of manufacturing to an active region of an element through inner interconnections in a bonding pad electrode of a semiconductor device having multilayer metal interconnections. CONSTITUTION:A bonding pad base electrode 13 and an inner interconnection 14 are separately provided, a bonding pad electrode 18 is formed on the electrode 13 via an upper interconnection layer, and the electrode 13 is connected to the interconnection 14. In this case, an area of a contact opening 17 at the side of the interconnection 14 is set to 1/10 or less of that of a contact opening 16 at the side of the electrode 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bonding pad electrode in a semiconductor device having multi-layer metal wiring and a method for manufacturing the same.

[0002]

2. Description of the Related Art Bonding pad electrodes in a conventional semiconductor device having multi-layered metal wiring are constructed as shown in FIG. This figure shows a case of applying to a two-layer Al wiring, and, for example, S is formed on the semiconductor substrate 1 on which a semiconductor element is formed.
The internal wiring composed of the first Al wiring layer connected to the active region of the semiconductor element through the interlayer insulating film ₂ such as iO ₂ , that is, the internal wiring 3 drawn from the gate of the MOS transistor, the diffusion region, or the like It is formed. This internal wiring 3
An interlayer insulating film 4 made of, for example, PSG (phosphosilicate glass) is formed thereon, and a bonding pad made of a second Al wiring layer is formed on the extension 3A corresponding to the bonding pad portion of the internal wiring 3 through the contact opening 5. An electrode 6 is formed, and, for example, plasma S except for the opening 7 that exposes the bonding pad electrode 6 on the uppermost layer.
An overcoat film 8 made of iN is formed and configured. The area of the contact opening 5 of the interlayer insulating film 4 is formed to be substantially the same as the area of the bonding pad electrode 6.

[0003]

The conventional bonding pad electrode described above has the following problems due to its manufacture.

That is, reactive ion etching (RIE)
When the contact opening 5 is formed in the interlayer insulating film 4 by using the apparatus, and when the second layer Al film to be the bonding pad electrode 5 is deposited by using the Al sputtering apparatus (especially, pretreatment of sputtering). In the same device as the lower layer A
When the surface oxide film such as the 1 wiring is removed by sputter etching), a large power is transiently applied to the RIE device and the Al sputtering device, and the wafer surface is charged.

At this time, the extension 3A in which the bonding pad electrode 6 of the lower internal wiring 3 is formed serves as a so-called antenna, and the charge charged on the wafer surface is collected in the extension 3A. In this case, the extension part 3 that serves as an antenna
Since the area of A is large, many charges will be collected.

The charges collected in the extension 3A flow into the active region connected through the internal wiring 3 and, for example, in the case of the gate of a MOS transistor, deteriorate the gate insulating film under the gate electrode, Further, if it is a diffusion region, the barrier property of the barrier metal is destroyed, and a so-called PN junction is deteriorated by causing a junction leak due to an alloying reaction between the silicon layer and aluminum.

The opening 7 of the overcoat film 8 is
It is formed by wet etching or plasma etching with little influence, and the above problems do not occur.

In view of the above points, the present invention provides a bonding pad electrode in a semiconductor device that does not adversely affect the active region of an element during manufacturing, and a method of manufacturing the same.

[0009]

The present invention relates to a bonding pad electrode in a semiconductor device having a multi-layer metal wiring, wherein a bonding pad base electrode 13 and an internal wiring 14 are separated from each other, and a contact opening portion 16 of an interlayer insulating film 15 is provided. 17
The bonding pad base electrode 13 is formed on the bonding pad base electrode 13 in the upper wiring layer via (and 22), and the bonding pad base electrode 13 and the internal wiring 14 are connected.

The area of the contact opening 17 on the internal wiring 14 side is set to 1/10 or less of the area of the contact opening 16 on the bonding pad electrode 18 side.

In the manufacturing method according to the present invention, the step of forming the bonding pad base electrode 13 made of the first metal wiring layer and the internal wiring 14 separately from each other, and the step of forming the interlayer insulating film 15 The step of forming the contact openings 16, 17 (and 22) in the portions of the insulating film 15 corresponding to the bonding pad base electrode 13 and the internal wiring 14, respectively, and the second step through the contact openings 16, 17 (and 22) The bonding pad electrode 18 is formed of the metal wiring layer and the bonding pad base electrode 13 and the internal wiring 14 are connected to each other, and the etching process performed in the above step is performed by a dry etching apparatus.

[0012]

In the bonding pad electrode according to the present invention, since the bonding pad base electrode 13 made of the metal wiring layer therebelow and the internal wiring 14 are separated from each other, the interlayer insulating film is manufactured by the RIE apparatus, the Al sputtering apparatus or the like. During formation of the contact openings 16 and 17 (and 22) of 15 and deposition of a metal film to be the bonding pad electrode 18, the charge charged on the wafer surface is collected on the base electrode 13 having a transiently large area. It does not flow into the internal wiring 14, and the active regions of the elements connected to the internal wiring 14 are not adversely affected. Finally, since the base electrode 13 and the internal wiring 14 are connected in the same wiring layer as the bonding pad electrode 18, the conduction between the internal wiring 14 and the bonding pad electrode 18 can be obtained.

By setting the area of the contact opening 17 on the side of the internal wiring 14 to be 1/10 or less of the area of the contact opening 16 on the side of the bonding pad electrode 18, the charges charged on the surface of the wafer are charged. However, the collection efficiency is extremely small and does not adversely affect the active region.

Further, in the manufacturing method, the bonding pad base electrode 13 made of the first metal wiring layer and the internal wiring 1 are formed.
When the contact openings 16 and 17 (and 22) are formed in the interlayer insulating film 15 by dry etching after forming 4 separately, or when the second metal wiring layer is formed. When the surface oxide film of the lower wiring layer is removed by dry etching as a pre-treatment of the wafer, even if the wafer surface is charged due to an excessive increase in power on the dry etching equipment side, a large bonding pad substrate The charges collected in the electrode 13 are transferred to the internal wiring 14
It doesn't flow to. Therefore, it is possible to avoid the adverse effect of the transient charge on the active region of the element connected to the internal wiring 14.

The internal wiring 1 is formed by the first metal wiring layer.
4 and the bonding pad base electrode 13 are formed, and the bonding pad electrode 18 is formed by the second metal wiring layer, and the base electrode 13 and the internal wiring 10 are connected to each other without increasing the number of steps. Bonding pad electrodes are formed. Therefore, a semiconductor device having highly reliable multilayer metal wiring can be obtained.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 and FIG. 2 show one embodiment of the present invention, which is a double layer A
This is a case where the invention is applied to a bonding pad electrode of a semiconductor device having an l wiring structure. In this example, a first layer of Al is formed on a semiconductor substrate 11 on which semiconductor elements such as transistors are formed with an interlayer insulating film 12 such as SiO ₂ interposed therebetween.
The bonding pad base electrode (so-called bonding cushion electrode) 13 formed of a wiring layer and the internal wiring 14 connected to the active region of the semiconductor element are formed in a separated state.

An interlayer insulating film 15 made of, for example, PSG (phosphosilicate glass) is formed on the upper surface including the base electrode 13 and the internal wiring 14, and a contact portion 14a of the base electrode 14 and the internal wiring 15 is contacted. Openings 16 and 17 are formed.

Further, a bonding pad electrode 18 made of a second Al wiring layer is formed on the base electrode 13 through the contact opening 16, and an extension 18A extending from the bonding pad electrode 18 is formed on the internal wiring 14.
Is connected to the connection portion 14a. Connection part 1 of internal wiring 14
The area of the contact opening 17 on the 4a side is 1 / the area of the contact opening 16 on the bonding pad electrode 18 side.
It is set to 10 or less. Then, an overcoat film 20 made of, for example, plasma SiN is formed in the uppermost layer except for the opening 19 exposing the bonding pad electrode 18, and the bonding pad electrode of this embodiment is configured.

Next, a manufacturing example of this bonding pad electrode is shown in FIGS.

First, as shown in FIG. 3A, an interlayer insulating film 12 made of, for example, SiO _{2 is} deposited on one main surface of a silicon semiconductor substrate 11 on which semiconductor elements are formed, and the interlayer insulating film 12 is formed on the interlayer insulating film 12. The bonding pad base electrode 13 and the internal wiring 14 connected to the active region of the semiconductor element are formed in a state of being separated from each other by the first Al wiring layer.

Next, as shown in FIG. 3B, the base electrode 13
An interlayer insulating film 15 of, for example, PSG is formed on the entire surface including the internal wiring 14.

Next, as shown in FIG. 3C, the base electrode 13 and the internal wiring 14 of the interlayer insulating film 15 are formed by using the RIE apparatus.
The portions corresponding to the connection portions 14a are selectively removed by etching to form the contact openings 16 and 17, respectively. In this case, the area of the contact opening 17 is formed to be 1/10 or less of the area of the contact opening 16.

During this etching process, a large amount of power is transiently applied to the RIE apparatus, and the wafer surface is electrically charged,
A of the lower layer where this electrode faces the contact openings 16 and 17
l wiring layer, the internal wiring 14 and the base electrode 16
Are separated from each other, the charges collected in the base electrode 13 having a large area do not flow to the internal wiring 14 side.

Next, as shown in FIG. 4D, a second-layer Al film is deposited by using, for example, an Al sputtering apparatus and patterned to form a bonding pad electrode 18 by a so-called second-layer Al wiring layer. That is, a bonding pad electrode 18 connected to the base electrode 13 through the contact opening 16, and an extension 18A extending integrally from the bonding pad electrode 18 and connected to the connecting portion 14a of the internal wiring 14 facing the contact opening 17. Are formed at the same time.

When the second Al film is deposited by using the Al sputtering device, the same Al sputtering device is used as a pretreatment for the first Al film facing the contact openings 16 and 17 in the lower layer. Layer (ie, base electrode 13, internal wiring 1
The surface oxide film on the surface of the connection portion 14a) of No. 4 is removed by etching, and then Al sputter processing is performed. During this pretreatment, a large amount of power is transiently applied to the device, and charges are accumulated on the surface of the wafer.
Although they are collected in the lower Al wiring layer facing 6 and 17, the charges collected in the large-sized base electrode 13 do not flow to the internal wiring 14 side because the internal wiring 14 and the base electrode 16 are separated.

Thereafter, as shown in FIG. 4E, an uppermost layer, for example, an overcoat film 20 of plasma SiN is deposited and an opening 19 exposing the bonding pad electrode 18 is formed by, for example, plasma etching or solution etching. . The etching process by the plasma etching apparatus used at this time is not affected by the above-mentioned charging of the wafer surface.

According to the above-described embodiment, the internal wiring 14 and the bonding pad base electrode 13 are separately formed in the first Al wiring layer, and then the bonding pad electrode 18 is formed by the second Al wiring layer. By forming the extended portion 18A and connecting the extended portion 18A to the connection portion 14a of the internal wiring 14, the contact opening portions 16 and 17 of the interlayer insulating film 15 are formed by the RIE apparatus and the Al sputtering apparatus, and the bonding pad electrode 18 is formed. When the second layer of Al film to be formed is deposited, electric charges are transiently charged on the wafer surface,
Even if this charge is collected by the base electrode 13 having a large area due to the antenna effect, it does not flow to the internal wiring 14 side, and the internal broken line 14
On the side, electric charges are only collected in the connection portion 14a having a small area. Therefore, the charge collection efficiency on the side of the internal wiring 14 is lowered, and it is possible to control the deterioration caused in the active region of the element connected to the internal wiring 14 due to the charge, for example, the above-mentioned deterioration of the gate oxide film and the PN junction. You can

Particularly, by setting the area of the contact opening 17 on the side of the connecting portion 14a of the internal wiring 14 to be 1/10 or less of the area of the contact opening 16 on the side of the bonding pad base electrode 13, the area of the internal wiring 14 is reduced. The charge collection efficiency can be sufficiently reduced so as not to affect the active region of the device.

Also in the manufacturing method, the internal wiring 14 and the bonding pad base electrode 13 are formed in the first Al wiring layer, and the bonding pad electrode 18 is formed and the internal wiring is connected in the second Al wiring layer. Therefore, the desired bonding pad electrode can be formed without increasing the number of steps.

5 and 6 show another embodiment of the present invention. In this example, the internal wiring 14 and the bonding pad base electrode 13 are formed separately by the first Al wiring layer, and the base electrode 13 is the same as the internal wiring 14 in the region 13a corresponding to the bonding pad electrode 18. It is formed of an extension portion 13b extending in width. Then, the interlayer insulating film 15
On the other hand, the contact opening 16 is formed in the portion corresponding to the region 13a of the base electrode, the contact opening 22 is formed in the portion corresponding to the end of the extension 13b, and the connecting portion 14a of the internal wiring 14 is formed. The contact opening 17 is formed in the corresponding portion.

Then, a bonding pad electrode 18 connected to the region 13a of the base electrode 13 is formed in the contact opening 16 by the second Al wiring layer, and the contact opening 17 is formed by the same second Al wiring layer. And 2
2 through the base electrode 13 of the connection portion 14a of the internal wiring 14
The connection wiring 23 for connecting to the extension 13b of is formed. Since other configurations are the same as those in FIGS. 1 and 2, duplicated description will be omitted.

Also in this case, the connecting portion 14a of the internal wiring 14
The area of the contact opening 17 on the side is 1/10 of the area of the contact opening 16 on the side of the bonding pad electrode 18.
Set as follows.

Also in this structure, the internal wiring 1 of the electric charges charged on the surface of the wafer is used as in the example of FIGS. 1 and 2 described above.
The collection efficiency on the fourth side is reduced, and deterioration due to electric charges in the active region of the element connected to the internal wiring 14 can be controlled.

As described above, in this embodiment, it is possible to provide a semiconductor device having a highly reliable bonding pad electrode, and further, a highly reliable multilayer metal wiring.

In the above example, the present invention is applied to a two-layer Al wiring structure, but it can also be applied to a multilayer wiring structure of more layers.

[0037]

According to the present invention, the base electrode and the internal wiring under the bonding pad electrode are separately provided, and the bonding pad electrode is formed and the base electrode and the internal wiring are connected in the upper wiring layer. The efficiency of collecting the electric charges charged on the wafer surface at the time of manufacturing in the internal wiring can be reduced. As a result, deterioration of the active region of the element connected to the internal wiring can be controlled.

Therefore, it is possible to obtain a semiconductor device having a highly reliable bonding pad electrode, and further, a multilayer metal wiring.

[Brief description of drawings]

FIG. 1 is a plan view showing an example of a bonding pad electrode according to the present invention.

FIG. 2 is a sectional view taken along the line AA of FIG.

FIG. 3 is a manufacturing process diagram (1) of a bonding pad electrode according to the present invention.

FIG. 4 is a manufacturing process diagram (2) of the bonding pad electrode according to the present invention.

FIG. 5 is a plan view showing another example of the bonding pad electrode according to the present invention.

6 is a cross-sectional view taken along the line BB of FIG.

FIG. 7 is a cross-sectional view of a conventional bonding pad electrode.

[Explanation of reference signs] 1,11 Semiconductor substrate 2,12 Interlayer insulating film 3,14 Internal wiring 4,15 Interlayer insulating film 5,16,17,22 Contact opening 6,18 Bonding pad electrode 13 Bonding pad base electrode 7, 19 Openings 8 and 20 Overcoat film 23 Connection wiring

Claims (3)

[Claims] 1. A bonding pad electrode in a semiconductor device having multi-layer metal wiring, wherein a bonding pad base electrode and an internal wiring are separated, and the bonding pad base is formed in an upper wiring layer through a contact opening of an interlayer insulating film. A bonding pad electrode, wherein a bonding pad electrode on the electrode is formed, and the bonding pad base electrode and the internal wiring are connected. 2. The bonding pad electrode according to claim 1, wherein the area of the contact opening on the internal wiring side is set to be 1/10 or less of the area of the contact opening on the bonding pad electrode side. 3. A step of forming a bonding pad base electrode made of a first metal wiring layer and an internal wiring separately from each other, and an interlayer insulating film is formed to form the bonding pad base electrode and the internal wiring of the interlayer insulating film. Forming a contact opening in each of the portions corresponding to the wiring, forming a bonding pad electrode in the second metal wiring layer through the contact opening, and connecting the bonding pad base electrode and the internal wiring The method of manufacturing a bonding pad electrode according to claim 1, wherein the etching treatment performed in the above step is performed using a dry etching apparatus.