JPH0644132A - Memory system and computer system - Google Patents

Abstract

PURPOSE:To incorporate a CPU module into a system and to access to a main memory at high speed without extending the bus width of a system bus when the bus width of a CPU bus is extended. CONSTITUTION:A bus interface 1c compares the address of an access object with an address stored in an address memory 1b at the time of read access, reads data corresponding to the address by which the compared result coincides from a data memory 1a and reads data corresponding to the address which coincides with the address of the access object, which is stored in an address memory 2b, when the compared result does not coincide. At the time of write access, 1c updates data stored in the data memory 1a into write data, and transfers data from the data memory 2a to the data memory 1a and updates transferred data into write data when the compared result does not coincide.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system and a computer system adopting a distributed main memory system.

[0002]

2. Description of the Related Art Conventionally, the processor (CPU) of a computer system has become faster than the bus timing of the system bus, and the frequency of use of the system bus has increased. The CPU accesses the main memory via the system bus. Therefore, it is difficult for the conventional system to increase the access speed of the main memory according to the increase in the speed of the CPU.

On the other hand, with the increase in speed, a large-capacity main memory is required. In order to meet such demands for high speed and large capacity, a distribution system in which the main memory is divided and distributed is considered. In the distributed method, the main memory and the main memory connected to the system bus are connected to the main memory.
It is distributed and arranged in the main memory connected to the PU bus.

When such a system is adopted, the CPU is C
By accessing the main memory connected to the PU bus, the frequency of use of the system bus can be reduced, so that high speed access can be realized. Further, since the main memory can be distributed and arranged as memory modules (specifically, a memory card or the like) connected to the system bus, it is possible to increase the capacity of the main memory as a whole. In this case, the CPU and the main memory are configured as a processor module (CPU module).

By the way, in the case of developing a new CPU module in which the bus width of the CPU bus is expanded in order to speed up the access to the main memory in the CPU module, the new CPU module is used as it is in the conventional system. Cannot be used.

For use, if the bus width of the new CPU bus is N times the bus width of the system bus, the bus width of the CPU bus is reduced to 1 / N by, for example, an external circuit or the like. Need to be incorporated into. Alternatively, it is necessary to newly develop the system according to the new CPU module.

[0007]

The distributed system of the main memory makes it possible to increase the capacity of the entire main memory. However, even if a new CPU module in which the bus width of the CPU bus is expanded is developed, it is necessary to reduce the bus width of the CPU bus according to the system bus in order to incorporate it into the conventional system. Further, it is conceivable to newly develop the system in accordance with the new CPU module, but this is not practical in terms of development cost and the like. Therefore, even if the distribution method of main memory is simply adopted,
It is difficult to realize high-speed access to the main memory by the CPU.

An object of the present invention is to provide a CP for a CPU module in a system adopting a distributed system of main memory.
To provide a memory system and a computer system in which, when the bus width of the U bus is expanded, the CPU module can be incorporated into the system without expanding the bus width of the system bus to realize high-speed access of the main memory. It is in.

[0009]

SUMMARY OF THE INVENTION The present invention provides a CPU in a memory system employing a main memory distribution system.
Read control means for controlling the data to be accessed from the first main memory connected to the CPU bus or the second main memory connected to the system bus at the time of read access of 2 is a memory system including a write control unit that updates the data of (1) to write data.

Further, according to the present invention, in a computer system adopting a distributed system of main memory, a processor module having a first main memory and a first address memory, a second main memory and a second address memory. A memory module having a CPU, read control means for controlling data to be accessed at the time of read access of the CPU to be read from the first main memory connected to the CPU bus or the second main memory connected to the system bus, and the CPU Is a computer system including write control means for updating access target data to write data at the time of write access.

[0011]

In the memory system of the present invention, the read control means determines whether or not there is data to be accessed in the first main memory, and if there is data, the data is read from the first main memory and the data is not written. If it exists, the data stored in the second main memory is transferred to the first main memory, and the data to be accessed is read from the first main memory. The write control means determines whether or not there is data at the address to be accessed in the first main memory, updates the data in the first main memory to write data if there is data, and if there is no data, Second
The data stored in the main memory is transferred to the first main memory, and the data to be accessed in the first main memory is updated to write data.

In the computer system of the present invention, the read control means compares the address to be accessed with the address stored in the memory for the first address, and the data corresponding to the address where the comparison result is the first is compared. Read from the main memory, and if the comparison result does not match, the data corresponding to the address that matches the access target address stored in the second address memory is read from the second main memory. The write control means compares the address to be accessed with the address stored in the first address memory, and updates the data corresponding to the address stored in the first main memory and the comparison result matches to the write data. If the comparison result does not match, the data corresponding to the address that matches the access target address stored in the second address memory is transferred to the first main memory, and this transferred data is written as write data. To update.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a computer system according to the embodiment, FIGS. 2 to 4 are conceptual diagrams for explaining the operation of the embodiment, and FIGS. 5 and 6 are operations of the embodiment. 4 is a flowchart for explaining

This system includes a processor (CPU) module 1 connected to a system bus 4, a plurality of memory modules 2 and 3, an I / O module 5 and an address module.
It has an initializer 6.

The CPU module 1 is a data memory 1
a, address memory 1b, bus interface 1c
And a CPU 1d. The data memory 1a and the address memory 1b are memories that form part of the main memory of the system. The data memory 1a stores data, and the address memory 1b stores addresses.

The bus interface 1c is connected to the CPU 1d through the CPU bus 1e and is also connected to the system bus 4. Bus interface 1c
Configures a read / write control circuit that executes read control and write control for the main memory in response to a read / write access request from the CPU 1d.

The memory modules 2 and 3 form a part of the main memory and have data memories 2a and 3a and address memories 2b and 3b, respectively. The memory modules 2 and 3 have respective bus interfaces 2c and 3c.
Is connected to the system bus 4. The bus interfaces 2c and 3c respectively include the data memories 2a and 2a.
Read control and write control for the memory 3a and the address memories 2b and 3b are executed.

The I / O module 5 is a circuit which constitutes an interface of various input / output devices. The address initializer 6 is a circuit that initializes the address of the main memory when the power of the system is turned on. next,
The operation of the embodiment will be described.

First, as shown in step S1 of FIG.
When the CPU 1d makes an access request to a designated address in the main memory, the bus interface 1c performs read control or write control of the main memory. CP
U1d outputs an address as shown in FIG. 2A at the time of access request. The address is composed of a portion X used for I / O and memory selection (chip select, etc.), an address portion Y stored in the address memory 1b, and an input address portion Z of the data memory 1a and the address memory 1b. .

The bus interface 1c is a CPU 1d.
The address memory 1b and the data memory 1a are accessed by the address received from the CPU 1d, and it is determined whether the address and data of the access request of the CPU 1d are stored. Specifically, as shown in FIG. 2B, the bus interface 1c accesses the address memory 1b and the data memory 1a by the value M of the address portion Z from the CPU 1d. Address memory 1b
The address L corresponding to the data N is stored in. The bus interface 1c compares the value of the address portion Y from the CPU 1d with the address L (step S2).

If the comparison results match (step S3)
YES), the bus interface 1c is the CPU 1d
It is determined that the access request data N is stored in the data memory 1a. At this time, if the access request is a read access (YES in step S4), the bus interface 1c reads the data N from the data memory 1a and transfers it to the CPU 1d through the CPU bus 1e (step S5).

If the access request is a write access (NO in step S4), the bus interface 1c writes the write data to the designated address M of the data memory 1a. That is, the data N of the data memory 1a corresponding to the designated address L is updated to the write data (step S6).

On the other hand, if the comparison results do not match (NO in step S3), the bus interface 1c executes the processing shown in FIG. Here, the CPU 1d uses the address (X = 0, Y = R as the address of the access request.
1, Z = 55) is output. In addition, the CPU module 1
In the address memory 1b and the data memory 1a, as shown in FIG. 3A, the address R2 and the data D2 are stored in the area of the address 55, respectively.
In the address memory 2b and the data memory 2a of the memory module 2, as shown in FIG.
Address R1 and data D1 are stored in the area of address 55, respectively.

If the access request is a read access (YES in step S7), the bus interface 1c
Is an address (X = 0, Y = R through the system bus 4
1, Z = 55) is output and a read request is issued to the memory module 2. In the memory module 2, the bus interface 2c reads the address R1 and the data D1 from the address memory 2b and the data memory 2a. The bus interface 2c transfers the address R1 and the data D1 to the bus interface 1c through the system bus 4.

On the other hand, the bus interface 1c reads the addresses R2 and D2 from the address memory 1b and the data memory 1a and transfers them to the bus interface 2c of the memory module 2. As a result, the bus interface 1c stores the address R2 stored in the address memory 1b of the CPU module 1 and the address R1 of the address memory 2b of the memory module 2 as shown in FIGS. Replace (step S8). The bus interface 1c is shown in FIG.
As shown in (C) and (D), the data D2 stored in the data memory 1a of the CPU module 1 and the data D1 of the data memory 2a of the memory module 2 are exchanged (step S9).

The bus interface 1c is shown in FIG.
As shown in FIG. 2, the data D1 to be accessed, which is stored by exchange in the data memory 1a, is read, and the CPU 1d
(Step S10).

On the other hand, if the access request is a write access (NO in step S7), the bus interface 1
c is an address (X = 0, Y =
R1, Z = 55) is output and a read request is issued to the memory module 2.

Here, the CPU 1d outputs the data D3 for updating the data D1 corresponding to the address R1 as write data. Further, in the address memory 1b and the data memory 1a of the CPU module 1, as shown in FIG. 4A, the address R2 and the data D2 are stored in the area of the address 55, respectively. Also,
In the address memory 2b and the data memory 2a of the memory module 2, as shown in FIG. 4B, the address R1 and the data D1 are stored in the area of the address 55, respectively.

In the memory module 2, the bus interface 2c reads the address R1 and the data D1 from the address memory 2b and the data memory 2a.
The bus interface 2c transfers the address R1 and the data D1 to the bus interface 1c through the system bus 4.

On the other hand, the bus interface 1c reads the addresses R2 and D2 from the address memory 1b and the data memory 1a and transfers them to the bus interface 2c of the memory module 2. As a result, the bus interface 1c, as shown in FIG.
The address R2 stored in the address memory 1b of the CPU module 1 and the address R1 of the address memory 2b of the memory module 2 are exchanged (step S1).
1).

The bus interface 1c is shown in FIG.
As shown in (D), the data D2 and the memory module 2 stored in the data memory 1a of the CPU module 1
And the data D1 in the data memory 2a is exchanged (step S12).

The bus interface 1c is shown in FIG.
As shown in, the access target data D1 stored by exchange in the data memory 1a is updated to the write data D3 from the CPU 1d (step S13).

In this way, in the distributed system in which the main memory is distributed in the CPU module 1 and the memory modules 2 and 3, the data requested by the CPU 1d exists in the main memory (data memory 1a) of the CPU module 1. For example, the read / write operation is executed through the CPU bus 1e.

If the bus interface 1c does not exist, the bus interface 1c accesses the memory modules 2 and 3 and transfers the access request data (including the address) stored in the main memory of the memory modules 2 and 3 to the CPU module. 1 in the main memory. Then, the read / write operation of the access request to the main memory of the CPU module 1 is executed through the CPU bus 1e.

Therefore, as a result, the CPU 1d
The main memory can be accessed through the CPU bus 1e of the U module 1. As a result, when a new CPU module 1 in which the bus width of the CPU bus 1e is expanded is developed, the new CPU module 1 can be incorporated into the system without changing the bus width of the system bus 4 of the system. It will be possible. In other words,
The new CPU module 1 for high speed
Can be incorporated into conventional systems.

[0037]

As described above in detail, according to the present invention, in the system adopting the distributed system of the main memory, C
New CP with increased bus width of PU bus for higher speed
The U-module can be incorporated without modification of conventional systems. Therefore, it is possible to increase the capacity of the entire main memory by the distributed system and to incorporate a high-speed CPU module, and as a result, it is possible to achieve high-speed access to the main memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is a conceptual diagram for explaining the operation of the embodiment.

FIG. 3 is a conceptual diagram for explaining the operation of the embodiment.

FIG. 4 is a conceptual diagram for explaining the operation of the embodiment.

FIG. 5 is a flowchart for explaining the operation of the embodiment.

FIG. 6 is a flowchart for explaining the operation of the embodiment.

[Explanation of symbols]

1 ... Processor module, 1a, 2a, 3a ... Data memory, 1b, 2b, 3b ... Address memory, 1
c, 2c, 3c ... Bus interface.

Claims (2)

[Claims] 1. Data storage / access by CPU
A main memory for reproduction is divided into a plurality of parts, and a distributed memory means composed of a first main memory connected to a CPU bus and a second main memory connected to a system bus; and a read access of the CPU, The presence or absence of data to be accessed in the first main memory is determined, if the data exists, the data is read from the first main memory, and if the data does not exist, the second main memory is read. Read control means for transferring the data stored in the memory to the first main memory and reading the data to be accessed from the first main memory; and the first main during the write access of the CPU. The presence or absence of data at the address to be accessed in the memory is determined, and if the data exists, the data in the first main memory is Update to the first data, and when the data does not exist, the data stored in the second main memory is transferred to the first main memory, and the data to be accessed in the first main memory is updated. A memory system comprising a write control means for updating to write data. 2. A distributed memory means that divides a main memory into a plurality of parts and is composed of a first main memory connected to a CPU bus and a second main memory connected to a system bus, and the first main memory. A processor module having a memory, an address corresponding to the data stored in the CPU and the first main memory, and a memory for the first address connected to the CPU bus; and a second main memory And a memory module having a second address memory for storing an address corresponding to the data stored in the second main memory, and an address to be accessed and a first address for a read access of the CPU. The address stored in the memory is compared, and the data corresponding to the address where this comparison result matches When data is read from the first main memory and the comparison result does not match, the data corresponding to the address that matches the access target address stored in the second address memory is stored in the second main memory. From the read control means and the address to be accessed at the time of the write access of the CPU are compared with the address stored in the first address memory, and the comparison result is stored in the first main memory. The data corresponding to the matched address is updated to the write data, and when the comparison result does not match, the data corresponding to the address matching the address of the access target stored in the second address memory is updated to the first data. And a write control means for updating the transferred data to write data. A computer system characterized by the above.