JPH0642550B2 - MIS type nonvolatile memory and method of manufacturing the same - Google Patents

MIS type nonvolatile memory and method of manufacturing the same

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Publication number
JPH0642550B2
JPH0642550B2 JP62200323A JP20032387A JPH0642550B2 JP H0642550 B2 JPH0642550 B2 JP H0642550B2 JP 62200323 A JP62200323 A JP 62200323A JP 20032387 A JP20032387 A JP 20032387A JP H0642550 B2 JPH0642550 B2 JP H0642550B2
Authority
JP
Japan
Prior art keywords
silicon nitride
nitride film
film
manufacturing
gate insulating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62200323A
Other languages
Japanese (ja)
Other versions
JPS6442867A (en
Inventor
泰信 斎藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP62200323A priority Critical patent/JPH0642550B2/en
Publication of JPS6442867A publication Critical patent/JPS6442867A/en
Publication of JPH0642550B2 publication Critical patent/JPH0642550B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はMIS型不揮発性メモリー及びその製造方法に
関する。
The present invention relates to a MIS type non-volatile memory and a method for manufacturing the same.

〔従来の技術〕[Conventional technology]

従来、MIS型不揮発性メモリーを構成するMNOS集
積回路においては、ゲート絶縁膜は酸化シリコン膜と窒
化シリコン膜とから構成されており、この窒化シリコン
膜は一般にNH3及びSiH2Cl2、あるいはNH3及び
SiH4の流量比を固定したCVD法で形成されてい
た。
Conventionally, in a MNOS integrated circuit which constitutes a MIS type nonvolatile memory, a gate insulating film is composed of a silicon oxide film and a silicon nitride film, and this silicon nitride film is generally NH 3 and SiH 2 Cl 2 or NH It was formed by the CVD method with a fixed flow ratio of 3 and SiH 4 .

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかしながら、上述した従来のMNOS集積回路の窒化
シリコン膜の形成方法は、原料ガスの流量比は固定する
ため、窒化シリコン膜の組成比が一定となり、ゲート絶
縁膜中に電荷を注入する書き込み特性、注入された電荷
を放出する消去特性及び注入された電荷の保持特性(以
後記憶特性と称する)、繰り返し書き込み消去に伴なう
特性の劣化(以後疲労特性と称する)等のメモリー特性
の各々の最適特性を得ることができなかった。
However, in the above-described conventional method for forming the silicon nitride film of the MNOS integrated circuit, since the flow rate ratio of the raw material gas is fixed, the composition ratio of the silicon nitride film becomes constant, and the write characteristic of injecting charges into the gate insulating film, Optimum of each memory characteristic such as erase characteristic for releasing injected charge, retention characteristic for injected charge (hereinafter referred to as memory characteristic), and deterioration of characteristic due to repeated write / erase (hereinafter referred to as fatigue characteristic) Could not get the characteristics.

そのため、書き込み及び消去特性を向上させるため窒化
シリコン膜の組成比r(r=N/Si)を小さくした場
合、酸化シリコン膜と窒化シリコン膜との界面でSi−
N結合が多くなり、疲労特性が低下する等の欠点があっ
た。
Therefore, when the composition ratio r (r = N / Si) of the silicon nitride film is reduced in order to improve writing and erasing characteristics, Si- is formed at the interface between the silicon oxide film and the silicon nitride film.
There were drawbacks such as increased N-bonding and reduced fatigue properties.

本発明の目的は、メモリー特性の改善されたMIS型不
揮発性メモリー及びその製造方法を提供することにあ
る。
An object of the present invention is to provide a MIS type non-volatile memory having improved memory characteristics and a manufacturing method thereof.

〔問題点を解決するための手段〕[Means for solving problems]

第1の発明のMIS型不揮発性メモリーは、半導体基板
上に形成された酸化シリコン膜と窒化シリコン膜の2層
からなるゲート絶縁膜とこのゲート絶縁膜上に設けられ
たゲート電極とを有するMIS型不揮発性メモリーにお
いて、前記窒化シリコン膜の組成は深さ方向に連続的に
変化し少くとも前記ゲート電極に近づくほど窒素濃度が
高くなっているものである。
A MIS type nonvolatile memory according to a first aspect of the present invention is a MIS having a gate insulating film formed on a semiconductor substrate and having a two-layer structure including a silicon oxide film and a silicon nitride film, and a gate electrode provided on the gate insulating film. In the non-volatile memory, the composition of the silicon nitride film continuously changes in the depth direction, and the nitrogen concentration increases as it gets closer to the gate electrode.

第2の発明の不揮発性メモリーの製造方法は、半導体基
板上に酸化シリコン膜と窒化シリコン膜を順次形成した
のちパターニングして酸化シリコン膜と窒化シリコン膜
の2層からなるゲート絶縁膜を形成するMIS型不揮発
性メモリーの製造方法であって、反応ガスの流量比を変
えるCVD法により前記窒化シリコン膜を連続的に組成
を変化させて形成するものである。
In the method for manufacturing a non-volatile memory of the second invention, a silicon oxide film and a silicon nitride film are sequentially formed on a semiconductor substrate and then patterned to form a gate insulating film composed of two layers of a silicon oxide film and a silicon nitride film. A method of manufacturing a MIS non-volatile memory, wherein the composition of the silicon nitride film is continuously changed by a CVD method in which a flow rate ratio of a reaction gas is changed.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明す
る。
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)〜(d)は本発明の第1の実施例のMIS
型不揮発性メモリーの製造方法を説明するための、工程
順に示した半導体チップの断面図である。
1A to 1D are MISs according to the first embodiment of the present invention.
6A to 6C are cross-sectional views of the semiconductor chip in process order, for explaining the method for manufacturing the nonvolatile memory.

まず第1図(a)に示すように、シリコン基板1上に厚
さ1000Å以上の素子分離用のフィールド酸化膜2を
形成したのち、MNOSトランジスタを形成する能動領
域に下層のゲート絶縁膜となる酸化シリコン膜3を10
数Åの厚さ形成する。
First, as shown in FIG. 1A, a field oxide film 2 for element isolation having a thickness of 1000 Å or more is formed on a silicon substrate 1 and then a lower gate insulating film is formed in an active region where a MNOS transistor is formed. Silicon oxide film 3 to 10
Form a few Å thickness.

次に第1図(b)に示すように、減圧CVD法により上
層のゲート絶縁膜となる窒化シリコン膜4を、厚さ方向
に連続的に組成比rを変えて数100Åの厚さに形成す
る。この組成比r(N/Si)の変化した窒化シリコン
膜は、例えば減圧CVD法において用いられるNH3
SiH2Cl2の流量比R(NH3/SiH2Cl2)を変
えることにより形成できる。
Next, as shown in FIG. 1 (b), a silicon nitride film 4 serving as an upper gate insulating film is formed by a low pressure CVD method to a thickness of several hundred Å by continuously changing the composition ratio r in the thickness direction. To do. The silicon nitride film having the changed composition ratio r (N / Si) can be formed, for example, by changing the flow rate ratio R (NH 3 / SiH 2 Cl 2 ) of NH 3 and SiH 2 Cl 2 used in the low pressure CVD method. .

第2図はこの第1の実施例における窒化シリコン膜を形
成した時の反応ガスの流量比Rと窒化シリコン膜の厚さ
との関連図である。
FIG. 2 is a diagram showing the relationship between the flow rate ratio R of the reaction gas and the thickness of the silicon nitride film when the silicon nitride film is formed in the first embodiment.

第2図において、酸化シリコン膜3の界面からの厚さt
1の領域である、窒化シリコン膜4の形成初期には、流
量比Rを数100に設定し、急激に流量比Rを低下させ
10以下にする。この操作により、酸化シリコン膜3
と、窒化シリコン膜4の界面には、Si−N結合の少な
い窒化シリコン膜が形成され、疲労特性が改善される。
In FIG. 2, the thickness t from the interface of the silicon oxide film 3 is
At the initial stage of formation of the silicon nitride film 4, which is the region of 1 , the flow rate ratio R is set to several hundreds, and the flow rate ratio R is rapidly decreased to 10 or less. By this operation, the silicon oxide film 3
Then, a silicon nitride film with few Si—N bonds is formed at the interface of the silicon nitride film 4, and the fatigue characteristics are improved.

次に、t2の領域では、流量比Rを10以下の適当な値
で反応させる。この時の窒化シリコン膜4はSiの未結
合手の多い膜質となり、電荷を捕獲するトラップが増大
し書き込み特性が改善される。
Then, in the region of t 2 , the flow rate ratio R is made to react at an appropriate value of 10 or less. At this time, the silicon nitride film 4 becomes a film having many Si unbonded hands, traps for trapping charges are increased, and writing characteristics are improved.

次に、t3の領域では流量比Rをしだいに大きくし、
(最終的にはR≧100)窒化シリコン膜4をSiの末
結合手の少ない膜質とする。これにより、ゲート電極側
への電荷移動が減少し、記憶特性が改善される。
Next, in the region of t 3 , the flow rate ratio R is gradually increased,
(Finally, R ≧ 100) The silicon nitride film 4 is made to have a film quality with few Si end bonds. As a result, the charge transfer to the gate electrode side is reduced and the storage characteristics are improved.

次に、このように窒化シリコ膜4を組成を変えて形成し
たのち第1図(c)に示すように、全面に多結晶シリコ
ン膜5を減圧CVD法で形式する。
Next, after forming the silicon nitride film 4 with different compositions in this way, a polycrystalline silicon film 5 is formed on the entire surface by a low pressure CVD method as shown in FIG. 1 (c).

次いで第1図(d)に示すように、フォトリソグラフィ
工程によりドライエッチ技術を用いて、多結晶シリコン
よりなるゲート電極5Aを形成後、イオン注入技術を用
いてMNOSトランジスタのソース・ドレイン拡散層6
を形成する。以下常法に従ってMNOSトランジスタを
完成させる。
Then, as shown in FIG. 1D, a gate electrode 5A made of polycrystalline silicon is formed by a dry etching technique by a photolithography process, and then a source / drain diffusion layer 6 of the MNOS transistor is formed by an ion implantation technique.
To form. Then, the MNOS transistor is completed according to a conventional method.

第3図は本発明の第2の実施例を説明するための、窒化
シリコン膜形成時のNH3とSiH2Cl2との流量比R
と窒化シリコン膜の厚さとの関連図である。
FIG. 3 is a flow rate ratio R of NH 3 and SiH 2 Cl 2 at the time of forming a silicon nitride film for explaining the second embodiment of the present invention.
FIG. 6 is a relational diagram between the thickness and the thickness of the silicon nitride film.

すなわち、第1図(a)〜(d)に示した第1の実施例
と同様に操作する際、窒化シリコン膜の膜厚t2′の領
域においては、流量比Rを10以下とし、次でt3′の
領域においては、流量比Rを次第に大きく(R≧10
0)して反応させ窒化シリコン膜を形成する。
That is, when the same operation as in the first embodiment shown in FIGS. 1A to 1D is performed, the flow rate ratio R is set to 10 or less in the region of the film thickness t 2 ′ of the silicon nitride film. In the region of t 3 ′, the flow rate ratio R is gradually increased (R ≧ 10
0) and react to form a silicon nitride film.

この第2の実施例では、非常に書き込みやすく、かつ記
憶特性についても考慮された窒化シリコンを有するゲー
ト絶縁膜が形成されるため、低電圧で書き込み可能であ
り、1回のみのプログラムの書き込みを行ういわゆるワ
ンタイムPROMには最適なメモリー特性が得られる利
点がある。
In the second embodiment, since the gate insulating film having silicon nitride, which is very easy to write and the memory characteristic is taken into consideration, is formed, it is possible to write at a low voltage, and it is possible to write the program only once. The so-called one-time PROM has an advantage that optimum memory characteristics can be obtained.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、酸化シリコン膜と窒化シ
リコン膜からなるゲート絶縁膜を有するMIS型不揮発
性メモリーにおいて、窒化シリコン膜の組成を連続的に
変化させて形成することにより、メモリー特性を向上さ
せることができる効果がある。
As described above, according to the present invention, in a MIS type nonvolatile memory having a gate insulating film composed of a silicon oxide film and a silicon nitride film, the composition of the silicon nitride film is continuously changed to form a memory characteristic. There is an effect that can be improved.

【図面の簡単な説明】[Brief description of drawings]

第1図(a)〜(d)は、本発明の第1の実施例を説明
するための工程順に示した半導体チップの断面図、第2
図は第1の実施例における窒化シリコン膜形成時の反応
ガスの流量比と膜厚との関連図、第3図は本発明の第2
の実施例の窒化シリコン膜形成時の反応ガスの流量比と
膜厚との関連図である。 1…シリコン基板、2…フィールド酸化膜、3…酸化シ
リコン膜、4…窒化シリコン膜、5…多結晶シリコン
膜、5A…ゲート電極、6…ソース・ドレイン領域。
1 (a) to 1 (d) are sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing the relationship between the flow rate ratio of the reaction gas and the film thickness when the silicon nitride film is formed in the first embodiment, and FIG. 3 is the second diagram of the present invention.
FIG. 6 is a diagram showing the relationship between the flow rate ratio of the reaction gas and the film thickness when the silicon nitride film is formed in the example of FIG. 1 ... Silicon substrate, 2 ... Field oxide film, 3 ... Silicon oxide film, 4 ... Silicon nitride film, 5 ... Polycrystalline silicon film, 5A ... Gate electrode, 6 ... Source / drain region.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に形成された酸化シリコン膜
と窒化シリコン膜の2層からなるゲート絶縁膜とこのゲ
ート絶縁膜上に設けられたゲート電極とを有するMIS
型不揮発性メモリーにおいて、前記窒化シリコン膜の組
成は深さ方向に連続的に変化し少くとも前記ゲート電極
に近づくほど窒素濃度が高くなっていることを特徴とす
るMIS型不揮発性メモリー。
1. A MIS having a gate insulating film formed of two layers of a silicon oxide film and a silicon nitride film formed on a semiconductor substrate, and a gate electrode provided on the gate insulating film.
Type non-volatile memory, wherein the composition of the silicon nitride film continuously changes in the depth direction, and the nitrogen concentration increases as it approaches at least the gate electrode.
【請求項2】半導体基板上に酸化シリコン膜と窒化シリ
コン膜を順次形成したのちパターニングして酸化シリコ
ン膜と窒化シリコン膜の2層からなるゲート絶縁膜を形
成するMIS型不揮発性メモリーの製造方法において、
反応ガスの流量比を変えるCVD法により前記窒化シリ
コン膜を連続的に組成を変化させて形成することを特徴
とするMIS型不揮発性メモリーの製造方法。
2. A method of manufacturing a MIS non-volatile memory in which a silicon oxide film and a silicon nitride film are sequentially formed on a semiconductor substrate and then patterned to form a gate insulating film composed of two layers of a silicon oxide film and a silicon nitride film. At
A method of manufacturing a MIS type non-volatile memory, characterized in that the silicon nitride film is formed by continuously changing the composition by a CVD method in which a flow rate ratio of a reaction gas is changed.
JP62200323A 1987-08-10 1987-08-10 MIS type nonvolatile memory and method of manufacturing the same Expired - Lifetime JPH0642550B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62200323A JPH0642550B2 (en) 1987-08-10 1987-08-10 MIS type nonvolatile memory and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62200323A JPH0642550B2 (en) 1987-08-10 1987-08-10 MIS type nonvolatile memory and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPS6442867A JPS6442867A (en) 1989-02-15
JPH0642550B2 true JPH0642550B2 (en) 1994-06-01

Family

ID=16422386

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62200323A Expired - Lifetime JPH0642550B2 (en) 1987-08-10 1987-08-10 MIS type nonvolatile memory and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JPH0642550B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7607189B2 (en) 2004-07-14 2009-10-27 Colgate-Palmolive Oral care implement

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5924547B2 (en) * 1976-11-04 1984-06-09 ソニー株式会社 nonvolatile memory transistor
JPS5834978A (en) * 1981-08-26 1983-03-01 Matsushita Electronics Corp Semiconductor memory unit
JPS5867072A (en) * 1981-10-16 1983-04-21 Nec Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS6442867A (en) 1989-02-15

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