JP2001189390A - Method for fabricating semiconductor nonvolatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for fabricating a semiconductor nonvolatile memory, in which the density of charge trap contained in a silicon nitride film composing the multilayer insulation film of the semiconductor nonvolatile memory having charge storage capability can be controlled. SOLUTION: A silicon oxide film 21 is formed on a semiconductor substrate 10, having a channel forming region and a silicon nitride film 22, is formed thereon as a part of a multilayer insulation film by CVD, using dichlorosilane and ammonia as material. It is then heat treated in gas atmosphere containing hydrogen and nitrogen, e.g. ammonia gas, and further heat treated in the atmosphere of N2O gas. Subsequently, a silicon oxide film 23 is formed on the surface of the silicon nitride film 22 through thermal oxidation thus forming a multilayer insulation film of an oxide film-a nitride film-an oxide film having charge storage capability. Thereafter, a control gate electrode is formed on the upper layer of the multilayer insulation film and a source/drain region is formed to be connected with a channel-forming region in the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor nonvolatile memory device, and more particularly to a method for manufacturing a semiconductor nonvolatile memory device having a laminated insulating film having a charge storage function between a gate electrode of a transistor and a channel formation region. About the method.

[0002]

2. Description of the Related Art Instead of a magnetic storage device such as a floppy disk, an electrically rewritable semiconductor nonvolatile storage device (EEPROM: Electrically Erasable and Prog
rammable ROM) has begun to be used. As an EEPROM, a floating gate type, MNOS type or M
Structures having various features such as an ONOS type and a TEXTURED POLY type have been developed.

One type of EEPROM is a MONOS type storage device. The MONOS type storage device is, for example, shown in FIG.
Has the structure shown in FIG. In the figure, a memory transistor is formed in a left region. That is, the first insulating film 21 made of, for example, silicon oxide is formed on the p-type well 11 of the semiconductor substrate 10 separated by the element isolation insulating film 20.
a, a second insulating film 22a on the upper layer made of, for example, silicon nitride, and a third insulating film 22a on the upper layer made of, for example, silicon oxide.
An insulating film 23a is formed. By stacking these first to third insulating films, a stacked insulating film SI having a charge storage function is obtained. On the upper layer of the third insulating film 23a, a control gate electrode 30a made of, for example, polysilicon is formed. In the semiconductor substrate 10 on both sides of the control gate electrode 30a, an LDD (Lightly Doped Drain) diffusion layer 14 containing a low concentration of n-type conductive impurities and a source / drain diffusion layer containing a high concentration of n-type conductive impurities are provided. 1
5 are formed. As described above, an n-channel type field effect transistor having the laminated insulating film SI between the control gate electrode 30a and the channel formation region in the semiconductor substrate 10 is obtained. An interlayer insulating film 25 made of, for example, silicon oxide is formed to cover the control gate electrode 31a, and a contact hole reaching the source / drain diffusion layer 15 is opened to form a source / drain electrode 31.

On the other hand, a peripheral circuit transistor is formed in a region on the right side of FIG. That is, a gate insulating film 21a 'made of, for example, silicon oxide is formed on the p-type well 11' of the semiconductor substrate 10 separated by the element isolation insulating film 20, and a gate electrode 30a made of, for example, polysilicon is formed thereon. 'Has been formed.
In the semiconductor substrate 10 on both sides of the gate electrode 30a ', an LDD diffusion layer 14' containing an n-type conductive impurity at a low concentration and a source / drain diffusion layer 15 'containing a high concentration are formed. Have been. Further, the gate electrode 31
An interlayer insulating film 25 made of, for example, silicon oxide is formed so as to cover a ′, and the source / drain diffusion layer 15 ′ is formed.
Is formed, and a source / drain electrode 31 'is formed.

In the MONOS type memory device having the above-described structure, the laminated insulating film SI has a charge trap in the second insulating film 22a or a charge trap formed at the interface between the second insulating film 22a and the third insulating film 23a. It has the function of retaining electric charges. Control gate electrode 30a, semiconductor substrate 10
Source / drain diffusion layer 15 and semiconductor substrate 1
By applying an appropriate voltage to 0, a Fowler-Nordheim type tunnel current is generated, electrons are injected from the semiconductor substrate 10 into the laminated insulating film SI through the first insulating film 21a, and an electric field formed by the above voltage causes Conducts and is trapped in the trap level. Alternatively, conversely, the semiconductor substrate 1 is removed from the laminated insulating film SI through the first insulating film 21a.
Electrons are emitted to zero.

FIG. 1 is an equivalent circuit diagram of a semiconductor nonvolatile memory device in which the above memory transistors are connected in a NOR type.
(B). For example, the control gate electrode of the memory transistor of the cell 1 is the word line WL1, and the source / drain diffusion layers are connected to the bit lines BL1a and BL1b, respectively. As described above, the memory transistors connected to each line are connected in a matrix of NOR type to form a memory array.

When electric charges are accumulated in the above-mentioned laminated insulating film SI, an electric field is generated by the accumulated electric charges, so that the threshold voltage of the transistor changes. This change allows data to be stored. For example, when electrons are accumulated in the above-described laminated insulating film SI of the cell 1, the threshold voltage shifts in the positive direction if the transistor portion is an n-channel type. At the time of reading, a voltage is applied to the control gate electrode (word line WL1) of the corresponding memory cell. Since the threshold voltage of the transistor is higher than the applied voltage due to the charge accumulated in the laminated insulating film SI, both voltages are applied. No current flows between the bit lines BL1a and BL1b. Conversely, when holes are accumulated in the laminated insulating film SI, the threshold voltage is shifted in the negative direction,
Both bit lines BL1a, B1
A current flows between L1b. Data can be stored in such a manner that the current flows or does not flow in correspondence with “0” and “1”. From the above, the field-effect transistor including the stacked insulating film SI is a memory transistor that stores data.

A method of manufacturing the above-mentioned semiconductor non-volatile memory device having the MONOS structure will be described with reference to the drawings.
First, as shown in FIG.
For 0, an element isolation insulating film 20 made of silicon oxide is formed by, for example, the LOCOS method. Here, the active region on the left side of the drawing separated by the element isolation insulating film 20 is a memory transistor formation region, while the active region on the right side of the drawing is a peripheral circuit transistor formation region.

Next, as shown in FIG. 2B, the peripheral circuit transistor forming region is protected by a resist film or the like, and a conductive impurity is ion-implanted or a well is formed in the memory transistor forming region for adjusting a threshold value. For example, ion implantation for formation is performed. In the drawing, for example, a p-well 11
Is formed.

Next, as shown in FIG. 2C, a silicon oxide film is formed on the entire surface by, for example, a thermal oxidation method, and a first insulating film 21 is formed.

Next, as shown in FIG.
By a VD (Chemical Vapor Deposition) method, the first insulating film 21 on the active region is covered and silicon nitride is deposited on the entire surface to form a second insulating film 22.

Next, as shown in FIG. 3E, a silicon oxide film is formed by oxidizing the entire surface of the second insulating film 22 by, for example, a thermal oxidation method, and a third insulating film 23 is formed.

Next, as shown in FIG.
Polysilicon is deposited on the third insulating film 23 by the VD method, the resist film is patterned by a photolithography process, and etching such as RIE (reactive ion etching) is performed to form the control gate electrode 30a.
To form At this time, the laminated insulating film SI including the first insulating film 21a, the second insulating film 22a, and the third insulating film 23a and having a charge storage function is simultaneously patterned into a gate electrode pattern.

Next, as shown in FIG. 4 (g), the memory transistor forming region is protected by a resist film and etched by RIE or the like to form a first insulating film 21 and a second insulating film in the peripheral circuit transistor forming region. 22, and the third insulating film 2
3 is removed to expose the semiconductor substrate 10 in the peripheral circuit transistor formation region.

Next, as shown in FIG. 4H, the memory transistor forming region is protected by a resist film or the like, and conductive impurity ions are implanted into the peripheral circuit transistor forming region for adjusting the threshold value, or a well is formed. For example, ion implantation for formation is performed. In the drawing, for example, p-well 1
The case where 1 ′ is formed is shown. Next, a silicon oxide film is formed on the entire surface by, for example, a thermal oxidation method, and a gate insulating film 21 'for a peripheral circuit transistor is formed. At this time, also in the memory transistor formation region, the surface of the p well 11 on both sides of the control gate electrode 30a,
A silicon oxide film is also formed on the surface of control gate electrode 30a. Next, polysilicon is deposited by, for example, a CVD method and patterned by a photolithography process to form a gate electrode 30 for a peripheral circuit transistor.
forming a ′. Next, the control gate electrode 30
a, ion implantation using the gate electrode 30a 'as a mask,
LDD diffusion layer 1 containing n-type conductive impurities at low concentration
4, 14 'are formed.

In the subsequent steps, for example, silicon oxide is deposited by a CVD method and etched back to form a sidewall insulating film (not shown) on the side of the control gate electrode 30a and the gate electrode 30a '. Is used as a mask to form source / drain diffusion layers 15 and 15 ′ containing n-type conductive impurities at a high concentration. Thus, a memory transistor and a peripheral circuit transistor are formed. Next, these transistors are covered by, for example, a CVD method, and silicon oxide is deposited on the entire surface to form an interlayer insulating film 25.
5, 15 'are opened, and a conductive film of an aluminum alloy or the like is deposited by, for example, a sputtering method, and is patterned to form a source / drain electrode 3.
1 to form the semiconductor nonvolatile memory device shown in FIG.

As a prior art relating to a method for controlling the charge trap density at the time of forming a silicon nitride film in the above-described method for manufacturing a semiconductor nonvolatile memory device, see, for example,
The method described in JP-A-6562 is known. That is, the charge trap density is increased or decreased by changing the mixing ratio of the source gases when forming the silicon nitride film and changing the chemical composition ratio of the formed silicon nitride film.

[0018]

However, the accumulation of charges by the above-mentioned laminated insulating film is performed by a charge trap existing in the bulk of the insulating film and a charge trap existing at the interface between the insulating film and the insulating film. In the case where the element is miniaturized, the interface between the insulating films is reduced, and the bulk of the insulating film is also reduced in thickness, so that the number of charge traps is reduced. And it becomes difficult to store data.

When a memory transistor having a conventional structure is arranged as shown in FIG. 1B, the control gate electrode used for writing / erasing data and the control gate electrode accessed when reading data are the same. Therefore, the read voltage is also applied to the control gate electrode of the unselected memory transistor connected to the same word line as the memory transistor to be accessed when reading data. For example, when a read voltage is applied to the word line WL1 in order to read data of the cell 1 in FIG. 1B, the read voltage is applied to the control gate electrode also to the memory transistor of the cell 2 which is an unselected cell, and the control voltage is applied. A potential difference is generated between the gate electrode and the semiconductor substrate, the memory transistor of the cell 2 enters a weak write state, and the data of the unselected cell 2 is destroyed during the read operation of the cell 1. Hereinafter, this phenomenon is called disturb. There is a problem that the thinning of the laminated insulating film accompanying miniaturization tends to enhance the effect of the disturb.

The above disturb characteristics vary depending on the number of charge traps contained in the silicon nitride film bulk.
Generally, the larger the number of traps, the larger the change in signal amount immediately after writing and after disturbing. Therefore, simply increasing the number of traps (density) is a problem in realizing the device, and it is necessary to realize the optimal number of charge traps (density) depending on the dimensions of the element.

In the above-described method of increasing or decreasing the charge trap density by changing the chemical composition ratio of the silicon nitride film to be formed by changing the mixing ratio of the source gases at the time of forming the silicon nitride film, The growth rate and optical constants also change, and it is hard to say that changing and controlling the conditions at the manufacturing site is simple.

The present invention has been made in view of the above problems, and accordingly, the present invention provides a semiconductor nonvolatile memory device having a laminated insulating film having a charge storage function between a channel forming region and a control gate electrode. It is an object of the present invention to provide a method for manufacturing a semiconductor nonvolatile memory device capable of controlling a charge trap density contained in a silicon nitride film constituting a laminated insulating film.

[0023]

In order to achieve the above object, a method for manufacturing a semiconductor nonvolatile memory device according to the present invention has a laminated insulating film having a charge storage function between a channel forming region and a control gate electrode. A method for manufacturing a semiconductor non-volatile memory device, comprising: forming a laminated insulating film on a semiconductor substrate having a channel forming region; forming a control gate electrode on an upper layer of the laminated insulating film; Forming a source / drain region in the substrate so as to be connected to the substrate, wherein the step of forming the laminated insulating film includes a step of forming at least a silicon nitride film and a gas atmosphere containing at least hydrogen and nitrogen. And a heat treatment step for the silicon nitride film below.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, the heat treatment step in a gas atmosphere containing at least hydrogen and nitrogen is a heat treatment step in an ammonia gas atmosphere.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, preferably, the step of forming the laminated insulating film includes a heat treatment step in an N ₂ O gas atmosphere. More preferably, the step of forming the laminated insulating film further includes a heat treatment step in an N ₂ O gas atmosphere after the heat treatment step in a gas atmosphere containing at least hydrogen and nitrogen.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, preferably, in the step of forming the silicon nitride film, the silicon nitride film is formed by a chemical vapor deposition method using dichlorosilane and ammonia as raw materials. Form a film.

In the method for manufacturing a semiconductor nonvolatile memory device according to the present invention, preferably, the step of forming the stacked insulating film includes forming the first silicon oxide film before the step of forming the silicon nitride film. And forming the silicon nitride film on the first silicon oxide film. More preferably, the step of forming the laminated insulating film further includes a step of forming a second silicon oxide film on the silicon nitride film after the step of forming the silicon nitride film.

In the method of manufacturing a semiconductor nonvolatile memory device according to the present invention, a laminated insulating film is formed on a semiconductor substrate having a channel formation region. Here, in the step of forming the laminated insulating film, at least a silicon nitride film is formed by a chemical vapor deposition method using dichlorosilane and ammonia as raw materials, and the film is formed under a gas atmosphere containing hydrogen and nitrogen such as ammonia gas. Heat-treating the silicon nitride film,
Further, heat treatment is performed in an N ₂ O gas atmosphere. Next, a control gate electrode is formed on the laminated insulating film, and a source electrode is formed in the substrate so as to be connected to a channel formation region.
Forming a drain region;

According to the method of manufacturing a semiconductor nonvolatile memory device of the present invention, the nitriding is performed by a heat treatment in a gas atmosphere containing hydrogen and nitrogen such as ammonia gas and a heat treatment in an N ₂ O gas atmosphere. The number (density) of charge traps in the silicon film can be increased, and the density of charge traps contained in the silicon nitride film included in the stacked insulating film can be controlled. By forming the first silicon oxide film before forming the silicon nitride, MNO
An S-type semiconductor nonvolatile memory device can be manufactured,
Further, by forming a second silicon oxide film after forming a silicon nitride film, a MONOS type semiconductor nonvolatile memory device can be manufactured.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor nonvolatile memory device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1A is a sectional view of a MONOS type storage device according to this embodiment, which has a structure similar to that of a conventional example. In the figure, a memory transistor is formed in a left region. That is, on the p-type well 11 of the semiconductor substrate 10 separated by the element isolation insulating film 20, a first insulating film 21a made of, for example, silicon oxide, a second insulating film 22a made of, for example, silicon nitride, and an upper layer thereof A third insulating film 23a made of, for example, silicon oxide is formed. By stacking these first to third insulating films, a stacked insulating film SI having a charge storage function is obtained.

On the upper layer of the third insulating film 23a, a control gate electrode 30a made of, for example, polysilicon is formed. In the semiconductor substrate 10 on both sides of the control gate electrode 30a, an LDD (Lightly Doped Drain) diffusion layer 14 containing a low concentration of n-type conductive impurities and a source / drain diffusion layer containing a high concentration of n-type conductive impurities are provided. Fifteen
Are formed. As described above, an n-channel type field effect transistor having the laminated insulating film SI between the control gate electrode 30a and the channel formation region in the semiconductor substrate 10 is obtained. An interlayer insulating film 25 made of, for example, silicon oxide is formed to cover the control gate electrode 31a, and a contact hole reaching the source / drain diffusion layer 15 is opened.
1 is formed.

On the other hand, peripheral circuit transistors are formed in the region on the right side of FIG. That is, a gate insulating film 21a 'made of, for example, silicon oxide is formed on the p-type well 11' of the semiconductor substrate 10 separated by the element isolation insulating film 20, and a gate electrode 30a made of, for example, polysilicon is formed thereon. 'Has been formed.
In the semiconductor substrate 10 on both sides of the gate electrode 30a ', an LDD diffusion layer 14' containing a low concentration of n-type conductive impurities and a source / drain diffusion layer 15 'containing a high concentration are formed. Have been. Further, the gate electrode 31
An interlayer insulating film 25 made of, for example, silicon oxide is formed so as to cover a ′, and the source / drain diffusion layer 15 ′ is formed.
Is formed, and a source / drain electrode 31 'is formed.

In the MONOS type memory device having the above-described structure, the laminated insulating film SI has a charge trap in the second insulating film 22a and a charge trap formed at the interface between the second insulating film 22a and the third insulating film 23a. It has the function of retaining electric charges. Control gate electrode 30a, semiconductor substrate 10
Source / drain diffusion layer 15 and semiconductor substrate 1
By applying an appropriate voltage to 0, a Fowler-Nordheim type tunnel current is generated, electrons are injected from the semiconductor substrate 10 into the laminated insulating film SI through the first insulating film 21a, and an electric field formed by the above voltage causes Conducts and is trapped in the trap level. Alternatively, conversely, the semiconductor substrate 1 is removed from the laminated insulating film SI through the first insulating film 21a.
Electrons are emitted to zero.

FIG. 1 is an equivalent circuit diagram of a semiconductor nonvolatile memory device in which the above memory transistors are connected in a NOR type.
(B). For example, the control gate electrode of the memory transistor of the cell 1 is the word line WL1, and the source / drain diffusion layers are connected to the bit lines BL1a and BL1b, respectively. As described above, the memory transistors connected to each line are connected in a matrix of NOR type to form a memory array.

When electric charges are accumulated in the above-mentioned laminated insulating film SI, an electric field is generated by the accumulated electric charges, so that the threshold voltage of the transistor changes. This change allows data to be stored. For example, when electrons are accumulated in the above-described laminated insulating film SI of the cell 1, the threshold voltage shifts in the positive direction if the transistor portion is an n-channel type. At the time of reading, a voltage is applied to the control gate electrode (word line WL1) of the corresponding memory cell. Since the threshold voltage of the transistor is higher than the applied voltage due to the charge accumulated in the laminated insulating film SI, both voltages are applied. No current flows between the bit lines BL1a and BL1b. Conversely, when holes are accumulated in the laminated insulating film SI, the threshold voltage is shifted in the negative direction,
Both bit lines BL1a, B1
A current flows between L1b. Data can be stored in such a manner that the current flows or does not flow in correspondence with “0” and “1”. From the above, the field-effect transistor including the stacked insulating film SI is a memory transistor that stores data.

A method of manufacturing the above-mentioned semiconductor nonvolatile memory device having the MONOS structure will be described with reference to the drawings.
First, as shown in FIG.
For 0, an element isolation insulating film 20 made of silicon oxide is formed by, for example, the LOCOS method. Here, the active region on the left side of the drawing separated by the element isolation insulating film 20 is a memory transistor formation region, while the active region on the right side of the drawing is a peripheral circuit transistor formation region.

Next, as shown in FIG. 2B, the peripheral circuit transistor forming region is protected by a resist film or the like, and a conductive impurity is ion-implanted into the memory transistor forming region for adjusting the threshold value or a well is formed. For example, ion implantation for formation is performed. In the drawing, for example, a p-well 11
Is formed.

Next, as shown in FIG. 2C, a silicon oxide film is formed on the entire surface by, for example, a thermal oxidation method to form a film of 0.5 to 3.5 n.
Then, the first insulating film 21 is formed.

Next, as shown in FIG. 3D, CVD (Chemic) using, for example, dichlorosilane and ammonia as raw materials.
al Vapor Deposition) to cover the first insulating film 21 on the active region and cover the entire surface with silicon nitride of 2 to 10 nm.
And a second insulating film 22 is formed. next,
For the second insulating film 22, as a gas containing hydrogen and nitrogen,
For example, heat treatment is performed at a temperature of 850 to 950 ° C. for 30 to 90 seconds in an ammonia gas atmosphere. The number of charge traps (density) in the second insulating film 22 (silicon nitride film) can be increased by the heat treatment in an ammonia gas atmosphere.

Further, as the above heat treatment, for example, after the above heat treatment in an ammonia gas atmosphere, for example, N ₂
Heat treatment may be performed at a temperature of 950 ° C. for 30 seconds in an O gas atmosphere, whereby a deep charge trap level can be introduced into the interface between the nitride film and the oxide film.

Next, as shown in FIG. 3E, the surface of the second insulating film 22 is entirely oxidized by, for example, a thermal oxidation method, or a silicon oxide film is formed on the second insulating film 22 by a CVD method. Is formed, and a third insulating film 23 is formed.

Next, as shown in FIG.
Polysilicon is deposited on the third insulating film 23 by the VD method, the resist film is patterned by a photolithography process, and etching such as RIE (reactive ion etching) is performed to form the control gate electrode 30a.
To form At this time, the stacked insulating film SI having the charge storage function, which includes the first insulating film 21a, the second insulating film 22a, and the third insulating film 23a, is simultaneously patterned into a gate electrode pattern.

Next, as shown in FIG. 4G, the memory transistor formation region is protected by a resist film and etched by RIE or the like to form a first insulation film 21 and a second insulation film in the peripheral circuit transistor formation region. 22, and the third insulating film 2
3 is removed to expose the semiconductor substrate 10 in the peripheral circuit transistor formation region.

Next, as shown in FIG. 4 (h), the memory transistor formation region is protected by a resist film or the like, and conductive impurity ions are implanted into the peripheral circuit transistor formation region for adjusting the threshold value, or a well is formed. For example, ion implantation for formation is performed. In the drawing, for example, p-well 1
The case where 1 ′ is formed is shown. Next, a silicon oxide film is formed on the entire surface by, for example, a thermal oxidation method, and a gate insulating film 21 'for a peripheral circuit transistor is formed. At this time, also in the memory transistor formation region, the surface of the p well 11 on both sides of the control gate electrode 30a,
A silicon oxide film is also formed on the surface of control gate electrode 30a. Next, polysilicon is deposited by, for example, a CVD method and patterned by a photolithography process to form a gate electrode 30 for a peripheral circuit transistor.
forming a ′. Next, the control gate electrode 30
a, ion implantation using the gate electrode 30a 'as a mask,
LDD diffusion layer 1 containing n-type conductive impurities at low concentration
4, 14 'are formed.

In the subsequent steps, for example, silicon oxide is deposited by the CVD method and etched back to form a sidewall insulating film (not shown) on the side of the control gate electrode 30a and the gate electrode 30a '. Is used as a mask to form source / drain diffusion layers 15 and 15 ′ containing n-type conductive impurities at a high concentration. Thus, a memory transistor and a peripheral circuit transistor are formed. Next, these transistors are covered by, for example, a CVD method, and silicon oxide is deposited on the entire surface to form an interlayer insulating film 25.
5, 15 'are opened, and a conductive film of an aluminum alloy or the like is deposited by, for example, a sputtering method, and is patterned to form a source / drain electrode 3.
1 to form the semiconductor nonvolatile memory device shown in FIG.

According to the method of manufacturing a semiconductor nonvolatile memory device according to the present embodiment, a method of manufacturing a semiconductor nonvolatile memory device having a laminated insulating film having a charge storage function between a channel formation region and a control gate electrode In the above, the semiconductor nonvolatile memory device can be manufactured by controlling the charge trap density contained in the silicon nitride film forming the laminated insulating film.

Second Embodiment The semiconductor non-volatile memory device according to the second embodiment is substantially the same as the semiconductor non-volatile memory device according to the first embodiment. This is an MNOS type semiconductor nonvolatile memory device including a first insulating film 21a made of and a second insulating film 22a made of, for example, silicon nitride on the first insulating film 21a.

The semiconductor non-volatile memory device according to the above-described embodiment does not include the third insulating film 23 except that the third insulating film 23 is not formed.
It can be formed in the same manner as in the first embodiment. That is, after forming the second insulating film (silicon nitride film), the second insulating film 22 is subjected to a gas containing hydrogen and nitrogen, for example, in an ammonia gas atmosphere at a temperature of 850 to 950 ° C. for 30 to 90 ° C.
A heat treatment is performed for 90 seconds, and further, for example, a heat treatment is performed for 30 seconds at a temperature of 950 ° C. in an N ₂ O gas atmosphere. By the heat treatment in the above-mentioned ammonia gas atmosphere, the second insulating film 2 is formed.
2 (silicon nitride film) can increase the number (density) of charge traps, and a heat treatment in an N ₂ O gas atmosphere can introduce a deep charge trap level into the interface between the nitride film and the oxide film. it can.

According to the method for manufacturing a semiconductor nonvolatile memory device according to the present embodiment, as in the first embodiment, a laminated insulating film having a charge storage function is provided between a channel formation region and a control gate electrode. In the method for manufacturing a semiconductor nonvolatile memory device, the charge trap density included in the silicon nitride film included in the stacked insulating film can be controlled to manufacture the semiconductor nonvolatile memory device.

Example 1 A sample of a MONOS type transistor was manufactured by the method for manufacturing a semiconductor nonvolatile memory device according to the first embodiment. That is, after the p-well 11 is formed in the n-type silicon semiconductor substrate 10, the first insulating film 21 of a silicon oxide film having a thickness of 1 nm is formed by a thermal oxidation method.
Which is formed from dichlorosilane and ammonia
The second insulating film 22 of silicon nitride was formed to a thickness of 8 nm by the VD method. Next, in an ammonia gas atmosphere, 9
After performing a heat treatment at a temperature of 50 ° C. (for 30 seconds, 60 seconds or 90 seconds), the heat treatment is subsequently performed under an N ₂ O gas atmosphere for 9 seconds.
Heat treatment was performed at a temperature of 50 ° C. for 30 seconds. Next, a third insulating film 23 is formed by oxidizing the entire surface of the second insulating film 22 by a thermal oxidation method, and polysilicon is deposited on the third insulating film 23 by a CVD method.
0a, a first insulating film 21a, a second insulating film 22a,
The laminated insulating film SI having a charge storage function and made of the third insulating film 23a was simultaneously patterned into a gate electrode pattern. Next, phosphorus is ion-implanted using the control gate electrode 30a as a mask to form the LDD diffusion layer 14, and further, a side wall insulating film is formed on the side of the laminated insulating film SI and the control gate electrode 30a, and this is used as a mask. The source / drain diffusion layer 15 is implanted with phosphorus ions.
Was formed.

For the sample of the MONOS transistor obtained above, a silicon nitride film (second insulating film 22
a) The electron current component of the Pool-Frenkel current flowing inside was measured at a constant electric field. FIG. 5 shows that the amount proportional to the number of charge traps obtained from the intercept of the Arrhenius plot of the above measurement results was determined by measuring the amount of heat treatment time (3
0 second, 60 seconds, and 90 seconds). From this figure, it was confirmed that the number of charge traps increased as the heat treatment time in an ammonia gas atmosphere was increased.

(Embodiment 2) The M created in the above-described embodiment 1
A sample of an ONOS transistor (a heat treatment time in an ammonia gas atmosphere is 30 seconds) and a heat treatment on a silicon nitride film (second insulating film 22a) in an ammonia gas atmosphere and an N ₂ O gas atmosphere separately from the above. The capacitance-gate voltage characteristics (C-
V characteristic) was measured. FIG. 6 shows the results. In the MONOS transistor, the capacitance C is changed between when the gate voltage Vg is changed to the high voltage side and when the gate voltage Vg is changed to the low voltage side.
Exhibit different hysteresis, and the magnitude of the shift amount of the flat band (the width indicated by the arrow in the figure) corresponds to the accumulated charge signal amount. As shown in FIG. 6, it was confirmed that the amount of the accumulated charge signal was increased by performing the heat treatment in the ammonia gas atmosphere and the N ₂ O gas atmosphere.

The method for manufacturing a semiconductor nonvolatile memory device of the present invention is not limited to the above embodiment. For example, the control gate electrode has a single layer, but may have a multilayer structure such as polycide. Also, as a laminated insulating film,
Any laminated insulating film including at least a silicon nitride film may be used, and the present invention can be applied to a laminated insulating film of oxide film-nitride film-oxide film or a laminated insulating film of oxide film-nitride film. Further, the source / drain diffusion layers may have a structure other than the LDD structure. NOR type, DINOR as a semiconductor memory device
Type, NAND type, etc. Further, the injection of charges into the laminated insulating film may be performed in any case of writing or erasing data. In addition, various changes can be made without departing from the gist of the present invention.

[0055]

According to the method of manufacturing a semiconductor nonvolatile memory device of the present invention, in the method of manufacturing a semiconductor nonvolatile memory device having a laminated insulating film having a charge storage function between a channel formation region and a control gate electrode, The semiconductor nonvolatile memory device can be manufactured by controlling the charge trap density included in the silicon nitride film included in the stacked insulating film.

[Brief description of the drawings]

FIG. 1A is a cross-sectional view of a semiconductor nonvolatile memory device according to the present invention and a conventional example, and FIG. 1B is an equivalent circuit diagram of the semiconductor nonvolatile memory device.

FIG. 2 is a sectional view showing a manufacturing process of a method for manufacturing a semiconductor nonvolatile memory device according to the present invention and a conventional example;
(A) shows up to the step of forming the element isolation insulating film layer, (b) shows the step of forming the well, and (c) shows the step of forming the first insulating film.

FIG. 3 is a sectional view showing a step subsequent to that of FIG. 2;
(D) shows the steps up to the step of forming the second insulating film, (e) shows the steps up to the step of forming the third insulating film, and (f) shows the steps up to the step of forming the control gate electrode pattern.

FIG. 4 is a sectional view showing a step subsequent to that of FIG. 3;
(G) shows up to the step of removing the laminated insulating film in the peripheral circuit transistor formation region, and (h) shows the step up to the step of forming the LDD diffusion layer.

FIG. 5 is a diagram showing the dependence of the number of charge traps of a semiconductor nonvolatile memory device manufactured by the method of manufacturing a semiconductor nonvolatile memory device of the present invention on the heat treatment time in an ammonia gas atmosphere.

FIG. 6 is a diagram showing capacitance-gate voltage characteristics (CV characteristics) of a semiconductor nonvolatile memory device manufactured by the method for manufacturing a semiconductor nonvolatile memory device of the present invention.

[Explanation of symbols]

10 ... semiconductor substrate, 11, 11 '... p well, 14 ... L
DD diffusion layer, 15: source / drain diffusion layer, 20: element isolation insulating film, 21, 21a: first insulating film, 22, 22
a: second insulating film, 23, 23a: third insulating film, 25: interlayer insulating film, 30: layer for control gate electrode, 30a
... Control gate electrode, 31, 31 ′ source / drain electrode, SI: laminated insulating film.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 27/115 F term (Reference) 5F001 AA14 AB02 AD17 AG02 AG21 AG30 AG40 5F058 BA20 BD02 BD04 BD10 BF02 BF24 BF29 BF30 BF63 BH05 BJ01 BJ10 5F083 EP18 EP22 EP77 ER11 GA30 PR33 ZA07 5F101 BA46 BB02 BD07 BH02 BH03 BH16 BH21

Claims (7)

[Claims] 1. A method for manufacturing a semiconductor nonvolatile memory device having a laminated insulating film having a charge storage function between a channel forming region and a control gate electrode, wherein the laminated insulating film is formed on a semiconductor substrate having a channel forming region. Forming a control gate electrode in an upper layer of the laminated insulating film; and forming a source / drain region in the substrate so as to be connected to the channel formation region. A method for manufacturing a semiconductor nonvolatile memory device, wherein the step of forming an insulating film includes a step of forming at least a silicon nitride film and a heat treatment step for the silicon nitride film in a gas atmosphere containing at least hydrogen and nitrogen. 2. The method for manufacturing a semiconductor nonvolatile memory device according to claim 1, wherein said heat treatment step in a gas atmosphere containing at least hydrogen and nitrogen is a heat treatment step in an ammonia gas atmosphere. 3. The method according to claim 1, wherein the step of forming the laminated insulating film comprises N ₂ O
2. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1, further comprising a heat treatment step in a gas atmosphere. 4. The method according to claim 3, wherein the step of forming the laminated insulating film further includes a heat treatment step in an N ₂ O gas atmosphere after the heat treatment step in a gas atmosphere containing at least hydrogen and nitrogen. Manufacturing method of a semiconductor nonvolatile memory device. 5. The step of forming the silicon nitride film, wherein the silicon nitride film is formed by a chemical vapor deposition method using dichlorosilane and ammonia as raw materials.
The manufacturing method of the semiconductor nonvolatile memory device described in the above. 6. The step of forming the laminated insulating film further includes a step of forming a first silicon oxide film before the step of forming the silicon nitride film, and in the step of forming the silicon nitride film, 2. The method according to claim 1, wherein the method is performed on the first silicon oxide film. 7. The method according to claim 6, wherein the step of forming the laminated insulating film further includes a step of forming a second silicon oxide film on the silicon nitride film after the step of forming the silicon nitride film. A method for manufacturing a semiconductor nonvolatile memory device.